JPS59134835A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the section of a through hole in a tapered shape by varying a substrte bias to gradually alter the quality of an interlayer insulating film when forming the film by an RF sputtering, thereby flattening the stepwise difference of the surface. CONSTITUTION:An Si substrate formed with wirings 2 is contained in an RF sputtering device, and an SiO2 film 3 is accumulated while gradually approaching a large negative bias voltage to 0. Then through holes 4 are formed by photolithographic technique and wet etching. Since the film accumulated by larger negative bias voltage has smaller etching rate, the section of the hole becomes in a tapered shape. Then, a resist 20 is removed, and upper layer electrode wirings 5 are superposed on the flattened interlayer insulating film 3. According to this configuration, the disconnection of the electrode wirings can be prevented without increasing a particularly equipment and steps.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device and a method of forming an interlayer insulating film of multilayer metal wiring.

Conventional 11-layer insulating films are formed by growing silicon oxide or phosphorus glass on electrode wiring made of AlSi alloy at a temperature of about 480°C by CVD using SiH4 and 02 as material scraps. Ta. FIG. 1 is a sectional view showing one step in this manufacturing method. As shown in FIG. 1 (5), the silicon oxide film or linker gland (3) formed on the electrode wiring (2) has poor step coverage in the rocky part of the turtle distribution.

Therefore, as shown in FIG. 1 (8), when forming a second layer of electrode wiring (5) on top of it, it had the disadvantage of being easily disconnected.To improve this point, conventional CVD Low-pressure CVD, plasma CVD, etc. have been used instead, but they seem to be insufficient for areas with large steps.Please note (1)
is the S1\base.

- In the oxidized silicon film formed by the RF sputtering link to which a substrate bias can be applied, good step coverage is restored due to the sputtering effect of Ar'' ions. Figure 2 shows the fabrication of one semiconductor device by this RF sputtering. 2 is a cross-sectional view showing one piece of wire in the method. Due to the gentle step coverage shown in FIG. 2 (8), there are few breaks in the second layer electrode wiring as shown in FIG. 2 (B).

However, as shown in both Figures 1 and 2, the first
The through hole (4) that connects the electrode wiring of the layer and the electrode wiring of the second layer is I? It is formed by reprint making and etching after the m-image formation. Depending on the etching method, through-holes carved using reactive ion etching have a steeply sloped cross-sectional shape.・In such a steeply sloped small hole, the second X pentode deposit material is deposited, but it begins to be deposited from the top of the side wall and the center of the first half.

Disconnection is likely to occur at the lower part of the r*+r wall, which is a big problem even with the NOEA IIJ+ film produced by RF sputtering, which has good step coverage at the h difference part of the electrode wiring.

In addition, the through-hole shape formed by wet etching has a slightly sloped side wall.

There may be a slight disconnection rate, but in either case, the unevenness is severe, and the electrical shelf distribution is in the same order of magnitude.

Furthermore, it has been an obstacle to forming multilayer '<<& wiring.

Ko (7) s In the case of multi-leg; To provide a half-tied body armor 1 nail that has an insulating interlayer film that can prevent disconnection and short circuit of electrode wiring by renovating the station sopka range in an RFI part and opening a tapered through hole. This is what I call "J".

Hereinafter, the method of forming a through hole based on this research will be explained with reference to an example shown in FIG. 3. First, semiconductor M
@ It is assumed that the first electrode wiring (2) has been completed in (1). Next, set the base bias voltage to a large negative value (Ill
A silicon oxide film is deposited using RF sputtering at a temperature of 100%, and the bias voltage is gradually brought closer to 0 to complete the deposition. The silicon oxide film formed at this time is (3) and (6). After this, through-holes are carved using Yoma platemaking technology and wet etching method (B
). Flattened I-Second electrician 46 l
! '16% (4) By the step of depositing (0° or more), a multilayer wiring with good step coverage in the gap portion of the electrode wiring and having a tapered through hole is formed.

Here, the good is the resist after development.

The principle diagram of the RF sputtering equipment used is shown in 4j.
Show to the prisoner. (6n is RF electric disappearance, (7) is Sin, target, (81ch RF bias KidM, (9)
x/1-, QQ indicates Δr゛brasma.

When depositing silicon oxide IpM using this RF sputtering %f&, the 1v-1 relationship between the b' voltage applied to the -$J board and the etching rate of the glands generated by that voltage is shown in Figure 5. The result will be 0. This leap (
I1% deposited at a large negative trt pressure has a small etching rate, as is the case with yarn.

This is thought to be because the Ar' ions applied with a negative voltage attack the silicon oxide film, resulting in a dense film. Therefore, a film formed by depositing a silicon oxide film with a high negative bias voltage and a silicon oxide film with a high negative bias voltage, if a through hole is opened there by etching. As time passes, side etch becomes large in the upper layer, and the side etch becomes smaller toward the bottom (11) parts. Therefore, by properly controlling the base biasing BE,
The opening of the through pole can be tapered and smooth (see FIG. 3).

In this way, the tapered through-hole has been extended, and the second and second wires are connected to the lower dove without being disconnected at the through-hole part, and the entire surface is flattened. Therefore, it is very easy to decide what to do with the wiring on the upper layer.

Generally, when the substrate bias voltage for RF sputtering is low, the step coverage is poor; however, if the substrate bias voltage is deposited at a large value at the beginning of R, as in the present invention, good coverage is obtained ( '4, even if the base bias is reduced to %, the coverage will remain good with almost no change.Therefore, the step coverage will not be bad.

In addition, in the above explanation, the electrical wiring of tun 1 and the second electrical wiring 4!
0! Is the inter-office film between the wires using a little more than 1, or the 2nd
It may also be used for the interlayer film between the eighth electrode wires when providing the balls of other wires, and also for the upper layer interlayer film, and the same effects as in the above embodiments can be obtained.

As described above, according to the present invention, the RF scattering causes hazy 11
When forming the old model, set the paper board bias to a large negative value.
Starting from 1C1, I will gradually make Rei develop his skills.')
For Li++ib arrangement: It is possible to form an interlayer film with good step coverage at the gap and tapered full holes, which has the effect of preventing connection of the upper layer electrode wiring. . In addition, especially new equipment 11
The above effects can be obtained without much effort or workmanship, which is a huge advantage.

[Brief explanation of drawings]

Figure 1 is a Pr plane view showing the step coverage of the 11-layer film formed by the conventional 0CVD method and the 1-imaginary disconnection when the second layer electrode wiring is formed on the through hole, and Figure 2 is the conventional RF sputtering method. 1 (a) The step coverage of the interlayer film formed by the method and the disconnection state when the electrode C wiring of the i 2 It' layer is formed on the through hole are avoided. A sectional view showing a method for manufacturing a two-IPl powder distribution structure according to an embodiment, FIG. 4 is a travel map of the RF' sputtering equipment used in the present invention, and FIG. 5 is a diagram showing the dependence of etching rate on substrate bias voltage. It is a diagram. In the figure, (1)? Silicon base for electrode wiring, (2)
It's electric! i+! #Self-fitting, (3JhaJlffi navy blue JJl
llJ, (4J has/l/-hole, (5) is the second electrode wiring, 2) is the resist after development, (6) is the RF electron beam, (7) is the SiO□ target, (8j is the RF
(9J stands for wafer, 0 o'clock stands for Ar' plasma. In the figure, the same symbol stands for (Tsukasa-) or the corresponding part. Agent Haku Kiyono - Figure 3 (A) I' −1〜〜〜〜〜〜へ１１〜−−−−−〜〜−− (Go) ′ Maro〉〜−−−〜−−−−−−−〜−−−−−−−１１１ 111-Figure 4Figure 5 Mr. Commissioner of the Japan Patent Office 1. Indication of the case Japanese Patent Application No. 58-8969 2. Name of the invention Method for manufacturing a semiconductor device 3. Person making the amendment 5. Subject of ?ai positive Column 6 of Detailed Explanation of Hosobachi no Mitsukiri, Contents of Amendment (1) The detailed description will be corrected as shown.

Claims (1)

[Claims] RF
In the process of forming a silicon oxide film by sputtering, the negative bias voltage applied to the substrate is gradually changed from a large negative value to zero, thereby flattening the surface level and forming through-holes. 1. A method of manufacturing a semiconductor device, characterized in that the cross-sectional shape of the portion is tapered.