JPS6022343A - Multilayer interconnection structure of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To maintain the electrical stability and prevent the generation of hillocks by composing a layer insulating film on the 1st layer interconnection of a low temperature growing silicon nitride film and a silicon oxide system insulating film. CONSTITUTION:A layer insulating film on the 1st layer interconnection 3 is composed of a low temperature growing silicon nitride film 4 and a silicon oxide system insulating film 5. With this composition, generation of hillocks of the interconnection 3 is suppressed by the nitride film 4 immediately above and not generated. Even if a charging phenomenon is generated at the boundary between the nitride film 4 and the insulating film 5, a leakage current between diffusion layers due to a parasitic MIS type FET effect is not generated because of the blocking by a shielding effect of the interconnection 3 so that the electrical stability is assured.

Description

[Detailed description of the invention] The present invention relates to a multilayer wiring structure of a semiconductor integrated circuit device.

Traditionally, metal multilayer wiring has been mainly used in bipolar 2 devices, which are characterized by high-speed calculations, but in recent years, MIIIJII devices have also been used to achieve high-speed operation through short channels and large-scale devices with high wiring density. In order to increase the scale, double-layer metal wiring began to be put into practical use.

When performing multilayer wiring, especially when the first layer wiring is made of aluminum (hereinafter abbreviated as At), selection of the interlayer insulating film on the first layer wiring is important. Usually the growth temperature is about 400℃
A silicon oxide film produced by the multi-phase growth method is used. During the growth of this interlayer insulating film.

Ar1. Hillocks grow on the first layer wiring of the system. Since this hillock causes a decrease in yield due to a decrease in breakdown voltage between -8 and two-layer wiring and an increase in leakage between one layer, various studies have been made to prevent hillocks. Low-temperature-grown plasma nitride films are being researched as an effective means of preventing hillocks, but when a high voltage such as static electricity is applied, electricity accumulates at the interface between the plasma nitride film and the silicon oxide film, causing parasitic MIS FETs. It has drawbacks such as the generation of leakage current, so it is hardly used in MIS type devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved multilayer wiring structure that is electrically stable and free from pillock even when applied to MIS type devices.

According to the present invention, there is obtained a multilayer wiring structure for a semiconductor integrated circuit device, characterized in that the interlayer insulating film on the first layer wiring is composed of a silicon nitride film grown at a low temperature and a silicon oxide film-based insulating film.

Embodiments of the present invention will be described below with reference to the drawings.

1 to 4 are cross-sectional views showing the steps of obtaining the multilayer wiring structure of the present invention. As shown in FIG. 8i0
2 film 2 is formed, and 100OOO as the first layer wiring is formed on it.
An At film 3 with a thickness of about Next, as shown in FIG. 2, anisotropic etching techniques such as parallel plate plasma etching and reactive ion etching are used.

Plasma nitride film 4. The At film 3 is etched to form a first layer wiring. Thereafter, as shown in Figure 3, a 100OOA insulating film was formed using a multiphase growth method, plasma method, etc.
After depositing an 8i02 film or phosphor glass film 5 (the 8i02 film or phosphor glass film is referred to as a silicon oxide film insulating film) on the entire surface, a connection hole 6 between the first layer wiring lfM3 and the second layer wiring is formed. Open a hole. When forming the connection hole 6, it is preferable that the plasma nitride film 4 be etched by anisotropic etching without side etching. Next, as shown in FIG. 4, a second layer wiring 7 is deposited.

As is clear from the above example, the hillock of the first layer wiring is
Not only is it suppressed by the plasma nitride film 4 directly above it and does not occur, but it is also suppressed by the plasma nitride film 4 and the 8i02 film or l layer above it.
Even if a static electricity phenomenon occurs at the interface with the phosphor glass film 5, it will be blocked by the shielding effect of the lower first layer wiring, and the parasitic M
No leakage current between diffusion layers occurs due to the IS type FET effect, and there is no problem of electrical instability.

In the embodiment of the present invention, an At film was used as the wiring conductor, but it goes without saying that an At alloy film containing impurities such as 8i, Cu, and Fe may also be used.

Also, a silicon oxide film used as an insulating film between the eyebrows or
A phosphorus glass film is sometimes used in combination with a silicon oxide film by coating or a phosphorus glass film for flattening one surface, but it also includes such composite silicon oxide films and phosphorus glass films. .

According to the present invention, it is possible to obtain a multilayer wiring structure that is electrically stable and free from hillocks even when applied to MI8W devices.

[Brief explanation of drawings]

1 to 4 are cross-sectional views showing the order of manufacturing steps for explaining one embodiment of the present invention. In the figure, 1... silicon substrate, 2... silicon oxide film, 3... A/= film of first layer wiring, 4...
...Silicon nitride film by plasma growth method, 5...
...Silicon oxide film or ringer 2 film by multi-phase growth method, 6...Connection hole connecting between first layer wiring and second layer wiring, 7...Second layer wiring Layer wiring A/, membrane. iL/-:',':+-1' Agent Patent Attorney Uchihara “j,゛su?I 㑵・1 N〉?1 Figure Z to Figure 3 4th

Claims (1)

[Claims] Multilayer wiring structure 0 for a semiconductor integrated circuit device characterized in that the glabellar insulating film on the first layer wiring is composed of a low-temperature grown silicon nitride film and a silicon oxide film-based insulating film.