JPH04155823A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable an aluminum alloy electrode to be miniaturized for enhancing the reliability upon a semiconductor by a method wherein the plugs coated with a high melting point metal are formed in contact holes. CONSTITUTION:A P type well region 2, an N-type well region 3 and element isolating regions 4 comprising silicon dioxide films are formed on a P-type silicon substrate 1; an N-type impurity diffused layer 5 is formed on the P-type well region 2; while a P type impurity diffused layer 6 is formed on the N-type well region 3. Besides, an interlayer insulating film 7 comprising silicon dioxide film is formed on the main surface of the silicon substrate 1 while contact holes A, B are made on the positions above respective impurity diffused layers 5, 6. Furthermore, a titanium tungsten film 11 is formed on the whole surface while a polycrystalline silicon film 12 containing phosphorus is deposited on the surface of the film 12 and then etched back to be left only on the contact holes A, B so as to form polycrystalline silicon plugs 12a, 12b in respective holes A, B. Later, an aluminum alloy film 13 is deposited on the whole surface. Next, the aluminum alloy film 13 is etched away by photoetching step to form the pattern of an electrode wiring and later silicon nitride vacuum as the passivation film 8 of a semiconductor device is produced by plasma excited vapor deposition process.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention improves wiring density and reliability of metal wiring in high-density integrated circuit devices by preventing disconnection at contact holes. The purpose is to The present invention relates to a semiconductor device suitable for high density and a manufacturing method thereof.

(Prior Art) In recent years, MOS integrated circuit devices have become more dense and highly integrated. For example, dynamic RAMs are formed with a minimum dimension of 0.6 microns and have a large capacity of 16 megapits or more. One of the technical challenges for miniaturization is the improvement of microfabrication technology for electrodes and metal wiring. In particular, it is difficult to miniaturize metal wiring, typically made of aluminum alloys, and there are many technical challenges in forming wiring and electrodes in submicron patterns. The main technical problem is that the contact hole coverage of the aluminum alloy film deteriorates, resulting in unstable wiring connections and low reliability.

Next, FIG. 7 shows a conventional method for forming electrodes of a semiconductor integrated circuit device. The figure shows the part of the CMO5 electrode taken out from the diffusion layer formed on the semiconductor substrate.
FIG. 3 is a partial process cross-sectional view of the integrated circuit device.

In the same figure (a), 1 is a P-type silicon substrate, 2 is a P-type well region formed on the main surface of the silicon substrate, 3 is also an N-type well region, 4 is an element isolation region made of a silicon dioxide film, 5 is an N-type impurity diffusion layer formed in the P-type well region 2, 6 is a P-type impurity diffusion layer formed in the N-type well region 3, 7 is an interlayer insulation film made of a silicon dioxide film, and A and B are interlayer insulation layers. A contact hole formed in the film 7,
Two impurity diffusion layers 5.6 formed on silicon substrate 1
This is the electrode outlet from. Next, as shown in FIG. 3B, titanium tungsten 11, which is a high melting point metal, and aluminum alloy 13 are deposited by a well-known sputter deposition method. The area of contact holes A and B is 0.7×0.7 microns square.

Subsequently, as shown in the same figure (C), aluminum alloy 13,
After performing electrode patterning and sintering on the high melting point metal 11 using a well-known photolithography method, a passivation film 8 is formed.
A CMO5 integrated circuit device is fabricated by depositing.

(Problems to be Solved by the Invention) However, in the above conventional electrode forming method,
) As you can see, contact hole A.

The bottom corner of B is hardly covered with the aluminum alloy 13, and therefore microcracks are likely to occur. Further, since the inner walls of the contact holes A and B are only coated very thinly, there is a drawback that the step cover of the aluminum alloy 13 is poor and the reliability of the electrode is reduced.

Furthermore, as can be seen from the same figure (C), the passivation film 8
does not penetrate into contact holes A and B, so a gap is formed after the contact holes are opened.

These voids remain as voids, causing passivation cracks and poor moisture resistance. In particular, the contact hole area is 0.7X
If the contact hole has an aspect ratio of 0.7 microns or less or an aspect ratio of 1 or more, significant voids will occur, resulting in the above-mentioned adverse effects.

Therefore, in order to solve the above-mentioned drawbacks, a method for taking out the electrode through a microhole has been proposed, for example, by forming a plug of tungsten or polycrystalline silicon film in the contact hole after opening the contact hole. There are disadvantages in that there is high film stress, voids generated in contact holes cannot be completely removed, and it is difficult to etch back. Furthermore, it has been disclosed that such a selective growth method has many problems such as erosion of the silicon substrate (for example, Tsui MIC Conference, 1985, p. 350 VM
ICC0NF, P, 350.1985). Furthermore, when applying polycrystalline silicon plugs to a CMO8 integrated circuit device, when forming contacts to the P-type diffusion layer and the N-type diffusion layer, P-type impurities are added to each polycrystalline silicon film plug.

Alternatively, it is necessary to selectively decide which of the N-type impurities to supply, which complicates the process and poses many problems for practical use.

The present invention has been made in view of the above, and its purpose is to specifically enable the miniaturization of aluminum alloy electrodes,
The objective is to improve the reliability of semiconductor devices.

(Means for Solving the Problems) In order to achieve the above object, the present invention has a configuration in which a plug coated with a high melting point metal is formed in a contact hole.

In other words, the specific solution of the present invention is to provide a semiconductor substrate of one conductivity type, and a first conductivity layer formed on the semiconductor substrate and of the same conductivity type as the semiconductor substrate. a layer formed on the semiconductor substrate.

a second conductive layer having a conductivity type opposite to that of the first conductive layer; an interlayer insulating film that insulates between the first conductive layer and the second conductive layer; and an opening at a predetermined position of the interlayer insulating film. a contact hole formed in the interlayer insulating film and the contact hole, a first conductive film buried in the contact hole in contact with the high melting point metal, and on the first conductive film. The structure includes at least a second conductive film formed on the conductive film.

Further, in the invention described in claim (5), an interlayer insulating film is formed on one main surface of a semiconductor substrate, and a contact hole is opened at a predetermined position of the interlayer insulating film, and then the interlayer insulating film and the contact hole are opened. to form a high melting point metal, and then
forming a first conductive film containing one or more of phosphorus, arsenic, and boron on the high melting point metal; further forming a plug of the first conductive film in at least the contact hole; A second conductive film is formed on the melting point metal and the plug, and the second conductive film is etched to form an electrode pattern.

(Function) With the above configuration, in the present invention, the plug made of the first conductive film is located in the contact hole in a state covered with the high melting point metal, so there is no need to consider the erosion of the silicon substrate, and For the first conductive film, impurities of the same conductivity type are used regardless of whether they are P-type or N-type in the first and second conductive layers, and voids are reliably prevented and contact holes are formed in submicron size. Even if there is a problem, the electrode can be taken out stably.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a first embodiment of an aluminum alloy electrode structure of a semiconductor device according to the present invention. The figure shows CMO3
1 is a partial structural sectional view of an integrated circuit device, in which 1 is a P-type silicon substrate; 2 is a P-type silicon substrate formed on the main surface of the silicon substrate 1 and serving as a first conductive layer of the same conductivity type as the silicon substrate 1;
A type well region 3 is also formed on the main surface of the silicon substrate 1, and is an N type well region serving as a second conductive layer having a conductivity type opposite to that of the P type well region 2. Further, 4 is an element isolation region made of a silicon dioxide film, 5 is an N-type impurity diffusion layer formed in the P-type well region 2, and 6 is a P-type impurity diffusion layer formed in the N-type well region 3. Furthermore, 7 is the P
An interlayer insulating film made of a silicon dioxide film that insulates between the type well region 2 and the N-type well region 3; A and B are interlayer insulating films 7;
These are contact holes formed in the silicon substrate 1, and are electrode extraction ports from the two impurity diffusion layers 5.6 formed in the silicon substrate 1, respectively.

In addition, 11 is a titanium tungsten film as a refractory metal formed in the interlayer insulating film 7 and the contact holes A and H, and 12a and 12b are embedded in the contact holes A and B, respectively, and the lower end portions are formed of the titanium tungsten film. The first conductive film is in contact with the tungsten film 11 and constitutes a polycrystalline silicon plug. Further, 13 is the polycrystalline silicon plug 12a.

12b and an aluminum alloy film formed on the surface of the titanium-tungsten film 111, 8 is a passivation film.

The two polycrystalline silicon plugs 12a and 12b are both doped with N-type impurities, and are covered and surrounded by a titanium-tungsten film 11 and an aluminum alloy film 13.

Next, a first embodiment of the method for manufacturing the CMOS integrated circuit device shown in FIG. 1 is shown in process cross-sectional views in FIGS. 2(a) to 2(d). First, in the same figure (a), a P-type silicon substrate 1
, a P-type well region 2, an N-type well region 3, an element isolation region 4 made of a silicon dioxide film, an N-type impurity diffusion layer 5 in the P-type well region 2, and a P-type impurity diffusion layer 6 in the N-type well region 3.
form. Further, an interlayer insulating film 7 made of a silicon dioxide film is formed on the main surface of the silicon substrate 1, and contact holes A and B are opened between the interlayer insulating film 7 and above each of the impurity diffusion layers 5 and 6. do. Here, contact hole A,
The diameter of B is 0.6 microns.

Next, as shown in FIG. 6B, a titanium-tungsten film 11 is formed in the interlayer insulating film 7 and the contact holes A and B, and a polycrystalline silicon film 12 containing phosphorus is formed on the upper surface of the titanium-tungsten film 11. A film with a thickness of 0.5 microns is deposited by a low pressure vapor phase growth method using a well-known mixed gas of silane and phosphine. It is also possible to use a film containing arsenic or boron instead of phosphine for the polycrystalline silicon film 12. Alternatively, it is also possible to deposit polycrystalline silicon that does not contain impurities and dope this film with phosphorus as an impurity by ion implantation.

Subsequently, as shown in the same figure (c), a polycrystalline silicon film 12 is
Etch back contact hole A.

Polycrystalline silicon plugs 12a and 12b are formed by selectively leaving polycrystalline silicon film 12 only in area B. This etchback can be performed by a well-known plasma etching method using SF6 gas. After that, an aluminum alloy film 13 is deposited. This aluminum alloy film 13 is deposited to overlap the titanium tungsten film 11 and the polycrystalline silicon plugs 12a and 12b.

In addition, as shown in FIG. 3(d), the aluminum alloy film 13 is etched by a well-known photolithography method to form an electrode wiring pattern, and then a passivation film 8 of the semiconductor device is formed by plasma-enhanced vapor phase growth. A CMOS integrated circuit device is fabricated by forming a silicon nitride vacuum using a method.

Therefore, in the above embodiment, the contact resistance at the electrode lead-out portion is, for example, in connection with the P-type impurity diffusion layer 6, between the titanium tungsten film 11 and the polycrystalline silicon plug 1.
The total resistance of the three layers of 2b and the aluminum alloy film 13 is 200 to 220 Ω/piece under the hole size of 0.7×0, 7 square microns, and the resistance with the N-type impurity diffusion layer 5 is The connection was also 55-60Ω/piece.

The depth of contact holes A and B is from 0.5 microns to 1
．． The difference in each contact resistance is small between 5 microns.

Also, a polycrystalline silicon plug 12a.

Because of the presence of 12b, the coverage of the aluminum alloy film 13 at the step between the contact holes A and B is improved, so even if the contact holes A and B are submicron in size, voids can be reliably prevented from occurring. The electrode can be taken out stably and a reliable connection can be made.

Moreover, since the polycrystalline silicon plugs 12a and 12b are covered with the titanium-tungsten film 11, there is no need to consider erosion to the silicon substrate 1, and the N
Plug 12 of type impurity diffusion layer 5 and P type impurity diffusion layer 6
Both a and 12b can be constructed of N type, and the process can be simplified.

Note that in this embodiment, the polycrystalline silicon plugs 12a, 12
Although the side and bottom portions of b are covered with a titanium tungsten film 11, other high melting point metal films include a titanium/titanium nitride laminated film, metal silicide molybdenum silicide, and tungsten silicide.

Alternatively, a similar effect can be obtained using titanium silicide.

3 and 4 show a second embodiment of the present invention, FIG. 3 is a structural cross-sectional view of a CM OS integrated circuit device, and FIG. 4 is a cross-sectional view of the manufacturing process of the CM OS integrated circuit device shown in FIG. Show the diagram. In FIG. 3, 1 is a P-type silicon substrate, 2 is a P-type well region, 3 is also an N-type well region, 4 is an element isolation region, 5 is an N-type impurity diffusion layer, 6 is a P-type impurity diffusion layer,
7 is an interlayer insulating film, 31a and 31b are titanium tungsten films, 12c and 12d are polycrystalline silicon plugs, and 32a.

32b is a molybdenum silicide film, 13 is an aluminum alloy film, and 8 is a passivation film.

Both the polycrystalline silicon plugs 12a and 12b are doped with N-type impurities, the bottom and side surfaces of the contact holes are covered with titanium-tungsten films 31a and 31b, and the tops of the polycrystalline silicon plugs 12a and 12b are covered with a molybdenum silicide film 32a. , 32b and the aluminum alloy film 13.

Next, the manufacturing process of the CMOS integrated circuit device shown in FIG.
This will be explained based on the diagram. In the same figure (a), as in the first embodiment, a P-type silicon substrate 1 is provided with a P-type well region 2, an N-type well region 3, an element isolation region 4, an N-type impurity diffusion layer 5, and a P-type impurity. A diffusion layer 6 and an interlayer insulating film 7 made of a silicon dioxide film are formed, and contact holes A and B are formed in the interlayer insulating film 7. Next, as shown in FIG. 2B, a titanium-tungsten film 31 and a polycrystalline silicon film 12 containing phosphorus are deposited to a thickness of 0.5 microns.

The same effect can be obtained even if a polycrystalline silicon film containing boron is deposited as the polycrystalline silicon film 12.

Subsequently, as shown in the same figure (c), a polycrystalline silicon film 12 is
Etch back contact hole A.

Polycrystalline silicon plug 12a selectively only in B.

Leave 12b. At this time, if the titanium tungsten film 31 is also etched continuously, manufacturing becomes extremely easy. Further, as shown in FIG. 2D, a molybdenum silicide film 32 is deposited as another high melting point metal, and an aluminum alloy 13 is successively deposited thereon. The other high melting point metal may be the same titanium tungsten film as the titanium tungsten films 31a and 31b, or titanium silicide, tungsten silicide, etc. may be used instead of the molybdenum silicide film. Next, as shown in FIG. 3(e), the molybdenum silicide film 32 and the aluminum alloy 13 are simultaneously etched in the same process using a well-known photolithography method to form an electrode wiring pattern, and then the passivation film of the semiconductor device is etched. 8 to fabricate a CMOS integrated circuit device.

Therefore, in the CMOS integrated circuit device of this embodiment, almost the same resistance value as in the first embodiment can be obtained. In this embodiment, the membrane structure is slightly more complicated than in the first embodiment, but manufacturing is easier.

FIG. 5 shows a third embodiment of the invention. This figure shows a specific partial structural cross-sectional view of an integrated circuit device in which electrodes are simultaneously formed from polycrystalline silicon electrode wiring and an N-type diffusion layer.
is a P-type silicon substrate, 4 is an element isolation region, 5 is an N-type impurity diffusion layer, 41 is an N-type polycrystalline silicon wiring, 7 is an interlayer insulating film, 11 is a titanium-tungsten film, 12e and 12f are N-type polycrystalline silicon The plug, 13 is an aluminum alloy film, and 8 is a passivation film. Both the polycrystalline silicon plugs 12e and 12f are doped with N-type impurities, and the titanium-tungsten film 11 and the aluminum alloy film 1
It has a structure covered by 3.

Next, the method for manufacturing the CMOS integrated circuit device shown in FIG.
The explanation will be based on the manufacturing process cross-sectional diagram shown in the figure.

First, as shown in FIG. 5A, an element isolation region 4, an N-type impurity diffusion layer 5, a polycrystalline silicon wiring 41, and an interlayer insulating film 7 made of a silicon dioxide film are deposited on a P-type silicon substrate 1. As shown in (b), contact holes A and B
is formed on the interlayer insulating film 7.

Subsequently, a titanium tungsten film 11 and a polycrystalline silicon film 12 containing phosphorus are deposited to a thickness of 0.7 microns.

Then, as shown in FIG. 3(c), the polycrystalline silicon film 12
is etched back to selectively leave polycrystalline silicon plugs 12e and 12f only in contact holes A and B. Thereafter, as shown in FIG. 2D, an aluminum alloy 13 is deposited, and then an electrode wiring pattern is formed by a well-known photolithography method. Then, a passivation film 8 of the semiconductor device is formed (see FIG. 5), and the integrated circuit device shown in FIG. 5 is manufactured.

Therefore, in this embodiment, as in the above two embodiments, the coverage of the aluminum alloy film 13 at the step between contact holes A and B can be improved, so that the same effect as in the above two embodiments can be achieved. can get.

As shown in the above embodiments, there are two types of structures in which a polycrystalline silicon plug is covered with one type of high-melting point metal film such as titanium tungsten, and another in which the inner wall, bottom, or top of the contact hole is covered with a different type of film. It is possible to adopt two types of structures, and the same effect of the present invention can be obtained in either case.

(Effects of the Invention) As explained above, according to the semiconductor device and its manufacturing method of the present invention, a plug coated with a high melting point metal is formed in the contact hole, so that erosion to the silicon substrate is not taken into account. Instead, use a polycrystalline silicon plug and convert it into cNi.

When applied to an S-type integrated circuit device, the P-type diffusion layer,
Since impurities of the same conductivity type, whether N-type or not, are used, it is possible to reliably prevent voids from forming within the contact hole and disconnection of the alloy film, allowing stable extraction of the electrode.
It is possible to improve the reliability of the O3 integrated circuit device.

In particular, it is highly effective in forming electrodes in submicron-sized contact holes and in forming highly reliable electrodes in contact holes with high aspect ratios.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device showing a first embodiment of the present invention, FIG. 4 is a cross-sectional view of a semiconductor device showing the second embodiment; FIG. 4 is a process cross-sectional view explaining a method of manufacturing the semiconductor device of the second embodiment; FIG. 5 is a cross-sectional view of a semiconductor device showing the third embodiment. , FIG. 6 is a process cross-sectional view explaining the manufacturing method of the semiconductor device of the third embodiment, and FIG.
The figure is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device. 1... P-type silicon substrate, 2... P-type well region,
3... N-type well region, 4... Element isolation region, 5...
...N-type impurity diffusion layer, 6...P-type impurity diffusion layer, 7
...Interlayer insulating film, A, B...Contact hole, 1
1...Titanium tungsten film, 12a, 12b...
Polycrystalline silicon plug, 13...aluminum alloy. Patent applicant Matsushita Electronics Co., Ltd.

Claims (8)

[Claims] (1) A semiconductor substrate of one conductivity type, a first conductive layer formed on the semiconductor substrate and of the same conductivity type as the semiconductor substrate, and a first conductive layer formed on the semiconductor substrate and of a conductivity type opposite to that of the first conductive layer. a second conductive layer, an interlayer insulating film that insulates between the first conductive layer and the second conductive layer, a contact hole opened at a predetermined position in the interlayer insulating film, and the interlayer insulating film and A high melting point metal formed in the contact hole, a first conductive film buried in the contact hole in contact with the high melting point metal, and a second conductive film formed at least on the first conductive film. A semiconductor device comprising: (2) The semiconductor device according to claim (1), wherein the first conductive film has a structure surrounded by a high melting point metal and the second conductive film. (3) Claim (1) characterized in that the second conductive film has another high melting point metal located on the first conductive film.
). (4) The semiconductor device according to claim (1), wherein at least one of the first conductive film and the second conductive film is composed of a polycrystalline silicon film. (5) After forming an interlayer insulating film on one main surface of the semiconductor substrate and opening a contact hole at a predetermined position in the interlayer insulating film, forming a high melting point metal in the interlayer insulating film and the contact hole, and then , forming a first conductive film containing one or more of phosphorus, arsenic, and boron on the high melting point metal; further forming a plug of the first conductive film in at least the contact hole; A method of manufacturing a semiconductor device, comprising forming a second conductive film on a high melting point metal and the plug, and etching the second conductive film to form an electrode pattern. (6) The method for manufacturing a semiconductor device according to claim (5), wherein the second conductive film is made of an aluminum alloy. (7) The semiconductor device according to claim (5), wherein another high melting point metal is formed on the first conductive film, and a second conductive film is formed on the other high melting point metal. manufacturing method. (8) The method for manufacturing a semiconductor device according to claim (7), wherein the etching is performed on at least the other high-melting point metal and the second conductive film in one step.