JPS63205972A - Superconducting circuit device and its manufacture - Google Patents
Superconducting circuit device and its manufactureInfo
- Publication number
- JPS63205972A JPS63205972A JP62037802A JP3780287A JPS63205972A JP S63205972 A JPS63205972 A JP S63205972A JP 62037802 A JP62037802 A JP 62037802A JP 3780287 A JP3780287 A JP 3780287A JP S63205972 A JPS63205972 A JP S63205972A
- Authority
- JP
- Japan
- Prior art keywords
- tunnel barrier
- lower electrode
- upper wiring
- electrode
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000002887 superconductor Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 229910052758 niobium Inorganic materials 0.000 description 9
- 239000010955 niobium Substances 0.000 description 9
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 208000031481 Pathologic Constriction Diseases 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002821 niobium Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 208000037804 stenosis Diseases 0.000 description 1
- 230000036262 stenosis Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は超伝導回路装置の接合領域の構造及び製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a structure and manufacturing method of a bonding region of a superconducting circuit device.
（従来の技術）
超伝導回路装置に用いる接合領域の従来構造の一つ（第
一の従来技術）は例えば昭和６１年度電子通信学会総合
全国大会（３３０）２−８８に示されている。第４図に
示す如く、下部電極４３、トンネル障壁４４、及び上部
電極４６の平面形状が同じであり、従来この構規定及び
絶縁層４５の形成と加工工程が必要であった。(Prior Art) One of the conventional structures (first prior art) of a bonding region used in a superconducting circuit device is shown, for example, in the 1985 National Conference of the Institute of Electronics and Communication Engineers (330) 2-88. As shown in FIG. 4, the planar shapes of the lower electrode 43, tunnel barrier 44, and upper electrode 46 are the same, and conventionally, this structure and the formation and processing steps of the insulating layer 45 were required.
別の従来構造の一つ（第二の従来技術）は例えばエクス
テンディッドアブストラクツ第１８回コンフエレンスオ
ンソリッドスナイトデバイシイズアンドマテリアルス（
Ｅｘｔｅｎｄｅｄ Ａｂｓｔｒａｃｔｓ ｏｆ ｔｈｅ
１８ｔｈ（１９８６Ｉｎｔｅｒｎａｔｉｏｎａｌ）Ｃ
ｏｎｆｅｒｅｎｃｅ ｏｎ ５ｏｌｉｄ ５ｔａ
ｔｅＤｅｖｉｃｅｓ ａｎｄ Ｍａｔｅｒｉａｌｓ）Ｐ
４４５に示されている。第５図に示す如く、下部配線５
２が下部電極を兼ねトンネル障壁５３は下部配線５２上
全面に設けられていた。Another conventional structure (second conventional technology) is, for example, Extended Abstracts 18th Conference on Solids Knight Devices and Materials (
Extended Abstracts of the
18th (1986 International)C
onference on 5olid 5ta
teDevices and Materials)P
445. As shown in FIG. 5, the lower wiring 5
2 also serves as a lower electrode, and a tunnel barrier 53 is provided over the entire surface of the lower wiring 52.
従来この構造は下部配線５２、トンネル障壁５３及び上
部電極５５を連続成長した後、上部電極５５だけを加工
する製造方法によって形成されていた。Conventionally, this structure has been formed by a manufacturing method in which the lower wiring 52, the tunnel barrier 53, and the upper electrode 55 are successively grown, and then only the upper electrode 55 is processed.
又、トンネル障壁形成後上部配線形成までに接合領域規
定、絶縁層５４の形成及び加工が必要であった。Furthermore, it is necessary to define the junction region and form and process the insulating layer 54 after forming the tunnel barrier and before forming the upper wiring.
別の従来構造の一つ（第三の従来技術）は例えば昭和６
１年度電子通信学会総合全国大会（８８−３）２−３７
３に示されている。第６図に示す如く下部配線６２が下
部電極を兼ね、接合領域は下部配線６２上に接して設け
られた絶縁層６３の開孔部として規定されていた。その
ため接合領域は凹部となり、トンネル障壁６４及び上部
配線６５（上部電極を兼ねる）が凸凹面上に設けられて
いた。Another conventional structure (third conventional technology) is, for example, the Showa 6
1st Annual National Conference of the Institute of Electronics and Communication Engineers (88-3) 2-37
3. As shown in FIG. 6, the lower wiring 62 also served as a lower electrode, and the bonding area was defined as an opening in an insulating layer 63 provided on and in contact with the lower wiring 62. Therefore, the junction region became a concave portion, and the tunnel barrier 64 and the upper wiring 65 (also serving as the upper electrode) were provided on the uneven surface.
（発明が解決しようとする問題点）
１．１ 第一と第二の従来技術においては、トンネル障
壁層より上層に上部電極、上部配線、絶縁層が配置され
ている。トンネル障壁形成後、上部配線を形成するまで
に、接合領域を規定する工程、絶縁層の形成及び平坦化
加工工程、更に上部電極と上部配線の電気的接触を実現
するための工程等が必要であった。トンネル障壁及び回
路装置の製造歩留りはトンネル障壁形成後に施される、
例えばベーキング、プラズマ処理、リソグラフィ処理等
の工程数の゛増大にともなって低下し、第一と第二の従
来技術では製造歩留りの向上を図る事は困難であった。(Problems to be Solved by the Invention) 1.1 In the first and second conventional techniques, an upper electrode, an upper wiring, and an insulating layer are arranged above the tunnel barrier layer. After forming the tunnel barrier and before forming the upper wiring, a process for defining a junction region, a process for forming and planarizing an insulating layer, and a process for realizing electrical contact between the upper electrode and the upper wiring are necessary. there were. The manufacturing yield of tunnel barriers and circuit devices is determined by the process performed after tunnel barrier formation.
For example, as the number of steps such as baking, plasma processing, lithography processing, etc. increases, it decreases, and it is difficult to improve the manufacturing yield with the first and second conventional techniques.
一方、第三の従来技術においては、トンネル障壁形成後
、上部配線を形成するまでには上部配線を形成する最少
工程数ですむ。しかし、トンネル障壁は凸凹面上に設け
られており、トンネル障壁及び上記配線が凸凹面上に設
けられた事による装置の信頼性の低下は避けられなかっ
た。On the other hand, in the third conventional technique, the minimum number of steps for forming the upper wiring is required after forming the tunnel barrier and before forming the upper wiring. However, the tunnel barrier is provided on an uneven surface, and since the tunnel barrier and the wiring are provided on the uneven surface, a decrease in reliability of the device is unavoidable.
すなわち、従来の技術においては、トンネル障壁形成後
の工程数を減らして且つ上部配線の平坦化を実現する事
は困難であり、信頼性の高い回路（問題を解決するため
の手段）
４゛１本発明の超伝導回路装置は基板上に設けられたシ
ュ
第１の超伝導電極と、該第１の超伝導電極の上にトンネ
ル障壁を介して設けられた第２の超伝導電極とで構成さ
れ、該トンネル障壁が第１の超伝導電極の周囲を第１の
超伝導電極の厚さと同じ厚さの絶縁層で包囲して形成さ
れる主表面上に延びている事を特徴とし、本発明の超伝
導回路装置の製造方法は基板上に設けられた第１の超伝
導電極と、該第１の超伝導電極の上にトンネル障壁を介
して設けられた第２の超伝導電極とで構成される超伝導
回路装置を製造方法する場合、第１の超伝導電極の周囲
を第１の超伝導電極の厚さと同じ厚さの絶縁層で包囲す
る第１の工程と、第１の工程によって形成される主表面
上全面にトンネル障壁を形成する第２の工程とを含む事
を特徴とする。In other words, with the conventional technology, it is difficult to reduce the number of steps after forming the tunnel barrier and flatten the upper wiring, and it is difficult to achieve a highly reliable circuit (means to solve the problem). The superconducting circuit device of the present invention includes a first superconducting electrode provided on a substrate, and a second superconducting electrode provided above the first superconducting electrode via a tunnel barrier. The present invention is characterized in that the tunnel barrier extends over the main surface formed by surrounding the first superconducting electrode with an insulating layer having the same thickness as the first superconducting electrode. The method for manufacturing a superconducting circuit device of the invention includes a first superconducting electrode provided on a substrate, and a second superconducting electrode provided on the first superconducting electrode via a tunnel barrier. In a method for manufacturing a superconducting circuit device, a first step of surrounding a first superconducting electrode with an insulating layer having the same thickness as the first superconducting electrode; and a second step of forming a tunnel barrier over the entire main surface formed by the method.
（作用）
下部電極が下部電極と同じ厚さの絶縁層で包囲されるた
め、下部電極の主表面と絶縁層の主表面は平坦性良く連
続した一つの平面を構成する。該平面に接してトンネル
障壁が設けられているのでトンネル障壁の平坦性は良好
である。、トンネル構造は下部電極を下部電極と同じ厚
さの絶縁層で、＼包囲して平坦性良く連続した下部電極
の主表面と絶縁層の主表面を形成した後主表面全体にト
ンネル障壁を形成する製造方法を用いて実現できる。(Function) Since the lower electrode is surrounded by the insulating layer having the same thickness as the lower electrode, the main surface of the lower electrode and the main surface of the insulating layer constitute one continuous plane with good flatness. Since the tunnel barrier is provided in contact with the plane, the tunnel barrier has good flatness. In the tunnel structure, the lower electrode is surrounded by an insulating layer with the same thickness as the lower electrode to form a flat and continuous main surface of the lower electrode and the main surface of the insulating layer, and then a tunnel barrier is formed over the entire main surface. This can be achieved using a manufacturing method.
トンネル障壁が平坦性の良い下地面に形成されるので、
平坦性の良いトンネル障壁が形成できる。Since the tunnel barrier is formed on a flat base surface,
A tunnel barrier with good flatness can be formed.
更に上部電極を兼ねた上部配線をトンネル障壁に重ねて
形成するため、平坦性の良い上部配線が形成できる。又
トンネル障壁を形成したのち上部配線を形成するまでの
工程数を最少限にする事ができる。Furthermore, since the upper wiring which also serves as the upper electrode is formed overlapping the tunnel barrier, the upper wiring with good flatness can be formed. Furthermore, the number of steps from forming the tunnel barrier to forming the upper wiring can be minimized.
すなわち、トンネル障壁形成後、上部配線形成までに必
要な工程数を最少にして且つ平坦な上部配線を形成する
事が可能になる。That is, it is possible to minimize the number of steps required from the formation of the tunnel barrier to the formation of the upper wiring, and to form a flat upper wiring.
（実施例）
第１図は本発明の詳細な説明するための超伝導回路装置
の断面図である。例えば、５ｉ０２を用いた基部１１上
に、例えばニオブを用いた下部配線１２を設ける。基部
１１には例えばニオブを用いたグランドプレーン、グラ
ンドプレーンを被覆する絶縁層等が含まれる場合も考え
られる。下部配線１２上に接して、例えばニオブを用い
た下部電極１３が設けられ、下部電極１３の周囲は下部
電極１３と同じ厚さの絶縁層１４（例えばＳｉＯ２が用
いられる）によって包囲された。下部電極１３と絶縁層
１４によって形成される平坦主表面上に例えばアルミ酸
化層を用いたトンネル障壁１５が設けられた。更にｌ・
ンネル陣壁１５に重ねて上部電極を兼ねた、例えばニオ
ブを用いた上部配線１６が設けられた。その後第１図に
は示していないが、上部配線１６を埋め込んだり、更に
上部に重ねて制御線を設ける事も考えられる。(Example) FIG. 1 is a sectional view of a superconducting circuit device for explaining the present invention in detail. For example, a lower wiring 12 made of niobium, for example, is provided on a base 11 made of 5i02. The base 11 may include a ground plane made of niobium, an insulating layer covering the ground plane, and the like. A lower electrode 13 made of niobium, for example, was provided in contact with the lower wiring 12, and the lower electrode 13 was surrounded by an insulating layer 14 (made of SiO2, for example) having the same thickness as the lower electrode 13. A tunnel barrier 15 using, for example, an aluminum oxide layer was provided on the flat main surface formed by the lower electrode 13 and the insulating layer 14. Furthermore l・
An upper wiring 16 made of niobium, for example, was provided to overlap the channel wall 15 and also serve as an upper electrode. After that, although not shown in FIG. 1, it is conceivable to bury the upper wiring 16 or to provide a control line in an overlapping manner.
第２図は本発明の詳細な説明するために、超伝導回路装
置の上部配線と下部電極又は下部配線との重なり具合を
示す平面図である。第２図（ａ）に示すように、下部配
線２１と上部配線２２を重ねると接合領域は、下部配線
２１と上部配線２２のそれぞれ配線幅によって規定され
、下部電極と上部電極にはそれぞれ下部配線２１と上部
配線２２の重なった部分が対応した。別に第２図（ｂ）
に示すように下部電極２３と上部配線２２が重なると接
合領域は下部電極２３の形状によって規定され、上部電
極には上部配線２２の下部電極と重なった部分が対応し
た。以上実施例に述べた構造を有する超伝導回路装置で
はトンネル障壁層の上層には直接上部配線が設けられ、
且ねて例えば厚さ２００ｎｍのニオブスパッタ膜を下部
配線３２として形成した（第３図（ａ））。この下部配
線３２の上に例えばニオブスパッタ膜を形成した後例え
ばフォトレジストパターンをマスクに用いた加工法によ
りこのニオブスパッタ膜を下部電極３３として成形し次
にこのフォトレジストパターンをリフトオフ用ステンシ
スマスクとして用いて例えば５ｉ０２膜をスパッタ堆積
した後リフトオフを施して下部電極３３の周囲を絶縁層
３４で包囲した。下部電極３３の堆積厚さは例えば１３
０ｎｍであり、絶縁層３４の堆積厚さは例えば１５０ｎ
ｍの厚さとした（第３図（ｂ））。次に、例えば８Ｘ１
０−５Ｐａの真空度下で例えばアルゴンガズ１０ｍＴｏ
ｒｒ、ＲＦプラズマ電力密度０゜８Ｗ１ｃｍ２の条件下
で例えば２０分ＲＦクリーニングを行った。この条件下
でニオブと８ｉ０２膜のエツチングレートはそれぞれ１
．５ｎｍ／分、２．５ｎｍ／分であるので、ＲＦクリー
ニング後は下部電極３３、絶縁層３４の厚さはいずれも
１１００ｎとなり平坦性の良い主表面が形成された（第
３図（Ｃ））。その後、同一真空室内で２Ｗ／ｃｍ２の
条件下でニオブをスパッタリング堆積して、例えば厚さ
２００ｎｍの上部配線３６を形成した。FIG. 2 is a plan view showing how the upper wiring and the lower electrode or lower wiring of the superconducting circuit device overlap in order to explain the present invention in detail. As shown in FIG. 2(a), when the lower wiring 21 and the upper wiring 22 are overlapped, the bonding area is defined by the wiring width of the lower wiring 21 and the upper wiring 22, respectively, and the lower electrode and the upper electrode have the lower wiring. The overlapping portions of 21 and upper wiring 22 corresponded to each other. Separately, Figure 2(b)
As shown in FIG. 2, when the lower electrode 23 and the upper wiring 22 overlap, the bonding region is defined by the shape of the lower electrode 23, and the portion of the upper wiring 22 that overlaps with the lower electrode corresponds to the upper electrode. In the superconducting circuit device having the structure described in the embodiments above, an upper wiring is provided directly on the upper layer of the tunnel barrier layer,
In addition, a niobium sputtered film having a thickness of, for example, 200 nm was formed as the lower wiring 32 (FIG. 3(a)). After forming, for example, a niobium sputtered film on this lower wiring 32, this niobium sputtered film is formed as a lower electrode 33 by a processing method using, for example, a photoresist pattern as a mask, and then this photoresist pattern is used as a stenosis mask for lift-off. For example, a 5i02 film was sputter-deposited using the same method, and then lift-off was performed to surround the lower electrode 33 with an insulating layer 34. The deposition thickness of the lower electrode 33 is, for example, 13
0 nm, and the deposited thickness of the insulating layer 34 is, for example, 150 nm.
The thickness was set at m (Fig. 3(b)). Next, for example 8X1
For example, 10 mTo of argon gas under a vacuum of 0-5 Pa.
For example, RF cleaning was performed for 20 minutes under the conditions of rr, RF plasma power density of 0°8W1cm2. Under these conditions, the etching rates of the niobium and 8i02 films are each 1
．． 5 nm/min and 2.5 nm/min, the thickness of the lower electrode 33 and the insulating layer 34 were both 1100 nm after RF cleaning, and a main surface with good flatness was formed (Figure 3 (C)). . Thereafter, niobium was deposited by sputtering in the same vacuum chamber under the condition of 2 W/cm 2 to form an upper wiring 36 having a thickness of, for example, 200 nm.
平坦性の良いトンネル障壁３５と同様に平坦性の良好な
上部配線３６が形成された（第３図（ｄ））。次に例え
ばフォトレジストマスクを用いてよく知られたドライエ
ツチング法により、上部配線３６のパターニングを行い
、必要な上部配線パターンを実現した（第３図（ｅ））
。この結果、平坦性の良好な上部配線がトンネル障壁形
成後最少工程数で実現できた。Similar to the tunnel barrier 35 with good flatness, the upper wiring 36 with good flatness was formed (FIG. 3(d)). Next, the upper wiring 36 was patterned by the well-known dry etching method using, for example, a photoresist mask to realize the required upper wiring pattern (Fig. 3(e)).
. As a result, an upper wiring with good flatness could be realized with a minimum number of steps after forming the tunnel barrier.
（発明の効果）
本発明の構造によれは、下部電極と絶縁層で構成される
平坦主表面の上にトンネル障壁層と上部配線が重ねて設
けられるので、トンネル障壁形成後上部配線形成までの
工程数の低減が可能になり、且つ平坦性の良い上部配線
が実現できる。その結果信頼性の高い回路装置を高歩留
りで実現できる。(Effects of the Invention) The structure of the present invention eliminates this problem because the tunnel barrier layer and the upper wiring are provided in an overlapping manner on the flat main surface composed of the lower electrode and the insulating layer. It becomes possible to reduce the number of steps and realize an upper wiring with good flatness. As a result, highly reliable circuit devices can be realized with high yield.
また、本発明の製造プロセスによれば下部電極が下部電
極と同じ厚さの絶縁層で包囲されて形成された平坦主表
面の上にトンネル障壁層と上部配線が重ねて形成される
ので、上部配線の平坦性が良好になり且つトンネル障壁
形成後上部配線形成までの工程数の低減が可能になった
。その結果信）第１図は本発明の構造の実施例を示すた
めの超伏２導回路装置の断面図である。第２図（ａ）、
（ｂ）は本発明の構造の実施例を示すための超伝導回路
装置の平面図である。第３図（ａ）〜（ｅ）は本発明の
製造方法の実施例を示すための超伝導回路装置の製造７
０−断面図である。第４図、第５図及び第６図はそれぞ
れ従来の構造を示すための超伝導回路装置の断面図であ
る。In addition, according to the manufacturing process of the present invention, the tunnel barrier layer and the upper wiring are formed in an overlapping manner on the flat main surface formed by surrounding the lower electrode with an insulating layer having the same thickness as the lower electrode. The flatness of the wiring has been improved, and the number of steps from forming the tunnel barrier to forming the upper wiring can be reduced. As a result, FIG. 1 is a sectional view of a super-conducting two-conductor circuit device showing an embodiment of the structure of the present invention. Figure 2(a),
(b) is a plan view of a superconducting circuit device for showing an embodiment of the structure of the present invention. FIGS. 3(a) to 3(e) show manufacturing 7 of a superconducting circuit device to show an embodiment of the manufacturing method of the present invention.
0- sectional view. FIG. 4, FIG. 5, and FIG. 6 are sectional views of a superconducting circuit device to show the conventional structure, respectively.
図において、
１１．３１，４１，５１．６１は基部、１２．２１，３
２，４２，５２．６２は下部配線、１３．２３，３３．
４３は下部電極、
１４．３４，４５．５４．６３は絶縁層、１５．３５，
４４．５３．６４はトンネル障壁、１６．２２，３６，
４７，５６．６５は上部配線、４６．５５は上部電極
である。In the figure, 11.31, 41, 51.61 are the base, 12.21, 3
2, 42, 52.62 are lower wiring, 13.23, 33.
43 is a lower electrode, 14.34, 45.54.63 is an insulating layer, 15.35,
44.53.64 is tunnel barrier, 16.22,36,
47, 56.65 are upper wirings, and 46.55 are upper electrodes.
Claims (1)
超伝導電極の上にトンネル障壁を介して設けられた第２
の超伝導電極とで構成される超伝導回路装置において、
該トンネル障壁が、第１の超伝導電極の周囲を第１の超
伝導電極の厚さと同じ厚さの絶縁層で包囲して形成され
る主表面上に延びている事を特徴とする超伝導回路装置
。 ２）基板上に設けられた第１の超伝導電極と、該第１の
超伝導電極の上にトンネル障壁を介して設けられた第２
の超伝導電極とで構成される超伝導回路装置の製造方法
において、第１の超伝導電極の周囲を第１の超伝導電極
の厚さと同じ厚さの絶縁層で包囲する第１の工程と、第
１の工程によって形成される主表面上全面にトンネル障
壁を形成する第２の工程とを含む事を特徴とする超伝導
回路装置の製造方法。[Claims] 1) A first superconducting electrode provided on a substrate, and a second superconducting electrode provided on the first superconducting electrode via a tunnel barrier.
In a superconducting circuit device consisting of a superconducting electrode,
A superconductor characterized in that the tunnel barrier extends over a main surface formed by surrounding the first superconducting electrode with an insulating layer having the same thickness as the first superconducting electrode. circuit device. 2) A first superconducting electrode provided on the substrate, and a second superconducting electrode provided on the first superconducting electrode via a tunnel barrier.
a first step of surrounding the first superconducting electrode with an insulating layer having the same thickness as the first superconducting electrode; , a second step of forming a tunnel barrier over the entire main surface formed in the first step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62037802A JPS63205972A (en) | 1987-02-23 | 1987-02-23 | Superconducting circuit device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62037802A JPS63205972A (en) | 1987-02-23 | 1987-02-23 | Superconducting circuit device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63205972A true JPS63205972A (en) | 1988-08-25 |
Family
ID=12507639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62037802A Pending JPS63205972A (en) | 1987-02-23 | 1987-02-23 | Superconducting circuit device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63205972A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018093544A1 (en) * | 2016-11-15 | 2018-05-24 | Northrop Grumman Systems Corporation | Method of making a josephson junction based superconductor device |
| US10276504B2 (en) | 2017-05-17 | 2019-04-30 | Northrop Grumman Systems Corporation | Preclean and deposition methodology for superconductor interconnects |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60178676A (en) * | 1984-02-25 | 1985-09-12 | Nippon Telegr & Teleph Corp <Ntt> | Tunnel type josephson element and manufacture thereof |
-
1987
- 1987-02-23 JP JP62037802A patent/JPS63205972A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60178676A (en) * | 1984-02-25 | 1985-09-12 | Nippon Telegr & Teleph Corp <Ntt> | Tunnel type josephson element and manufacture thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018093544A1 (en) * | 2016-11-15 | 2018-05-24 | Northrop Grumman Systems Corporation | Method of making a josephson junction based superconductor device |
| US10608159B2 (en) | 2016-11-15 | 2020-03-31 | Northrop Grumman Systems Corporation | Method of making a superconductor device |
| AU2017360504B2 (en) * | 2016-11-15 | 2020-04-16 | Northrop Grumman Systems Corporation | Method of making a Josephson junction based superconductor device |
| US10276504B2 (en) | 2017-05-17 | 2019-04-30 | Northrop Grumman Systems Corporation | Preclean and deposition methodology for superconductor interconnects |
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