JPS5913374A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the semiconductor device whose threshold voltage is hard to depend upon channel width by a method wherein field ions are implanted to a region isolated from an element region, impurities with reverse conductive type of a substrate are diffused, and net impurity concentration is lowered at the circumferential part of the element region than the central part of the element region. CONSTITUTION:An oxide film 22 is formed according to the thermal oxidation method on the P type silicon substrate 21, and a silicon nitride film 23 is formed thereon and is patterned. Then anisotropic dry etching is performed using Freon, hydrogen gas, for example, and an oxide film 24 on the surface of the substrate is etched. Arsenic is diffused to the substrate 21 from AsSG 24, and moreover field ions are implanted through the silicon nitride film 23, AsSG 24 and the nitride film 23 to form the boron ion implanted layer 25 (refer to the picture). Moreover AsSG is etched to be removed according to NH4F, etc., and the field part 27 is formed according to the thermal oxidation method.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a highly integrated, high-performance semiconductor device by a selective oxidation method using an oxidation-resistant film.

[Prior art and its problems]

FIG. 711 shows the selective oxidation process in the conventional silicon hand conductor manufacturing process. First, an oxide film 12 is formed on one main surface of the silicon substrate 11 by a thermal oxidation method (see FIG. 1A). Next, a silicon nitride film 13 is formed on the thermal oxide film 12, and the silicon nitride film 13 is patterned by a known photoetching technique (see FIG. 1). First, heporon ions are implanted into the silicon substrate through the f+iJ oxidation layer 12 to form a poron ion implantation layer 14 (see FIG. 1C). After that, selective oxidation is performed (see Figure 1C). Thereafter, M is applied to the silicon substrate 11 under the oxide film 12 using a well-known technique.
OS mMj field effect transistor etc. are formed.

However, the MO8 type transistor formed by this selective oxidation method has a drawback that a so-called narrow channel effect occurs in which the threshold voltage increases as the channel width becomes narrower, as shown in FIG. In this process, the poron ions implanted into the silicon substrate seep into the element region, resulting in an impurity distribution as shown in Figure 3.
The narrow channel effect is further emphasized. The channel width dependence of the threshold voltage due to the narrow channel effect increases with the miniaturization of the L-L transistor, which adversely affects device characteristics and poses a troublesome problem in the design of integrated circuits.

[Purpose of the invention]

The present invention improves the drawbacks of the conventional method described above, and aims to provide a semiconductor device in which the threshold voltage is less dependent on the channel width.

〔G essential for ``ψ'']

In order to prevent ions of the same conductivity type as the substrate from seeping into the element region described above, the present invention performs field ion implantation into a region far away from the child region and injects impurities of the opposite 4-conductivity type to the substrate. The present invention is characterized in that an impurity distribution as shown in FIG. 4 is obtained in which the net impurity concentration is lower at the periphery of the element region than at the center of the element region.

[)Raming effect]

According to the present invention, as shown in FIG. 5, a semiconductor device is obtained in which the narrow cell effect is suppressed compared to the conventional one, and the degree of integration and reliability of the integrated circuit are greatly improved.

(In Figures 4 and 5, a is conventional,
bl-1 According to the Present Invention) [Embodiments of the Invention] The present invention will be described in detail below by way of an embodiment with reference to the drawings.

FIG. 6 is a plan view of step 11 of an embodiment of the present invention. An oxide film 22 of, for example, 1000 K is formed on a J-13 type silicon substrate 2 by a thermal oxidation method (see FIG. 6). C
reference). A silicon nitride film of, for example, 4000 K is formed thereon, and the necessary portions are patterned using a known photoetching technique (see FIG. 6). After that, for example, AsH, gas and 5rkl, gas and 02 gas are formed using CV D method K YoIJ As 8 (324f, for example, 3000 A (see Fig. 6C)).Next, for example, Freon, water volume is formed. 0.01-0.03 Lor using gas
When the oxide film on the surface of the substrate is etched by angular dry etching at a gas pressure of . Next, arsenic is diffused from As5G24 into the substrate 21 by a heating process at 1000° C., and further 1. the arsenic film Z3, ASSG
For example, an acceleration voltage of 1 is applied through Z4 and the silicon nitride film n.
(G) Key, perform field ion implantation 4f at a dose of lXl013-2. For example, poron is used as the implanted ion, and the poron ion implantation layer 5 is formed (sixth
(see figure d). Furthermore, the As5G is removed by etching with NH4F or the like (see FIG. 6C). Thereafter, a field portion 27 is formed by a thermal oxidation method (see FIG. 6C). Finally, the silicon nitride film is removed using a conventional technique, and an A40B type transistor is formed on the surface of the silicon substrate with the hole formed.

In addition, in the above embodiment, the voltage from As5G24 to the substrate 21 is
Although the arsenic diffusion was performed before the poron ion implantation step, it may be performed after the ion implantation.

Further, in the above embodiment, an As5G film was deposited in the step shown in FIG. 6-C, but an arsenic-doped polycrystalline silicon film may be deposited by the CVD method. In this case, in the above embodiment, the etching was removed in the step shown in FIG. 16-e, but this step may be omitted and the field portion 37 may then be formed by thermal oxidation as shown in FIG.

By doing so, it becomes more even.

In the above embodiment, the explanation was given using an n-channel MO8 using a P-type substrate, but [P-channel using a type 1 substrate,
The precept can be used for C+OS as well.

When the method of manufacturing a semiconductor device of the present invention is used, the characteristics of the conventional selective oxidation method are lost.1. It is possible to obtain a transistor with a suppressed narrow channel effect and a small channel width dependence of the threshold voltage, which is effective in achieving high integration and high performance.

[Brief explanation of the drawing]

Figures 1 (21) to (d) are 8 cross-sectional views of silicon conductors obtained by the conventional selective oxidation method, and Figure 2 is the channel width of the threshold voltage in a transistor obtained by the rice pressing method. A characteristic diagram showing the dependence. Figure 3 is a net impurity distribution diagram at the interface between the oxide film and silicon in the conventional method. Figure 4 is a diagram showing the impurity distribution at the interface between the oxide film and silicon in the transistor according to the present invention. Figure 5 7 is a cross-sectional view of the manufacturing process of a conductor in a transistor according to the present invention, and FIG.
, 15.22.24.27, 34.37... Oxide film, 13, 23, 33-... Silicon nitride film,
Lc. 14.25, 35...Boron ion layer, 26, 3
6...Siri, con ion layer. (d) Representative patent attorney Kensuke Norichika (and 1 other person) Figure 1 Figure 2 Figure 3 Figure 7

Claims (1)

[Claims] In a method for manufacturing a semiconductor device in which a thermal oxide film is selectively formed on the surface of a semiconductor substrate using an oxidation-resistant film as a mask, after the oxidation-resistant film is selectively formed, at least one substrate is of opposite conductivity type. A material layer doped with impurities is placed so as to cover the oxidation-resistant film, the material layer is formed so as to cover only the side surfaces and the vicinity of the oxidation-resistant film, and the material layer is applied to the substrate in the opposite direction to the substrate. After diffusing conductivity type impurities, ion implantation of impurities of the same conductivity type as the substrate is performed, and after removing the above material layer, a thermal oxidation layer is selectively formed, and the element region has the same conductivity type impurity concentration as the net substrate. A method of manufacturing a semiconductor device, characterized in that the peripheral part of the element region is lower than the central part.