JPS5913364A - Semiconductor device - Google Patents

Abstract

PURPOSE:To conform substrate potential under and in the vicinity of a dynamic circuit to reference potential while eliminating the variation of potential, and to expand the maximum operating voltage of the dynamic circuit largely by forming a substrate contact around the dynamic circuit. CONSTITUTION:The substrate contacts 141-143 are set up near the periphery of the dynamic circuit 13 besides substrate contacts 121-124 of the fringe section of a chip in the LSI chip 11. Consequently, substrate potential among the dynamic circuit 13 and the substrate contacts 141-143 is made approximately the same. As a result, the variation of potential as a hazard synchronizing with clock pulses as seen in conventional devices is not generated, and there is no danger of which contents memorized in the dynamic circuit 13 change. When a P<+> layer 17 is formed so as to surround the dynamic circuit 13, contact resistance between a substrate and an aluminum wiring 15 is reduced by the layer 17, and substrate potential can further be brought close to GND potential.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to semiconductor devices, particularly dynamic RAM.
(Random Access Memory),
Dynamic ROM (Read Only Memo
ry ), etc. dynamics.

The present invention relates to a substrate contact for matching the substrate potential to a reference potential in a circuit having a similar configuration.

[Technical background of the invention]

Conventionally, for example, N-channel MO8LS I (M@t
In a 10xlds per 5ml onduator), the substrate contacts were arranged as shown in FIG. 1, for example. That is, the four sassist straight contacts 11, l* +18 174 are L
The substrate contacts 11 to 4 are respectively arranged at the peripheral edge of the SI chips 1 and 2, and these substrate contacts 11 to 4 are connected to each other by an aluminum At wiring 3. A dending pad 4 for GND connection is provided in the middle of the aluminum wiring 3, and a dynamic circuit (for example, a dynamic RAM ) The substrate potential of step 5 is made to match the GND potential.

[Problems with background technology]

However, in the above-mentioned MO8LSI, the substrate potential of the dynamic circuit 5 portion does not match the GND potential, which is a frequent cause of malfunction of the dynamic circuit 5. For example, as shown in FIG. 2, a hazard-like potential fluctuation occurs in the substrate potential v, ub of the dynamic circuit 50 in synchronization with the clock pulse φ, φ. The amplitude of this potential fluctuation is
It is approximately proportional to the power supply voltage, and if the power supply voltage exceeds a certain value (maximum operating voltage), the contents stored in the dynamic circuit 5 will change.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device that can eliminate fluctuations in substrate potential around a circuit.

[Summary of the invention]

The present invention provides a substrate contact at least in a portion near the periphery of a dynamic circuit in order to eliminate fluctuations in substrate potential that cause malfunctions of the dynamic circuit.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 3, substrate contacts 121 + 12 are attached to the periphery of the N-channel MO8LSI chip full.
1 + 12s + 12th is provided, and a dynamic circuit (e.g. dynamis, RAM)
Substrate contact 1 is placed near three sides around 13.
4Ip 14t *14B is provided. The above substrate contact 12. ~124 r 141
14s are interconnected by, for example, aluminum wiring 15. There is a G in the middle of this aluminum wiring 15.
Bonding /'P and /dodes 16 for ND connection are provided. That is, the ending pad 16, the aluminum wiring 16 and the substrate contact 12
．． ~12. ,14. 141, the substrate potential of the dynamic circuit 13 is made to match the GND potential.

Conventionally, the substrate potential of the dynamic circuit part often matched the GND potential because the substrate contact was LS
This is because it was placed only on the periphery of the I-chip, separated from the dynamometer circuit part, and due to the resistance of the board, the part where the substrate contact was connected to the substrate potential and the dynamometer circuit part. This is because there is a gradient in . On the other hand, in the LSI chip 11 shown in FIG. 3, in addition to substrate contacts 12+ to 12 on the chip periphery, substrate contacts 14t to 148 are provided near the periphery of the dynamic circuit 13. Substrate contact 141
The substrate potentials between 143 and 143 are approximately the same. Therefore, hazard-like potential fluctuations that are synchronized with the pulses as in the prior art do not occur, and there is no fear that the contents stored in the dynamic circuit 13 will change.

In FIG. 4, a P+ layer 17 is provided so as to surround the dynamic circuit 13, which greatly reduces the contact resistance between the substrate and the aluminum wiring 15 and lowers the substrate potential.
The GND potential potential pressure increases.

FIG. 5 shows a cross-sectional structure of the dynamic circuit 13 of FIG. 4 and its surrounding area. In the same figure, 18 is P
type silicon substrate, 19° 20 is an insulating layer, 21.22 is N
A breakdown layer that becomes the source and drain of the channel transistor,
23 is a dirt oxide film, 24 is a dirt electrode made of polycrystalline silicon, and 26 is a polycrystalline silicon wiring.

The figure shows a dynamic circuit section, and the substrate contact 148 is provided on the insulating layer 19 near the dynamic circuit section A, and the P+ layer 17 is provided on the surface of the substrate 18 directly below the substrate contact 14m. It is being

In the above embodiment, the substrate contacts 14+ to 14s are provided near the three sides around the dynamic circuit 13, but the present invention is not limited to this. It is sufficient to set it in Furthermore, in the embodiment shown in FIG. 4, the P+ layer 17 for lowering the contact resistance does not necessarily need to be provided all around the dynamic circuit 13;
It may also be provided only in the portion directly below the substrate contacts 14I to 148. Further, in the above embodiment, an N-channel MO8LSI was described, but it goes without saying that a P-channel configuration may also be used. however,
In this case, the diffusion layer for lowering the contact resistance is an N+ layer.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to match the substrate potential under and in the vicinity of the dynamic circuit to the reference potential, and it is possible to eliminate potential fluctuations that cause malfunctions, and as a result, the dynamic circuit The maximum operating voltage of the device can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional semiconductor device, FIG. 2 is a waveform diagram showing the cross pulses and substrate potential used in the above device, and FIG. 3 is a configuration diagram of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a block diagram of another embodiment of the present invention, and FIG. 5 is a sectional view taken along the line xx' in FIG. 4. 11...LSI Chi, 7.12. ~ No. 12, 141
~143...Substrate contact, 13...
Dynamic circuit, 15... Aluminum wiring, 16
...Pounding pad, 17... P-tier applicant's agent Takeshi Suzue Pig box 1 Figure 2 Figure 3 Figure 22 Figure 4 12?

Claims (2)

[Claims] (1) A semiconductor device characterized in that a substrate contact portion for matching the potential of a circuit board to a reference potential via metal wiring is provided at least in a portion near the periphery of an internal circuit. (2) The semiconductor device according to claim 1, wherein a high concentration impurity region of the same conductivity type as the circuit board is provided on the surface of the circuit board located directly below the substrate contact portion.