JPH04163940A - Power-on-reset circuit for master slice system integrated circuit deice - Google Patents

Power-on-reset circuit for master slice system integrated circuit deice

Info

Publication number
JPH04163940A
JPH04163940A JP2290407A JP29040790A JPH04163940A JP H04163940 A JPH04163940 A JP H04163940A JP 2290407 A JP2290407 A JP 2290407A JP 29040790 A JP29040790 A JP 29040790A JP H04163940 A JPH04163940 A JP H04163940A
Authority
JP
Japan
Prior art keywords
power
capacitor
reset circuit
integrated circuit
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2290407A
Other languages
Japanese (ja)
Inventor
Hiroyuki Yano
博之 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2290407A priority Critical patent/JPH04163940A/en
Publication of JPH04163940A publication Critical patent/JPH04163940A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the cost and the number of the parts by arranging a power- on-reset circuit in an input/output cell region. CONSTITUTION:A P-type MOS transistor 301, a capacitor 302, a waveform shaping inverter 303, and a pad electrode 304 are formed. The gate electrode of the transistor 301 is connected with VSS, and the source terminal is connected with VDD. And the drain terminal is connected with the first electrode of the capacitor 302 and input terminal of the waveform shaping inverter 303. The capacitor 502 are formed by using the pad electrode 304. In this way, a power- on-reset circuit is arranged in the input/output cell arranged region of a master slice system integrated circuit device. Accordingly, the pad electrode in the input/output cell arranged region can be utilized as a capacitor, a stabilized power-on-reset signal can be supplied to an inside cell, and besides the cost can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マスタースライス方式集積回路装置のパワー
オンリセット回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-on reset circuit for a master slice type integrated circuit device.

［従来の技術］ 従来のマスタースライス方式集積回路装置は、パワーオ
ンリセット回路を形成することが出来なかった。もしも
、必要な場合は集積回路装置の外に、パワーオンリセッ
ト回路を付加した。[Prior Art] A conventional master slice type integrated circuit device cannot form a power-on reset circuit. If necessary, a power-on reset circuit was added outside the integrated circuit device.

［発明が解決しようとする課題］ しかし、前述の従来技術では、パワーオンリセット回路
を、マスタースライス方式集積回路装置内に、形成する
ことができ゛ず、もしも、必要な場合は、パワーオンリ
セット回路を外付けにしなければならないため、コスト
、部品点数の増加と言う問題点を有する。そこで本発明
は、このような問題点を、解決するもので、その百的と
するところは、パワーオンリセット回路を形成し、なお
かつ、集積回路装置の面積を増加させることのない、マ
スタースライス集積回路装置を提供するところにある。[Problems to be Solved by the Invention] However, with the above-mentioned prior art, it is not possible to form a power-on reset circuit in a master slice type integrated circuit device, and if necessary, a power-on reset circuit cannot be formed in the master slice type integrated circuit device. Since it has to be externally attached, there are problems such as an increase in cost and the number of parts. SUMMARY OF THE INVENTION The present invention aims to solve these problems, and its primary purpose is to provide a master slice integrated circuit that forms a power-on reset circuit and does not increase the area of an integrated circuit device. The company provides circuit devices.

［課題を解決するための手段］ 本発明のマスタースライス方式集積回路装置用パワーオ
ンリセット回路は、マスタースライス方式集積回路装置
において、入出力セル領域内に、パワーオンリセット回
路を配置したことを特徴とする。[Means for Solving the Problems] A power-on reset circuit for a master slice integrated circuit device according to the present invention is characterized in that the power-on reset circuit is arranged within an input/output cell region of the master slice integrated circuit device. shall be.

［実施例］ 第１図は、パワーオンリセット回路の一回路例を示して
おり、１０１は、Ｐ型ＭＯＳトランジスタであり、ゲー
ト端子をｖＳＳに接続し、ソース端子をＶＤＤに、ドレ
イン端子をキャパシタの第一の端子に接続している。１
０２は、キャパシタであり、第一の端子をＰ型ＭＯ８ト
ランジスタ１０１のドレイン端子と接続し、残る第二の
端子をｖＳＳに接続している。１０３は、波形整形用イ
ンバーターであり、入力端子はＰ型トランジスタ１０１
のドレイン端子、および、キャパシタ１０２の第一の端
子と接続している。出力端子は、集積回路装置内で、パ
ワーオンリセットとして使用される。[Example] FIG. 1 shows an example of a power-on reset circuit, in which 101 is a P-type MOS transistor whose gate terminal is connected to vSS, whose source terminal is connected to VDD, and whose drain terminal is connected to a capacitor. is connected to the first terminal of the 1
02 is a capacitor, the first terminal of which is connected to the drain terminal of the P-type MO8 transistor 101, and the remaining second terminal connected to vSS. 103 is a waveform shaping inverter, the input terminal of which is a P-type transistor 101
and the first terminal of the capacitor 102. The output terminal is used as a power-on reset within the integrated circuit device.

第２図は、本発明の一実施例−における、マスタースラ
イス方式集積回路装置の一部平面図であり、２０１は、
本発明のパワーオンリセット回路、２０２は、パワーオ
ンリセット回路出力配線、２０３は、記憶素子でありパ
ワーオンリセットがかけられる記憶素子を示す。２０４
は、実際に使用する入出力セル、２０５は、ボンディン
グワイヤー、２０６は、リードフレーム、２０７は、内
部セル配置領域を示す。パワーオンリセット回路２０１
は、使用されない入出力セル配置領域内に配置される。FIG. 2 is a partial plan view of a master slice integrated circuit device according to an embodiment of the present invention, and 201 is a
In the power-on reset circuit of the present invention, 202 is a power-on reset circuit output wiring, and 203 is a storage element to which a power-on reset is applied. 204
205 is a bonding wire, 206 is a lead frame, and 207 is an internal cell arrangement area. Power-on reset circuit 201
is placed in an unused input/output cell placement area.

なお、本実施例では、パワーオンリセット回路２０１を
、一つしか使用していないが、複数使用してもかまわな
い。Although only one power-on reset circuit 201 is used in this embodiment, a plurality of power-on reset circuits 201 may be used.

第３図は、第２図２０１を拡大した図であり、３０１は
、Ｐ型ＭＯＳトランジスタ、３０２は、キャパシタ、３
０３は、波形整形用インバーター、３０４は、パッド電
極を示す。Ｐ型ＭＯＳトランジスタ３０１のゲート電極
は、ｖＳＳと接続され、ソース端子はＶＤＤと接続され
る。また、ドレイン端子は、キ；バシタ３０２の第一の
電極と、波形整形用インバーター３０３の入力端子とに
接続される。キャパシタ３０２は、パッド電極３０４を
使用して、キャパシタを形成する。本実施例では、パッ
ド電極を使用して、キャパシタを形成しているが、パッ
ド電極を使用せずにキャパシタを形成しても同じ効果が
得られる。波形整形用インバーター３０３の入力は、Ｐ
型ＭＯＳｈランジスタ３０１のドレイン端子とキャパシ
タ３０２の第一の端子とが接続される。波形整形用イン
バーター３０３の出力端子は、パワーオンリセットをか
ける記憶素子に接続する。なお、波形整形用インバータ
ー３０３は、バッファタイプのものでも同じ効果が得ら
れる。なお、第３図の３０１．３０２．３０３は、それ
ぞれ第１図の１０１．１０２．１０３と同じものを示す
。FIG. 3 is an enlarged view of FIG. 2 201, in which 301 is a P-type MOS transistor, 302 is a capacitor, 3
03 is a waveform shaping inverter, and 304 is a pad electrode. The gate electrode of the P-type MOS transistor 301 is connected to vSS, and the source terminal is connected to VDD. Further, the drain terminal is connected to the first electrode of the capacitor 302 and the input terminal of the waveform shaping inverter 303. Capacitor 302 uses pad electrode 304 to form a capacitor. In this embodiment, the capacitor is formed using a pad electrode, but the same effect can be obtained even if the capacitor is formed without using a pad electrode. The input of the waveform shaping inverter 303 is P
The drain terminal of type MOSh transistor 301 and the first terminal of capacitor 302 are connected. The output terminal of the waveform shaping inverter 303 is connected to a storage element to which a power-on reset is applied. Note that the same effect can be obtained even if the waveform shaping inverter 303 is of a buffer type. Note that 301, 302, and 303 in FIG. 3 are the same as 101, 102, and 103 in FIG. 1, respectively.

［発明の効果］ 以上述べたように、本発明によれば、マスタースライス
方式集積回路装置の入出力セル配置領域内に、パワーオ
ンリセット回路を配置する構造にしたため、入出力セル
配置領域内にあるパッド電極を、キャパシタとして利用
することができ、安定したパワーオンリセット信号を内
部セルに対して供給でき、集積回路の面積を増加させる
ことなく、パワーオンリセット回路を取り込むことがで
きる。これにより、コストの低下、部品点数の減少とい
う効果を有する。[Effects of the Invention] As described above, according to the present invention, since the power-on reset circuit is arranged in the input/output cell arrangement area of the master slice integrated circuit device, the power-on reset circuit is arranged in the input/output cell arrangement area. A certain pad electrode can be used as a capacitor, a stable power-on reset signal can be supplied to internal cells, and a power-on reset circuit can be incorporated without increasing the area of the integrated circuit. This has the effect of lowering costs and reducing the number of parts.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、パワーオンリセット回路の一回路例を示した
図。 １０１　・・・　Ｐ型ＭＯＳトランジスタ１０２　・・
・　キャパシタ １０３　・・・　波形整形用インバーター第２図は、本
発明の一実施例におけるマスタースライス方式集積回路
装置の一部平面図。 ２０１　・・・　パワーオンリセット回路２０２　・・
・　パワーオンリセット回路出力配線 ２０３　・・・　記憶素子 ２０４　・・・　実際に使用する入出力セル２０５　・
・・　ボンディングワイヤー２０６　・・・　　リード
フレーム ２０７　・・・　内部セル配置領域 第３図は、第２図２０１を拡大した図。 ３０１　・・・　Ｐ型ＭＯＳトランジスタ３０２　・・
−・　キャパシタ ３０３　・・・　波形整形用インバーター３０４　・・
・　パッド電極 以上 出願人　セイコーエプソン株式会社 代理人　弁理士　鈴木喜三部　他１名 第　　１　　図 第　　２　　図 第　　３　　図FIG. 1 is a diagram showing an example of a power-on reset circuit. 101... P-type MOS transistor 102...
- Capacitor 103... Inverter for waveform shaping FIG. 2 is a partial plan view of a master slice type integrated circuit device according to an embodiment of the present invention. 201... Power-on reset circuit 202...
- Power-on reset circuit output wiring 203... Memory element 204... Input/output cell actually used 205 -
... Bonding wire 206 ... Lead frame 207 ... Internal cell arrangement area FIG. 3 is an enlarged view of FIG. 2 201. 301... P-type MOS transistor 302...
- Capacitor 303... Waveform shaping inverter 304...
- Applicant for pad electrodes and above Seiko Epson Co., Ltd. agent Patent attorney Kizobe Suzuki and 1 other person Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 　マスタースライス方式集積回路装置において、入出力
セル領域内に、パワーオンリセット回路を配置したこと
を特徴とするマスタースライス方式集積回路装置用パワ
ーオンリセット回路。A power-on reset circuit for a master slice integrated circuit device, characterized in that the power-on reset circuit is disposed within an input/output cell region of the master slice integrated circuit device.
JP2290407A 1990-10-26 1990-10-26 Power-on-reset circuit for master slice system integrated circuit deice Pending JPH04163940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2290407A JPH04163940A (en) 1990-10-26 1990-10-26 Power-on-reset circuit for master slice system integrated circuit deice

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2290407A JPH04163940A (en) 1990-10-26 1990-10-26 Power-on-reset circuit for master slice system integrated circuit deice

Publications (1)

Publication Number Publication Date
JPH04163940A true JPH04163940A (en) 1992-06-09

Family

ID=17755618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2290407A Pending JPH04163940A (en) 1990-10-26 1990-10-26 Power-on-reset circuit for master slice system integrated circuit deice

Country Status (1)

Country Link
JP (1) JPH04163940A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001526008A (en) * 1997-05-06 2001-12-11 テレフオンアクチーボラゲツト エル エム エリクソン Electronic system having a chip with integrated power-on reset circuit with glitch sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001526008A (en) * 1997-05-06 2001-12-11 テレフオンアクチーボラゲツト エル エム エリクソン Electronic system having a chip with integrated power-on reset circuit with glitch sensor

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