KR970023929A - Pad Placement Reduces Chip Area - Google Patents

Pad Placement Reduces Chip Area Download PDF

Info

Publication number
KR970023929A
KR970023929A KR1019950038999A KR19950038999A KR970023929A KR 970023929 A KR970023929 A KR 970023929A KR 1019950038999 A KR1019950038999 A KR 1019950038999A KR 19950038999 A KR19950038999 A KR 19950038999A KR 970023929 A KR970023929 A KR 970023929A
Authority
KR
South Korea
Prior art keywords
chip
pads
pad arrangement
pad
chip area
Prior art date
Application number
KR1019950038999A
Other languages
Korean (ko)
Inventor
김형동
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950038999A priority Critical patent/KR970023929A/en
Publication of KR970023929A publication Critical patent/KR970023929A/en

Links

Landscapes

  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 발명은 반도체장치의 패드배치에 관해 개시한다. 본 발명의 패드배치는 모든 패드(Pad)를 칩 내부에 구비하는 패드 배치에 있어서, 상기 패드중 일부패드를 연결수단을 구비하여 칩 외부에 배치한 것을 특징으로 한다.The present invention discloses a pad arrangement of a semiconductor device. In the pad arrangement of the present invention, in the pad arrangement including all pads inside the chip, some pads of the pads are provided outside the chip with connection means.

본 발명은 패드배치에 의하면, 칩의 면적을 줄일 수 있고 전체적으로는 반도체장치의 고 집적화를 이룰 수 있다.According to the pad arrangement, the present invention can reduce the area of the chip and achieve high integration of the semiconductor device as a whole.

Description

칩 면적을 감소시키는 패드 배치Pad Placement Reduces Chip Area

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 패드배치를 나타낸 도면이다.2 is a view showing a pad arrangement according to the present invention.

Claims (4)

모든 패드(Pad)를 칩 내부에 구비하는 패드 배치에 있어서, 상기 패드중 일부패드를 연결수단을 구비하여 칩 외부에 배치한 것을 특징으로 하는 칩 면적을 감소시키는 패드배치.In a pad arrangement having all pads inside a chip, a pad arrangement for reducing a chip area, wherein some pads of the pads are disposed outside the chip with connection means. 제1항에 있어서, 상기 일부패드는 웨이퍼상태에서의 모니터링 패드 및 테스트 패드인 것을 특징으로 하는 칩면적을 감소시키는 패드배치.The pad arrangement of claim 1, wherein the some pads are a monitoring pad and a test pad in a wafer state. 제1항에 있어서, 상기 칩 외부는 스크라이브 라인(scribe line)영역 및 한개의 칩이 형성되기보다는 작은 웨이퍼 상의 영역인 것을 특징으로 하는 칩 면적을 감소시키는 패드배치.2. The pad arrangement of claim 1, wherein the outside of the chip is a scribe line area and an area on a small wafer rather than one chip being formed. 제1항에 있어서, 상기 연결수단은 금속라인 또는 도핑된 실리콘 라인중 선택된 어느 하나인 것을 특징으로 하는 칩 면적을 감소시키는 패드 배치.The pad arrangement as claimed in claim 1, wherein the connecting means is any one selected from a metal line or a doped silicon line. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038999A 1995-10-31 1995-10-31 Pad Placement Reduces Chip Area KR970023929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950038999A KR970023929A (en) 1995-10-31 1995-10-31 Pad Placement Reduces Chip Area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950038999A KR970023929A (en) 1995-10-31 1995-10-31 Pad Placement Reduces Chip Area

Publications (1)

Publication Number Publication Date
KR970023929A true KR970023929A (en) 1997-05-30

Family

ID=66585058

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950038999A KR970023929A (en) 1995-10-31 1995-10-31 Pad Placement Reduces Chip Area

Country Status (1)

Country Link
KR (1) KR970023929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9859237B2 (en) 2014-11-10 2018-01-02 Samsung Electronics Co., Ltd. Chip using triple pad configuration and packaging method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9859237B2 (en) 2014-11-10 2018-01-02 Samsung Electronics Co., Ltd. Chip using triple pad configuration and packaging method thereof

Similar Documents

Publication Publication Date Title
KR950034544A (en) Semiconductor Wafers and Semiconductor Devices
KR920010906A (en) Semiconductor memory
DE69013646D1 (en) Integrated semiconductor circuit device with contacting areas on the edge of the semiconductor chip.
KR900017129A (en) Back metallization scheme for semiconductor device and manufacturing method thereof
KR970023929A (en) Pad Placement Reduces Chip Area
KR950020965A (en) Semiconductor devices
KR910020875A (en) Leadframe for IC
KR900001020A (en) Semiconductor integrated circuit device
SE9403722D0 (en) Semiconductor device
KR920007509A (en) Thin memory module
KR910001924A (en) Semiconductor devices
ATE375006T1 (en) SECURE INTEGRATED SEMICONDUCTOR CIRCUIT ARRANGEMENT AND MANUFACTURING METHOD
KR970011961A (en) Pad device connecting main pad and dummy pad
KR840009182A (en) Semiconductor devices
KR950021301A (en) Semiconductor devices
KR970023618A (en) Semiconductor device with conductive layer for noise reduction
JPS52122090A (en) Semiconductor integrated circuit device
KR950009994A (en) Metal pad formation method of semiconductor device
KR960024376A (en) Structure of Semiconductor Acceleration Sensor
KR970053179A (en) Device Arrangement Structure of Semiconductor Chip
KR970025321A (en) Static electricity protection circuit of semiconductor device
KR970028813A (en) Reticle for Semiconductor Device Manufacturing
KR960015883A (en) Leadframes for Semiconductor Packages
KR970008561A (en) Transistor of input protection circuit of semiconductor device
KR970018296A (en) Circuit Area Arrangement Method of Semiconductor Device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination