JPS59132655A - Solid-state image pickup device - Google Patents
Solid-state image pickup deviceInfo
- Publication number
- JPS59132655A JPS59132655A JP58007815A JP781583A JPS59132655A JP S59132655 A JPS59132655 A JP S59132655A JP 58007815 A JP58007815 A JP 58007815A JP 781583 A JP781583 A JP 781583A JP S59132655 A JPS59132655 A JP S59132655A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- gate region
- region
- signal charge
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005036 potential barrier Methods 0.000 claims abstract description 16
- 238000003384 imaging method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 3
- 230000005764 inhibitory process Effects 0.000 abstract 1
- 230000001629 suppression Effects 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14887—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は固体撮像装置に関し、特に過大な強度の入射
光に対しても良質の画像出力信号が得られるブルーミン
グ抑止機能を備え、しかも特別のプルーミング抑止制御
信号を印加するための制御ラインが不要であるため、特
別の制御信号電源が不要で、さらに製造上でも特別の制
御ラインを製造する必要がない分だけ歩留り良く製造す
ることができ、したがって安価で高性能な固体撮像装置
を提供するものであり、今後の発展に大きな期待が寄せ
られる固体カメラ分野の業界への寄与は多大なものであ
ると考えられる。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a solid-state imaging device, and in particular has a blooming suppression function that allows a high-quality image output signal to be obtained even with excessively intense incident light, and a special blooming suppression function. Since there is no need for a control line to apply control signals, there is no need for a special control signal power source.Furthermore, since there is no need to manufacture a special control line, the manufacturing yield can be improved due to the fact that there is no need to manufacture a special control line, so the manufacturing cost is low. It provides a high-performance solid-state imaging device, and is considered to have made a significant contribution to the solid-state camera industry, where future development is highly anticipated.
従来例の構成とその問題点
固体撮像装置は従来の撮像管と比較して、小型軽量、低
消費電力性、高信頼性等の特長を有しているため撮像管
にとって代わって小型カメラへの応用が検討されている
。しかし、このような固体撮像装置の欠点のうちの最大
のものに、入射光が過大な強度を有する場合に発生する
プルーミングと呼ばれる強い明かるさの画像のにじみが
存在することが挙げられる。したがって良好な画像出力
信号を得るためにブルーミング抑止機能を備えた各種の
固体撮像装置が提案されつつある。Conventional configuration and its problems Solid-state imaging devices have advantages such as being smaller and lighter, lower power consumption, and higher reliability than conventional image pickup tubes, so they are being used in small cameras instead of image pickup tubes. Applications are being considered. However, one of the biggest drawbacks of such solid-state imaging devices is that images with strong brightness are blurred, which is called pluming, which occurs when incident light has excessive intensity. Therefore, various solid-state imaging devices having a blooming suppression function are being proposed in order to obtain good image output signals.
第１図および第２図は上記ブルーミング抑止機能が備え
られた従来の固体撮像装置の一例の平面図を示す。第１
図は、−列の感光画素列に対して一本のドレイン領域を
有する場合、第２図は１列の感光画素列に対して一本の
ドレイン領域を有する場合を示す。第１図お」：び第２
図において、１ａ、１ｂ・・・・・・および１１ａ、１
１ｂ・・・・・・は半導体基板の表面領域に形成された
フォトダイオード（感光画素）、３ａ、３ｂ−・−・・
・（１３ａ、１３ｂ・・・・・・）および４ａ、４ｂ・
・・・・・（１４ａ、１４ｂ・・・・・・）は上記フォ
トダイオードで得られた光電変換信号を信号出力端へ転
送するための転送ゲート電極列であり、また３ａ 、
ｓｂ−・・（１３ａ 、 １３ｂ・・・）はＣＣＤのス
トレージ電極でもある。４ａ。FIGS. 1 and 2 are plan views of an example of a conventional solid-state imaging device equipped with the blooming suppression function described above. 1st
The figure shows a case in which one drain region is provided for - column of photosensitive pixel columns, and FIG. 2 shows a case in which one drain region is provided for one column of photosensitive pixel columns. Figure 1: and 2
In the figure, 1a, 1b... and 11a, 1
1b... are photodiodes (photosensitive pixels) formed on the surface area of the semiconductor substrate, 3a, 3b...
・(13a, 13b...) and 4a, 4b・
...(14a, 14b...) is a transfer gate electrode array for transferring the photoelectric conversion signal obtained by the photodiode to the signal output terminal, and 3a,
sb-...(13a, 13b...) are also storage electrodes of the CCD. 4a.
４ｂ・・・・・・（１４ａ、１４ｂ・・・）はＣＣＤの
トランスファ電極を示し、捷た２ａ、２ｂ・・・および
１２ａ。4b... (14a, 14b...) indicate CCD transfer electrodes, and 2a, 2b... and 12a are twisted.
１２ｂ・・・ば」１記フォトダイオードと信号電荷読み
出しＣＯＤとの間の読み出しゲート領域を示す。12b... indicates a readout gate region between the photodiode 1 and the signal charge readout COD.
さらに」１記フォトダイオード”１ａ、１ｂ・・・およ
び１１ａ、１１ｂ・・・それぞれの配列方向に沿った側
面には制御ゲート電極６，１５が形成され、上記各制御
ゲート電極５，１５に隣接する上記半導体基板の表面領
域には、高い直流電圧が常時供給されているドレイン領
域６および１６（または６）が形成されている。なお、
上記フォトダイオードと信号電荷読み出しＣＯＤの各転
送ゲート電極列との間にはチャネルストップ領域が形成
されている。Furthermore, control gate electrodes 6 and 15 are formed on the side surfaces of each of the photodiodes 1a, 1b, 11a, 11b, along the arrangement direction, and are adjacent to each of the control gate electrodes 5, 15. Drain regions 6 and 16 (or 6) to which a high DC voltage is constantly supplied are formed in the surface region of the semiconductor substrate.
A channel stop region is formed between the photodiode and each transfer gate electrode row of the signal charge readout COD.
この様な構成において、上記半導体基板上に光が照射さ
れると、フォトダイオード１ａ、１ｂ・・・オヨび１１
ａ、１１ｂ・・・でその入射光量に応じた信号電荷が発
生し、この信号電荷はいったん各フォトダイオードに蓄
積される。次に信号電荷読み出しゲート領域２ａ、２ｂ
・・・および１２ａ、１２ｂ・・・に制御パルスが印加
されると、上記各フォトダイオード１ａ、１ｃ・・・お
よび１１ａ、１１ｃ・・・で蓄積された信号電荷は信号
電流読み出しＣＯＤのストレージ電極３ａ、３Ｃ−・お
よび１３ａ、１３ｃの下のポテンシャル井戸内に移動す
る（インターレース走査の他のフィールドではフォトダ
イオード１ｂ・・・および１１ｂ・・・の信号電荷がス
トレージ電極３ｂ・・・および１３ｂ・・・の下に移動
する）。さらに次にクロックパルスを各転送ゲート電極
３ａ。In such a configuration, when the semiconductor substrate is irradiated with light, the photodiodes 1a, 1b, . . .
A, 11b, . . . generate signal charges corresponding to the amount of incident light, and these signal charges are temporarily accumulated in each photodiode. Next, signal charge readout gate regions 2a, 2b
... and 12a, 12b..., the signal charge accumulated in each of the photodiodes 1a, 1c... and 11a, 11c... is transferred to the storage electrode of the signal current reading COD. 3a, 3C-... and 13a, 13c (in other fields of interlace scanning, the signal charges of the photodiodes 1b... and 11b... move into the potential wells below the storage electrodes 3b... and 13b... ). Furthermore, a clock pulse is then applied to each transfer gate electrode 3a.
３ｂ・・・および４ａ、４ｂ・・・捷た１ ３ａ 、
１３ｂ・・・および１４ａ、１４ｂ・・・に印加すると
、上記の各電極下に予め移動した信号電荷は第１図また
は第２図中上方に向って順次転送され、さらに水平方向
の図示しない水平ＣＯＤを介して、シリアルの画像信号
として出力される。3b... and 4a, 4b... 1 3a,
13b... and 14a, 14b..., the signal charges previously moved under each of the electrodes are sequentially transferred upward in FIG. It is output as a serial image signal via the COD.
ところで、上記従来の装置において、各制御ゲ−）５
、１５には制御電圧が供給され、寸だ各ドロ ｌ 〕
レイン領域６または６および１６にはこれより高い直流
電圧が供給されているため、各制御ゲート５．１５の下
の半導体基板内部にはポテンシャル障壁が形成されてい
る。したがって上記の入射光の強度が非常に強くてフォ
トダイオードで発生する信号電荷が過剰となり上記ポテ
ンシャル障壁を越えれば、この過剰電荷は各ドレイン領
域６および１６（または６）に流れ込むことになる。し
たがって第１図または第２図の従来装置でブルーミング
の発生を抑圧することができる。しかしながら、ドレイ
ン領域６および１６（または６）とフォトダイオード１
ａ、１ｂ−および１１ ａ 、１１ｂとの間に制御ゲー
ト電極５，１５を形成する必要がある。またこの制御ゲ
ート電極５，１６に制御信号を印加するための電源も必
要となる。このことは、固体撮像装置が特別の制御ライ
ンと特別の電源を持つことを意味し、製造歩留りの低下
を招くだけでなく、安価な固体撮像装置を広く世界に提
供するための問題点でもある。By the way, in the above conventional device, each control game) 5
, 15 are supplied with a control voltage, and a DC voltage higher than this is supplied to the rain region 6 or 6 and 16, so that the inside of the semiconductor substrate under each control gate 5.15 is supplied with a control voltage. A potential barrier is formed. Therefore, if the intensity of the incident light is so strong that the signal charge generated in the photodiode becomes excessive and exceeds the potential barrier, this excess charge will flow into each drain region 6 and 16 (or 6). Therefore, the occurrence of blooming can be suppressed using the conventional device shown in FIG. 1 or 2. However, drain regions 6 and 16 (or 6) and photodiode 1
It is necessary to form control gate electrodes 5, 15 between a, 1b- and 11a, 11b. A power source is also required for applying control signals to the control gate electrodes 5 and 16. This means that solid-state imaging devices have special control lines and special power supplies, which not only leads to lower manufacturing yields, but also poses a problem in providing inexpensive solid-state imaging devices to the world. .
発明の目的
この発明は上述の様々事情を考慮してなされたものであ
り、その目的は制御電源の数が少なく、しかもブルーミ
ング抑止機能を具備した高性能の固体撮像装置を製造歩
留り良く提供することである。Purpose of the Invention The present invention has been made in consideration of the various circumstances described above, and its purpose is to provide a high-performance solid-state imaging device with a small number of control power supplies and a blooming suppression function with a high manufacturing yield. It is.
発明の構成
この発明は、ドレイン領域と信号電荷読み出し手段との
間に制御ゲート領域を具備し、さらに上記の制御ゲート
領域を駆動するための電極が該固体撮像装置における感
光画素から信号電荷読み出し手段への読み出しゲート領
域を駆動するための電極と共通の電極であり、１だ同一
の制御パルスを印加する様な構造で、構成される、。Structure of the Invention The present invention comprises a control gate region between a drain region and a signal charge readout means, and further includes an electrode for driving the control gate region that is connected to a signal charge readout means from a photosensitive pixel in the solid-state imaging device. It is a common electrode with the electrode for driving the readout gate region of the cell, and is constructed in such a structure that only one control pulse is applied.
実施例の説明
以下、図面によりこの発明の一実施例を説明する。第３
図はこの発明に係る固体撮像装置の一実施例の構成を平
面図で示したものである１、なお、従来のものと対応す
る箇所には同一の符号を付してその説明は省略し、従来
と異なるところのみを抽出して説明する。すなわち、こ
の実施例の装置ではフォトダイオード１ａ、１ｂ・・・
および１１ａ。DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Third
The figure is a plan view showing the configuration of an embodiment of a solid-state imaging device according to the present invention 1. The same reference numerals are given to the parts corresponding to those of the conventional one, and the explanation thereof will be omitted. Only the points that are different from the conventional method will be extracted and explained. That is, in the device of this embodiment, the photodiodes 1a, 1b...
and 11a.
１１ｂとドレイン領域６の間の制御ゲート電極６゜１６
を取り除き、その代りにドレイン領域６と信号電荷読み
出しＣＯＤのストレージ電極３ａ、３ｂおよび１３ａ、
１３ｂ・・・との間の半導体基板の表面領域に制御ゲー
ト領域７ａ、７ｂ・・・および１７ａ。Control gate electrode 6°16 between 11b and drain region 6
is removed, and instead of the drain region 6 and the storage electrodes 3a, 3b and 13a of the signal charge readout COD,
control gate regions 7a, 7b, .
１７ｂ・・・を形成したものであり、しかも例えば１つ
のフォトダイオード１ａに蓄積された信号電荷をストレ
ージ電極３ａに読み出す際に、ストレージ電極３ａ、読
み出しゲート領域２ａ、制御ゲート領域７ａのそれぞれ
の電極に同一のクロックツくルスを印加するように構成
したものである。すなわち、同図における斜線は上記の
各領域２ａ、３ａ。17b..., and for example, when reading signal charges accumulated in one photodiode 1a to the storage electrode 3a, each electrode of the storage electrode 3a, the readout gate region 2a, and the control gate region 7a. The configuration is such that the same clock pulse is applied to both. That is, the diagonal lines in the figure indicate the above-mentioned regions 2a and 3a.
７ａが共通の電極で形成されていることを示すものであ
る。This shows that 7a is formed of a common electrode.
捷だ、第４図には第３図の一実施例のＡ−Ａｍに沿う断
面図である。第４図において、２０は半導体基板、２１
はゲート絶縁膜、２２は多結晶シリコン電極であり、こ
の電極２２の下に基板２０の表面領域としてフォトダイ
オード１ａ、ドレイン領域６、ストレージ電極３ａ、読
み出しゲート領域２ａ、制御ゲート領域７ａがそれぞれ
形成されている。また、第６図には、第４図の断面図に
示す領域１ａ、２ａ、３ａ、７ａ、６のそれぞれ領域に
対応するポテンシャル（電位）障壁の高さが、第６図に
は共通の多結晶シリコン（第４図の２２）に印加する制
御パルスの例がそれぞれ示されている。4 is a sectional view taken along line A-Am of one embodiment of FIG. 3. In FIG. 4, 20 is a semiconductor substrate, 21
2 is a gate insulating film, 22 is a polycrystalline silicon electrode, and under this electrode 22, a photodiode 1a, a drain region 6, a storage electrode 3a, a read gate region 2a, and a control gate region 7a are formed as surface regions of the substrate 20, respectively. has been done. Furthermore, in FIG. 6, the heights of potential barriers corresponding to regions 1a, 2a, 3a, 7a, and 6 shown in the cross-sectional view of FIG. Examples of control pulses applied to crystalline silicon (22 in FIG. 4) are each shown.
第６図における３０がこの実施例における感光画素から
信号電荷読み出しＣＯＤへの信号読み出しパルスであり
、３１が信号電荷を出力方向へ転送するための転送りロ
ックパルス列である。なお、この駆動パルスは従来の装
置のものと全く同一でありこの発明に特別のものではな
い。In FIG. 6, 30 is a signal read pulse from the photosensitive pixel to the signal charge readout COD in this embodiment, and 31 is a transfer lock pulse train for transferring the signal charge in the output direction. Note that this drive pulse is exactly the same as that of the conventional device and is not special to this invention.
以下、第３．４，５図を用いてこの実施例装置の動作を
説明する。フォトダイオード１ａが空の時の電位が２３
、第４図の多結晶シリコン電極２２への印加電圧が低レ
ベル■Ｌの時の領域２ａ、３ａ。The operation of this embodiment apparatus will be explained below using FIGS. 3.4 and 5. The potential when the photodiode 1a is empty is 23
, regions 2a and 3a when the voltage applied to the polycrystalline silicon electrode 22 in FIG. 4 is at a low level ■L.
７ａのポテンシャルの高さが２６’、 ２７’、 ２
Ｂ’とする。この様にストレージ電極３ａの電位２７８
ｉ０
信号読み出しゲート領域２ａと制御ゲート領域７ａのそ
れぞれの電位障壁の高さ２６．２８’よりも低いことは
もちろんであるが、しかも電位障壁の高さ２６′よりも
２８′の高さの方がたとえば少なくとも０．１ｖ以上は
低くしたことがこの実施例の要点である。この様な電位
障壁の高さの設定の目的は、以下に述べるブルーミング
抑止の動作をスムーズに行なうことである。この状態で
、フォトダイオード１ａに光が入射されると、ダイオー
ド１ａの電位は入射光の強度に対応した電位まで上昇す
る。The potential height of 7a is 26', 27', 2
Let it be B'. In this way, the potential 278 of the storage electrode 3a
i0 Of course, it is lower than the potential barrier height 26.28' of each of the signal readout gate region 2a and the control gate region 7a, and moreover, the potential barrier height 28' is lower than the potential barrier height 26'. The key point of this embodiment is that the voltage is lowered, for example, by at least 0.1v. The purpose of setting the height of the potential barrier in this way is to smoothly perform the blooming suppression operation described below. In this state, when light is incident on the photodiode 1a, the potential of the diode 1a increases to a potential corresponding to the intensity of the incident light.
次に多結晶シリコン電極２２に高レベルｖＨを印加して
、フォトダイオードに蓄積された信号電荷を読み出す場
合の領域２ａ 、３ａ 、７ａのそれぞれの電位障壁の
高さを２６．２７．２８とするとこの時、フォトダイオ
ード１ａに蓄積された信号電荷が２３〜２４までの間で
あり、その電荷量が信号読み出しＣＯＤのストレージ領
域３ａによって転送できる最大電荷量以内の間の信号電
荷である場合は、電位障壁２８を越える電荷は全く存在
しない。Next, when a high level vH is applied to the polycrystalline silicon electrode 22 and the signal charge accumulated in the photodiode is read out, the height of the potential barrier in each of regions 2a, 3a, and 7a is set to 26, 27, and 28. At this time, if the signal charge accumulated in the photodiode 1a is between 23 and 24, and the amount of signal charge is within the maximum amount of charge that can be transferred by the storage area 3a of the signal readout COD, then There is no charge beyond potential barrier 28.
しかるに、入射光の強度が過大でブルーミングを発生す
る様な信号電荷（例えば第６図では２６の電位）がフォ
トダイオード１ａに蓄積された場合には、ＣＯＤのスト
レージ領域３ａには転送できる最大の電荷量が転送され
、残りのいかなる量の信号電荷も、電位障壁２８を越え
てドレイン領域６（電位２９）に排出される。このよう
にして次にクロックパルス（第６図の３１）が印加され
て、出力端子の方向すなわち第５図では紙面の垂転送で
きる最大電荷量を越えることはない訳である。このよう
に過剰な電荷が出力捷で到達しないのであるから、入射
光が過大な強度であってもブルーミングが発生すること
を抑止できるのである。However, if the intensity of the incident light is too high and a signal charge that causes blooming (for example, potential 26 in FIG. 6) is accumulated in the photodiode 1a, the maximum amount of signal charge that can be transferred is stored in the storage area 3a of the COD. The amount of charge is transferred and any remaining amount of signal charge is drained across the potential barrier 28 into the drain region 6 (potential 29). In this way, when the next clock pulse (31 in FIG. 6) is applied, the amount of charge that can be transferred in the direction of the output terminal, that is, vertically to the plane of the paper in FIG. 5, will not be exceeded. Since excess charge does not reach the output terminal in this way, it is possible to prevent blooming from occurring even if the intensity of the incident light is excessive.
なお、第７図にはこの発明の別の実施例を示しである。In addition, FIG. 7 shows another embodiment of the present invention.
同図においても、第３図の実施例と同じ様にゲート領域
２ａ 、３ａ 、７ａ上には共通の電極が設置されてい
るが、領域２ａ 、３ａ 、７ａの配置構成が異ってい
る。駆動の仕方は前述の説明と同様である。−また、第
８図にもこの発明の別の実施例を示した。同図は、固体
撮像装置の感度向上のための光導電体膜積層型の装置に
この発明を実施した場合の例である。この場合には、光
導電体膜によって蓄積される信号電荷の量が、通常のシ
リコン、フォトダイオードだけによる場合よりも大であ
るため、この発明によるブルーミングの抑止は積層型の
固体撮像装置における特性向上のうえで欠くことのでき
ない技術といえる。第８図において、２０〜２２および
１ ａ〜３ ａ 、 ６．７ａは第４図と同じである。In the figure as well, common electrodes are provided on the gate regions 2a, 3a, and 7a as in the embodiment of FIG. 3, but the arrangement of the regions 2a, 3a, and 7a is different. The driving method is the same as described above. - Another embodiment of the invention is also shown in FIG. This figure shows an example in which the present invention is applied to a photoconductor film laminated type device for improving the sensitivity of a solid-state imaging device. In this case, the amount of signal charge accumulated by the photoconductor film is larger than that by ordinary silicon or photodiodes alone, so the suppression of blooming by this invention is a characteristic of stacked solid-state imaging devices. It can be said that this is an indispensable technique for improvement. In FIG. 8, 20 to 22, 1a to 3a, and 6.7a are the same as in FIG.
３４．３５の絶縁膜でかこまれた導体３２．３３を介し
て、フォトダイオード１ａと光導電体膜３６が結合され
ている。The photodiode 1a and the photoconductor film 36 are coupled through conductors 32 and 33 surrounded by insulating films 34 and 35.
３７は透明電極である。37 is a transparent electrode.
発明の効果
以上で説明したように、この発明によれば、従来の装置
に比べてもブルーミング抑止効果は全く低下することな
く、またブルーミング抑止のために特別の電源や制御ラ
インを増加することなく、従来の装置の駆動パルスと全
く同一のパルスを用３
いて、高性能で安価な固体撮像装置が歩留り良く提供で
きるという効果がある。Effects of the Invention As explained above, according to the present invention, the blooming suppression effect does not decrease at all compared to conventional devices, and there is no need to increase special power supplies or control lines for blooming suppression. This has the effect that a high-performance, inexpensive solid-state imaging device can be provided with a high yield by using pulses that are exactly the same as the driving pulses of conventional devices.
第１図および第２図はそれぞれブルーミング抑止機能を
具備した従来の固体撮像装置の概略平面構成を示す図、
第３図はこの発明の一実施例の固体撮像装置の概略平面
図、第４図は第３図の八−Ａ′線に沿う断面図、第６図
は上記実施例を説明するための第３図の各ゲート領域に
おける電位障壁の高さを示す図、第６図は第３図の実施
例を駆動するパルス波形図、第７図、第８図はそれぞれ
この発明の他の実施例の固体撮像装置の概略平面図、断
面図である。
１ａ、１ｂ・・・・・・、１１ａ、１１ｂ・・・・・・
感光画素。
′ ２ａ、２ｂ・・・・・・、１２ａ、１２ｂ・・・・
・・読み出しゲート領域、３ａ、３ｂ・・・・・・、１
３ａ、１３ｂ・・・・・・信号読み出しＣＯＤのストレ
ージ領域、４ａ 、４ｂ・・・・・・、１４ａ、１４ｂ
・・・・・・信号読み出しＣＯＤのトランスファ領域、
５，１５．７ａ、７ｂ・・・・・・。
１７ａ、１７ｂ・・・・・制御ゲート、６・・・・・・
ドレイン４
領域、２０・・・・・・半導体基板、２１・・・・・・
ゲート絶縁膜、２２・・・・・・多結晶シリコン電極。
代理人の氏名 弁理士 中 尾 敏 男 はが１名−〜
Ｗ 雑
纂 ３ 図
第４図
第５図
第６図
纂８図FIG. 1 and FIG. 2 are diagrams showing a schematic plan configuration of a conventional solid-state imaging device equipped with a blooming suppression function, respectively;
3 is a schematic plan view of a solid-state imaging device according to an embodiment of the present invention, FIG. 4 is a sectional view taken along line 8-A' in FIG. 3, and FIG. 6 is a diagram for explaining the above embodiment. FIG. 3 is a diagram showing the height of the potential barrier in each gate region, FIG. 6 is a pulse waveform diagram for driving the embodiment of FIG. 3, and FIGS. 7 and 8 are diagrams of other embodiments of the present invention. FIG. 1 is a schematic plan view and a cross-sectional view of a solid-state imaging device. 1a, 1b..., 11a, 11b...
photosensitive pixel. ' 2a, 2b..., 12a, 12b...
...Reading gate region, 3a, 3b..., 1
3a, 13b...Storage area for signal readout COD, 4a, 4b..., 14a, 14b
・・・・・・Transfer area of signal readout COD,
5, 15.7a, 7b... 17a, 17b...control gate, 6...
Drain 4 region, 20... semiconductor substrate, 21...
Gate insulating film, 22...polycrystalline silicon electrode. Name of agent Patent attorney Toshio Nakao 1 person ~ W Miscellaneous 3 Figure 4 Figure 5 Figure 6 Figure 8
Claims (1)
変換信号を発生し蓄積する複数の感光画素と、」二記複
数の感光画素に蓄積された信号電荷を読み出す手段と、
上記複数の感光画素の配列方向に沿って上記半導体基板
の表面領域に設けられた基板とは逆導電型のドレイン領
域と、上記ドレイン領域と上記信号電荷読み出し手段と
の間の制御ゲート領域とを具備し、上記の感光画素と信
号電荷読み出し手段との間の信号電荷読み出しゲート領
域と上記のドレイン領域と信号電荷読み出し手段との間
の制御ゲート領域とを共通の電極で形成するとともに、
」二記の共通電極に制御信号を印ＪＪ口することにより
上記複数の感光画素に発生した過剰の信号、電荷を」−
記ドレイン領域へ排出することを特徴とする固体撮像装
置。 （功 感光画素と信号電荷読み出し手段との間の信号電
荷読み出しゲート領域の電位障壁の高さよりも、ドレイ
ン領域と信号電荷読み出し手段との間 ′の制御ゲート
領域の電位障壁の高さの方を低くしたことを特徴とする
特許請求の範囲第１項に記載の固体撮像装置。(1) a plurality of photosensitive pixels on a semiconductor substrate that generate and accumulate photoelectric conversion signals according to the amount of incident light; and (2) means for reading signal charges accumulated in the plurality of photosensitive pixels;
a drain region of a conductivity type opposite to that of the substrate provided on the surface region of the semiconductor substrate along the arrangement direction of the plurality of photosensitive pixels; and a control gate region between the drain region and the signal charge readout means. forming a signal charge readout gate region between the photosensitive pixel and the signal charge readout means and a control gate region between the drain region and the signal charge readout means with a common electrode;
"By applying a control signal to the common electrode mentioned above, the excess signal and charge generated in the plurality of photosensitive pixels can be removed."
What is claimed is: 1. A solid-state imaging device characterized by discharging water to a drain region. (The height of the potential barrier in the control gate region between the drain region and the signal charge readout means is higher than the height of the potential barrier in the signal charge readout gate region between the photosensitive pixel and the signal charge readout means.) The solid-state imaging device according to claim 1, characterized in that the height of the solid-state imaging device is lowered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58007815A JPS59132655A (en) | 1983-01-19 | 1983-01-19 | Solid-state image pickup device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58007815A JPS59132655A (en) | 1983-01-19 | 1983-01-19 | Solid-state image pickup device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59132655A true JPS59132655A (en) | 1984-07-30 |
| JPH035672B2 JPH035672B2 (en) | 1991-01-28 |
Family
ID=11676087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58007815A Granted JPS59132655A (en) | 1983-01-19 | 1983-01-19 | Solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132655A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132659A (en) * | 1983-01-20 | 1984-07-30 | Matsushita Electric Ind Co Ltd | Solid-state image pickup device |
| US6674470B1 (en) | 1996-09-19 | 2004-01-06 | Kabushiki Kaisha Toshiba | MOS-type solid state imaging device with high sensitivity |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5793568A (en) * | 1980-12-02 | 1982-06-10 | Nec Corp | Semiconductor image pickup element |
-
1983
- 1983-01-19 JP JP58007815A patent/JPS59132655A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5793568A (en) * | 1980-12-02 | 1982-06-10 | Nec Corp | Semiconductor image pickup element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59132659A (en) * | 1983-01-20 | 1984-07-30 | Matsushita Electric Ind Co Ltd | Solid-state image pickup device |
| US6674470B1 (en) | 1996-09-19 | 2004-01-06 | Kabushiki Kaisha Toshiba | MOS-type solid state imaging device with high sensitivity |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH035672B2 (en) | 1991-01-28 |
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