JPS59132171A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS59132171A
JPS59132171A JP584783A JP584783A JPS59132171A JP S59132171 A JPS59132171 A JP S59132171A JP 584783 A JP584783 A JP 584783A JP 584783 A JP584783 A JP 584783A JP S59132171 A JPS59132171 A JP S59132171A
Authority
JP
Japan
Prior art keywords
ions
etching
electrode
schottky
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP584783A
Other languages
Japanese (ja)
Inventor
Haruhisa Kinoshita
木下 治久
Yoshiaki Sano
佐野 芳明
Toshimasa Ishida
俊正 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP584783A priority Critical patent/JPS59132171A/en
Publication of JPS59132171A publication Critical patent/JPS59132171A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To improve an ideal coefficient of a diode, by performing beam etching by the mixed gas ions of argon ions and oxygen ions. CONSTITUTION:A diode having a Schottky junction comprises an N<+> GaAs substrate 1, an N-GaAs layer 2, a Ti electrode 3 forming a Schottky junction, and an AuGe/Ni/Au electrode 4 forming ohmic contact with the substrate 1. In manufacturing the Schottky diode, the layer 2 is made clean by etching immediately before the electrode 3 is evaporated. When ion beam etching is used by the mixed gas ions of argon ions and oxygen ions, an ideal coefficient is improved.

Description

【発明の詳細な説明】 (技術分野) 本発明は電気的な特性が良好なショットキ接合半導体素
子の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a Schottky junction semiconductor device with good electrical characteristics.

(背景技術) 第1図はショットキ接合をなすダイオードの断面図であ
シ、1は1×lOcnn 程度のキャリア密度をもつn
−GaAs基板、2はlXl0 cm  程度のキャリ
ア密度の2000X程度の厚さのn−GaAs層、3は
ショットキ接合をなすTi電極、4はn”−GaAs基
板1′とオーミック接合をなすAu−Ge/Ni/Au
電極である。このようなショットキダイオードの製作に
おいて30Ti電極を蒸着する直前に2のn−GaAs
の表面をエツチングによって清浄化しなければならない
。化学的エツチング゛によりた場合は化学反応を利用し
て表面上の異物を取り除くた−め、化学的に不活性な異
物は取り除くことが不可能であり、一般的にこれらの異
物のGaAS基板表面上の分布は不均一であるため、こ
のようにして製作したショットキダイオードの電気的性
質のバラつきの分布は悪くなる。
(Background Art) Figure 1 is a cross-sectional view of a diode forming a Schottky junction, where 1 has a carrier density of about 1×lOcnn.
-GaAs substrate, 2 is an n-GaAs layer with a thickness of about 2000X with a carrier density of about lXl0 cm, 3 is a Ti electrode forming a Schottky junction, and 4 is an Au-Ge layer forming an ohmic contact with the n''-GaAs substrate 1'. /Ni/Au
It is an electrode. In the fabrication of such a Schottky diode, just before depositing the 30Ti electrode, 2 n-GaAs
The surface must be cleaned by etching. When using chemical etching, foreign matter on the surface is removed using a chemical reaction, so it is impossible to remove chemically inert foreign matter, and generally these foreign matter are removed from the surface of the GaAS substrate. Since the above distribution is non-uniform, the Schottky diode manufactured in this way has a poor distribution of variations in electrical properties.

(発明の目的) 本発明の目的は、物理的エツチングによって清浄化する
ことにあり、アルゴンイオン(Ar)と酸素イオン(0
□)′との混合ガスイオンによるイオンビームエツチン
グを採用して、ダイオードのアイディアル係数nの向上
を図ったものである。
(Object of the Invention) The object of the present invention is to perform cleaning by physical etching, in which argon ions (Ar) and oxygen ions (0
The ideal coefficient n of the diode is improved by employing ion beam etching using mixed gas ions with □)'.

(発明の構成〕 第2図は本発明を説明するための特性図であり、横軸は
イオンエネルギであり、縦軸はダイオード9の整流特性
におけるアイディアル係数nである。
(Structure of the Invention) FIG. 2 is a characteristic diagram for explaining the present invention, in which the horizontal axis represents ion energy and the vertical axis represents the ideal coefficient n in the rectification characteristics of the diode 9.

第2図には、本発明の一実施例であるAr102(1:
1)イオンエツチング特性の他に、Arイオンエツチン
グ特性及び化学エツチング特性を示している。
FIG. 2 shows Ar102 (1:
1) In addition to ion etching characteristics, Ar ion etching characteristics and chemical etching characteristics are shown.

Ar102(=1 : 1 )イオンエツチング特性は
、n−GaAs2表面をArと02の流量比が1:1の
混合ガスイオンによってイオンビームエツチングしり後
、そのエッチンノ表面にT1電極を蒸着し、その後、大
気圧のN2ガス雰囲気中で300℃20分間アニとルし
てショットキ半導体素子を作成し、そしてシff7トキ
T1電極3とオーミータAu−Ge/Ni/Au電極4
との間にバイアス電圧をかけてn値を測定したものであ
る。Ar102 (1: 1. )ガスによってイオン
ビームエツチングしたn −GaAs表面はAr、l!
ZQ2のイオンによって物理的にスノク、タリングされ
ているため非常に清浄であり、素子間でのバラつきが小
さい。またイオンビームエツチングによるとGaAsの
表面層に数百X程度の深さの損傷を与えるが、Arに0
2を1:1の流量比で混合した場合においては100 
eVと300 eVのイオンエネルギでエツチングした
場合n値が118と123とかなり良好であり、リーク
電流に与える影響は化学エツチングと同等に良好である
。このことによりArと′02の混合ガスによるイオン
ビームエツチングでは約30’OeV以下のエスルギを
もったイオンによって表面清浄をしても表面層の損傷の
程度は軽く、大気圧のN2中で300℃20分間の熱処
理によって容易に回復することがわかる。300℃以上
の温度による熱処理の一例として、350℃にて20分
間大気圧のN2雰囲気中で第1図に示したショットキダ
イオードを熱処理してもn値はほとんど変わらない。他
方、第2図から明らかなように、Arイオンビームエツ
チングによった場合には、100eVでn値は13Gと
悪く、300℃20分間程度の熱処理では回復していな
い。なお、Arイオンのエネルギを50 eVまで小さ
くすると、−大気圧のN2jス雰囲気中300℃20分
間の熱処理によってn値ば114と回復しているが、5
0ev程度までイオンエネルギを下げるとエツチングス
ピードが場所によって不均一に々す、実際上棟J[1シ
難くなる。
Ar102 (=1:1) ion etching characteristics are as follows: After ion beam etching the n-GaAs2 surface with mixed gas ions with a flow rate ratio of Ar and O2 of 1:1, a T1 electrode is deposited on the etched surface, and then, A Schottky semiconductor device was produced by annealing at 300° C. for 20 minutes in a N2 gas atmosphere at atmospheric pressure, and then a Schottky semiconductor device was fabricated with a Schottky T1 electrode 3 and an ohmitter Au-Ge/Ni/Au electrode 4.
The n value was measured by applying a bias voltage between the two. The n-GaAs surface ion-beam etched with Ar102 (1:1.) gas is Ar,l!
It is very clean because it is physically snoked and tarred by ZQ2 ions, and there is little variation between elements. Furthermore, ion beam etching damages the surface layer of GaAs to a depth of several hundred times, but Ar
2 is mixed at a flow rate ratio of 1:1, 100
When etching with ion energies of 300 eV and 300 eV, the n values are 118 and 123, which are quite good, and the effect on leakage current is as good as chemical etching. As a result, in ion beam etching using a mixed gas of Ar and '02, the degree of damage to the surface layer is slight even if the surface is cleaned by ions with an energy of less than about 30'OeV, and the degree of damage to the surface layer is slight at 300°C in N2 at atmospheric pressure. It can be seen that it is easily recovered by heat treatment for 20 minutes. As an example of heat treatment at a temperature of 300° C. or higher, the n value hardly changes even if the Schottky diode shown in FIG. 1 is heat-treated at 350° C. for 20 minutes in an N2 atmosphere at atmospheric pressure. On the other hand, as is clear from FIG. 2, when Ar ion beam etching was used, the n value was poor at 13 G at 100 eV, and was not recovered by heat treatment at 300° C. for about 20 minutes. Note that when the energy of Ar ions was reduced to 50 eV, the n value recovered to 114 by heat treatment at 300°C for 20 minutes in a N2j atmosphere at -atmospheric pressure, but the n value recovered to 114;
If the ion energy is lowered to about 0ev, the etching speed will be uneven depending on the location, and it will actually become difficult to etch the upper surface.

又)02イオンによるエツチング例左シては、300 
eVでエツチングしたショットキダイオードを300℃
と350Cで熱処理した場合n値が13】と111とな
って、350℃の熱処理かがなり有効表なる。Lかしo
2イオンのエツチングレートはArイオンの場合と比較
して約1/1oと大巾2   に小さく 、OK Ar
を混合する事によりエラチングレートがかなり増大する
ので、GaAs表面の清浄化にはArと02の混合ガス
によるイオンビームエツチングが適している。
Also, the example on the left of etching with 02 ions is 300
Schottky diode etched with eV at 300℃
When heat treated at 350C, the n value becomes 13] and 111, indicating that the heat treatment at 350C is more effective. L Kashio
The etching rate of 2 ions is about 1/1o, which is about 2 times smaller than that of Ar ions, and OK Ar
Ion beam etching using a mixed gas of Ar and 02 is suitable for cleaning the GaAs surface because the etching rate increases considerably by mixing the two gases.

(発明の効果) 本発明は物理的スパッタリング作用をもっArと02の
混合がスイオンによる半導体表面の清浄化を行りている
ので表面上に付着した酸化物、有機物等を容易に除去す
る事ができ、電気的特性の再現性2面内分布の優れたシ
ョットキ接合を形成可能であるから、MESFETのダ
ートリセス部の−)ッチングに利用することができ、ま
た本発明は物理的ス・ぐツタリングを利用しているので
GaAs以外の無機半導体妬も適用可能である。
(Effects of the Invention) In the present invention, the mixture of Ar and O2, which has a physical sputtering effect, cleans the semiconductor surface using sions, so oxides, organic substances, etc. attached to the surface can be easily removed. Since it is possible to form a Schottky junction with excellent reproducibility and in-plane distribution of electrical characteristics, it can be used for -) etching of dirt recesses in MESFETs. Therefore, inorganic semiconductors other than GaAs can also be applied.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はンヨットキ半導体素子例を示す断面図、第2図
は本発明の説明に用いる特性図であっ゛て、ショットキ
半導体素子のn値のイオンエネルギ依存性の説明図であ
る。 1 ・−n−GaAs基板、2− n −GaAs層、
3−ン。 ットキ接合Ti電極、4・・オーミック電極。 特許出願人 沖電気工業株式会社 第1図 第2図 イスノエネVへ−(eVl 手続補正書(鮭) 1 事件の表示 昭和58年 特 許 願第005847号2、発明の名
称 半導体素子の製造方法 3 補正をする者 事件との関係      特 許 出 願 人件 所(
〒105)  東京都港区虎ノ門1丁目7番12号4、
代理人 住 所(〒105)  東京都港区虎ノ門1丁目7番1
2号5、補正の対象 明細書中1発明の詳細な説明」の
欄及び「図面の簡単な説明jの欄− 6、補正の内容 別紙のとおシ ロ、補正の内容 I1第2頁第13行目の「エツチングにて」のあとに「
半導体表面を」を挿入すr+/す (2)同書第2貞第20行目に「イオンエネルギであシ
」とあるのを「イオンエネルギーであり」と補正する。 (3)同書第3貞第10行目に「ショットキ半導体素子
」とあ\るのを「ショットキ接合半導体素子」と補正す
る。 (4) 同書第3頁・第20行目に「イオンエネルキコ
乙のを「イオンエネルギー」と補正する。 (5)  同書第5貞第6行目に「02イオンの」とあ
るのを「02イオンによるGaAsの」と補正する。 1第6頁第3行目と第5行目に「ショソ半導体素子」と
あるのを「ショットキ接合半導体素子」と補正する。 (7)同書第6頁第5行目に「イオンエネルギ」とある
のを「イオンエネルギー」と補正する。
FIG. 1 is a sectional view showing an example of a Schottky semiconductor device, and FIG. 2 is a characteristic diagram used to explain the present invention, which is an explanatory diagram of the dependence of the n value of the Schottky semiconductor device on ion energy. 1.-n-GaAs substrate, 2- n-GaAs layer,
3-n. 4. Ohmic electrode. Patent Applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 2 To IsunoEne V - (eVl Procedural Amendment (Salmon) 1 Indication of Case 1982 Patent Application No. 005847 2 Name of Invention Method for Manufacturing Semiconductor Elements 3 Relationship with the case of the person making the amendment Patent application Personnel office (
105) 1-7-12-4 Toranomon, Minato-ku, Tokyo.
Agent address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
No. 2 No. 5, Subject of amendment 1. Detailed explanation of the invention in the specification” column and “Brief explanation of the drawings j” column - 6. Contents of amendment Attachment 2, Contents of amendment I1, page 2, line 13 After ``by etching'' in the eyes, ``
Insert "Semiconductor surface" r+/su (2) In the 20th line of the second chapter of the same book, "Ion energy" is corrected to "Ion energy". (3) In the 10th line of No. 3 of the same book, the phrase "Schottky semiconductor device" is corrected to "Schottky junction semiconductor device." (4) On page 3, line 20 of the same book, ``Ion Energy is corrected to ``Ion Energy''. (5) In the 6th line of No. 5 of the same book, the phrase "of 02 ions" is corrected to "of GaAs by 02 ions." 1, page 6, lines 3 and 5, the words "Shosso semiconductor device" are corrected to read "Schottky junction semiconductor device." (7) In the same book, page 6, line 5, "ion energy" is corrected to "ion energy."

Claims (1)

【特許請求の範囲】[Claims] アルゴンイオンと酸素イオンとの混合ガスイオンによる
イオンビームを照射して半導体表面をエツチングする工
程と、そのエツチング表面にショットキ接合をなす金属
を形成する工程と、その後、イオンビーム損傷回復の熱
処理を行なう工程とを備えた半導体素子の製造方法。
A process of etching the semiconductor surface by irradiating the semiconductor surface with an ion beam using mixed gas ions of argon ions and oxygen ions, a process of forming a metal forming a Schottky junction on the etched surface, and then a heat treatment to recover from the ion beam damage. A method for manufacturing a semiconductor device, comprising the steps of:
JP584783A 1983-01-19 1983-01-19 Manufacture of semiconductor element Pending JPS59132171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP584783A JPS59132171A (en) 1983-01-19 1983-01-19 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP584783A JPS59132171A (en) 1983-01-19 1983-01-19 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS59132171A true JPS59132171A (en) 1984-07-30

Family

ID=11622397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP584783A Pending JPS59132171A (en) 1983-01-19 1983-01-19 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS59132171A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610999B2 (en) * 1998-04-06 2003-08-26 California Institute Of Technology Multiple stage high power diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610999B2 (en) * 1998-04-06 2003-08-26 California Institute Of Technology Multiple stage high power diode

Similar Documents

Publication Publication Date Title
JPS59132171A (en) Manufacture of semiconductor element
JPH0361346B2 (en)
JPS59130425A (en) Manufacture of ohmic electrode
KR100459885B1 (en) Method for forming a metal electrode on the semiconductor
JP3162181B2 (en) Semiconductor manufacturing method
JP2780501B2 (en) Semiconductor wafer with insulating film and method of manufacturing the same
JPS6266629A (en) Forming method for thin film
JPS628575A (en) Semiconductor device
JPS6077467A (en) Manufacture of field effect transistor
JP2637950B2 (en) Surface cleaning method
JPH03116834A (en) Manufacture of semiconductor structure using n-type gaas
JPS6143484A (en) Formation of electrode in semiconductor device
JPH0544184B2 (en)
JPS5988830A (en) Semiconductor structure
JPH0380542A (en) Semiconductor integrated circuit device
JPH05251404A (en) Dry etching method for dielectric layer
JPS60116178A (en) Semiconductor device and manufacture thereof
JPS604214A (en) Manufacture of semiconductor device
JPH01107577A (en) Manufacture of field effect transistor
JPH07101695B2 (en) Method for manufacturing semiconductor device
JPH0740605B2 (en) Method for manufacturing semiconductor device
JPS6292432A (en) Manufacture of compound semiconductor device
JPS61270829A (en) Surface cleaning method
JPH04256317A (en) Etching method for semiconductor substrate
JPS63173319A (en) Heat treatment of compound semiconductor