JPS604214A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS604214A
JPS604214A JP11217283A JP11217283A JPS604214A JP S604214 A JPS604214 A JP S604214A JP 11217283 A JP11217283 A JP 11217283A JP 11217283 A JP11217283 A JP 11217283A JP S604214 A JPS604214 A JP S604214A
Authority
JP
Japan
Prior art keywords
layer
deposited
electrode
gaas
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11217283A
Other languages
Japanese (ja)
Inventor
Haruo Kakuwa
角和 晴夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11217283A priority Critical patent/JPS604214A/en
Publication of JPS604214A publication Critical patent/JPS604214A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To reduce a reversal direction leakage current of a Schottky junction by a method wherein Al is deposited on a main surface of a gallium arsenite wafer and, after a heat-treatment, the aluminium layer and a reactive product layer are removed by etching and then a junction electrode is formed. CONSTITUTION:A thin N type layer 5 is formed on the main surface of an N<+> GaAs substrate 4 by an epitaxial growth. An SiO2 film 2 is formed on the surface of the thin layer 5 and a part of the SiO2 film where a Schottky junction is to be formed is removed by etching and the N type layer is exposed. After an aluminium layer 6 is formed on the whole surface, a thin GaAlAs layer 7 is formed by a heat-treatment of the GaAs wafer. Because of a diffusion during the heat-treatment, impurities of the surface of the N type layer 5 and heavy metals are captured into the GaAlAs layer 7 and removed with the aluminium layer 6 and the GaAlAs layer 7 by a hydrochloric acid etching. The tantallum layer 8 is deposited and a metal layer 9 is deposited on the tantalum layer 8 and the metal layer 9 and the tantallum layer 8 other than the electrode part are removed by an etching. Then on the backside of the substrate 4, an ohmic electrode 10 made of a gold/germanium alloy is formed. With this constitution, a reversal direction leakage current of the Schottky junction can be reduced and a contact resistance between the electrode metal and the GaAs wafer can be made uniform with low resistance.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は砒化ガリウム(C,aAs )ウェハの主表面
上に接合電極を形成する半導体装置の製造方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which a bonding electrode is formed on the main surface of a gallium arsenide (C, aAs) wafer.

〔発明の技術的背景およびその問題点〕一般に、半導体
装置は電極を介して電気信号の授受を行ない動作するも
のであるから、その電極の役割は極めて重要である。
[Technical Background of the Invention and Problems Therewith] Generally, semiconductor devices operate by transmitting and receiving electrical signals through electrodes, so the role of the electrodes is extremely important.

従来、GaAsウェハに電極を形成する場合は、まず、
第1図(lL)に示すように、n+GaAs基板Iの電
基板酸面上を化学的な方法で処理し、その表面に絶縁物
である二酸化シリコン膜(SIO2膜)2を堆積させ、
さらにフォトエツチング(以下PEPという)を用いて
S 102膜2を所定の形状に窓開けを行う。次に第1
図(b)に示すように。
Conventionally, when forming electrodes on a GaAs wafer, first,
As shown in FIG. 1 (lL), the acid surface of the electrical substrate of the n + GaAs substrate I is treated by a chemical method, and a silicon dioxide film (SIO2 film) 2, which is an insulator, is deposited on the surface.
Furthermore, a window is opened in the S102 film 2 into a predetermined shape using photoetching (hereinafter referred to as PEP). Then the first
As shown in figure (b).

GaAs基板表面をエツチングし、さらに全面に金属膜
を真空蒸着により被着して電極金属3を形成し、次にP
EPにより不要の金属膜をエツチング除去する。その後
、熱処理等を施すことにより所望とする電極を得ている
The surface of the GaAs substrate is etched, and a metal film is further deposited on the entire surface by vacuum evaporation to form an electrode metal 3.
Etch and remove unnecessary metal film using EP. Thereafter, a desired electrode is obtained by performing heat treatment or the like.

しかしながら、このような方法により製造された電極は
GaAs基板と接合をなす金属との界面にPEP 、エ
ツチング等の処理で生じた不純物や重金属が付着してお
り、特に、ショットキ接合を形成する場合、これら不純
物や重金属がショットキ接合の逆方向リーク電流の増大
の原因として作用したり、又オーミック接触の場合にも
電圧電流特性に整流性が出たり、接触面全体に均一で低
い接触抵抗が得られない等の不都合が発生することがあ
った。この様な現象を抑制する為に、一般的には露出し
でいる接合面を工。
However, in electrodes manufactured by such a method, impurities and heavy metals generated by processes such as PEP and etching adhere to the interface between the GaAs substrate and the metal that forms the bond, especially when forming a Schottky junction. These impurities and heavy metals can act as a cause of increasing reverse leakage current in Schottky junctions, and even in the case of ohmic contacts, they can cause rectification in the voltage-current characteristics, making it difficult to obtain uniform and low contact resistance over the entire contact surface. Inconveniences may occur, such as not being able to do so. In order to suppress this phenomenon, the exposed joint surfaces are generally machined.

チ/グにて深く除去し、比抵抗の高い(15MΩ以上)
純水で何度も洗浄したり、又、オーミック接触の接触抵
抗を低減する為に、例えばケ゛ルマニウムを電極形成用
の金属に微量添加し、熱処理を行うこと等が前述の不都
合に対処するための比較的有効な手段として知られてい
る。しかし、以上の方法では、前者については純水洗浄
をいくらていねいに行っても充分に満足できる程清浄な
GaAs表面を得ることは難しく、又、後者の方法にお
いても低接触抵抗のオーミ、り接触を得ることは、技術
的に困難である場合が多かっブζ。
Deeply removed with chi/g, high resistivity (15MΩ or more)
In order to deal with the above-mentioned disadvantages, washing the electrode repeatedly with pure water, adding a small amount of kermanium to the electrode forming metal, and performing heat treatment to reduce the contact resistance of the ohmic contact, etc. It is known as a relatively effective method. However, with the above methods, it is difficult to obtain a sufficiently clean GaAs surface no matter how carefully the pure water cleaning is performed, and even with the latter method, it is difficult to obtain a sufficiently clean GaAs surface with low contact resistance. It is often technically difficult to obtain ζ.

〔発明の目的〕[Purpose of the invention]

本発明は上記の事情に鑑みてなされたもので、GaAs
基板表面に付着している不純物や重金属を、GaAs基
板に何等拶傷を与えることなく確実に除去して清浄なG
aAs基板表面を得ることにより、ショットキ接合の逆
方向リーク電流を減少し得。
The present invention has been made in view of the above circumstances.
Clean G that reliably removes impurities and heavy metals adhering to the substrate surface without causing any damage to the GaAs substrate.
By obtaining an aAs substrate surface, the reverse leakage current of the Schottky junction can be reduced.

且つ電極金属とGaAs基板との接触抵抗を接触面全面
にわたって均一に低抵抗で形成し得る半導体装置の製造
方法を提供することを目的とする。
Another object of the present invention is to provide a method for manufacturing a semiconductor device that can uniformly form a low contact resistance between an electrode metal and a GaAs substrate over the entire contact surface.

〔発明の概要〕[Summary of the invention]

本発明は、GaAsウェハの主表面上に電極を形成する
にあたり、あらかじめGaAsウェノへの主表面上にア
ルミニウムを蒸着させ熱処理し、しかるのち、蒸着した
アルミニウム層−及び熱処理によって形成された砒化ガ
リウムとアルミニウムの反応生成層をエツチング除去し
ておき、次にGaAgウェハの主表面に所要金属を蒸着
して接合電極を形成する半導体装置の製造方法である。
In the present invention, when forming an electrode on the main surface of a GaAs wafer, aluminum is deposited on the main surface of the GaAs wafer in advance and heat treated, and then the deposited aluminum layer and the gallium arsenide formed by the heat treatment are deposited on the main surface of the GaAs wafer. This is a method of manufacturing a semiconductor device in which a reaction product layer of aluminum is removed by etching, and then a required metal is deposited on the main surface of a GaAg wafer to form a bonding electrode.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

即ち、第2図はタンタル(Ta)−n型GaAsショッ
トキバリヤダイオードを本発明に適用した場合の実施例
會その製造工程に従って示すものである。第2図(、)
はn+GaAs基板4の主表面上に15〜2.0μm程
度の厚さでキャリア濃度2X 10”cm−3の薄いn
型層5をエピクキンヤル成長技術により形成したことを
示す。さらに、第2図(b)はこのn型層50表面にS
 iO2膜2等の絶縁膜をCVD法で形成し、PEPを
用いてショットキ接合となる部分のn型層5上の前記S
 iO2膜2をエツチングして取り除き、n型層5を露
出させたことを示す。次に第2図(C)は、露出したn
型層5を含めた表面全体にアルミニウム層6を蒸着法を
用いて2000iから3000 、J被着したことを示
す。この際、基板加熱(約100℃)を行うと、露出し
たn型層5の表面に吸着したガスが除去でき表面清浄化
に寄与して有効である。次に、このようにして形成され
たGaAsウェハを還元雰囲気(水素ガス)の炉に入れ
温度200℃程度で10分間の熱処理を行う。この熱処
理によりアルミニウム層6は固相拡散に、↓二り接触す
るn型層5中に侵入し、非常に薄いGaAtAs層7を
形成していく、これを第2図(d)に示す。この熱処理
中の拡散でアルミニウム層6と接触するn型層5表面に
付着していた不純物や重金属は拡散進行に伴ない反応生
成したGaklA s層7中に取り込まれる。ギの後、
塩酸で処理することによりアルミニウム層6及びGaA
tAs層7はエツチングされ取り込まれた不純物や重金
属も同時に除去される。
That is, FIG. 2 shows an embodiment in which a tantalum (Ta)-n-type GaAs Schottky barrier diode is applied to the present invention according to its manufacturing process. Figure 2 (,)
is a thin n layer on the main surface of the n+GaAs substrate 4 with a thickness of about 15 to 2.0 μm and a carrier concentration of 2×10”cm−3.
It is shown that the mold layer 5 was formed by an epicyclic growth technique. Furthermore, FIG. 2(b) shows that S is on the surface of this n-type layer 50.
An insulating film such as the iO2 film 2 is formed by the CVD method, and the S on the n-type layer 5 in the portion that will become the Schottky junction is formed using PEP.
This shows that the iO2 film 2 is etched away and the n-type layer 5 is exposed. Next, FIG. 2(C) shows the exposed n
It shows that an aluminum layer 6 of 2000i to 3000J was deposited on the entire surface including the mold layer 5 using a vapor deposition method. At this time, heating the substrate (about 100° C.) is effective because gas adsorbed on the exposed surface of the n-type layer 5 can be removed, contributing to surface cleaning. Next, the GaAs wafer thus formed is placed in a furnace in a reducing atmosphere (hydrogen gas) and subjected to heat treatment at a temperature of about 200° C. for 10 minutes. Through this heat treatment, the aluminum layer 6 penetrates into the n-type layer 5 in two-way contact with solid phase diffusion, forming a very thin GaAtAs layer 7, as shown in FIG. 2(d). Due to diffusion during this heat treatment, impurities and heavy metals adhering to the surface of the n-type layer 5 in contact with the aluminum layer 6 are taken into the GaklAs layer 7 which is reacted and produced as the diffusion progresses. After Gi,
Aluminum layer 6 and GaA are removed by treatment with hydrochloric acid.
The tAs layer 7 is etched, and the impurities and heavy metals incorporated therein are also removed at the same time.

塩酸はGaAsに対してほとんどエツチングしない性質
を有するので、アルミニウム層6及びG弘S層7のみを
溶解除去することができ、GaAsウェハへの影響は皆
無である。又、この塩酸処理中に電極形感部のn型層5
の表面には薄いGaAs酸化膜が形成され、安定な表面
保護膜として作用するので露出したn型層5表面が再び
汚染されることは全くない。更に、この酸化膜は数1o
1と極めて薄い為、後工程に影響を与えることもない。
Since hydrochloric acid has the property of hardly etching GaAs, only the aluminum layer 6 and G-S layer 7 can be dissolved and removed, and the GaAs wafer is not affected at all. Also, during this hydrochloric acid treatment, the n-type layer 5 of the electrode-shaped sensing part
A thin GaAs oxide film is formed on the surface of the n-type layer 5 and acts as a stable surface protection film, so that the exposed surface of the n-type layer 5 is never contaminated again. Furthermore, this oxide film has a thickness of several 10
Because it is extremely thin, it does not affect subsequent processes.

第2図(e)はショットキ接合全形成するため高融点遷
移金属のクンクル層8を蒸着し、さらにはンデイング・
ヤツド用として金層9をタンタル層8上に連続して蒸着
させたことを示す。第2図(f)はグラズマエッチング
技術を用い、電極部以外の金層9及びタンタル層8を工
ッチング除去し、しかるのち、1+GaAs基板4の裏
面に2ノピング、ポリッゾノグを施し、ウェハ層全10
0〜120μmの厚さで形成し、オーミ7り電極を形成
する為に、金−ダルマニウム合金10を、そのポリッシ
ング面全体に蒸着、その後400℃の炉で10分間熱処
理を行うことで、裏面オーミック電極が形成できた最終
形状を示すものである。アルミニウムは他の金属に比べ
てGaAs中の深い不純物準位密度が低く、この意味で
GaAsに対し不活性な金属として作用しており、本発
明の上からは極めて有効なものであるO 第3図は従来方法で製造したTa−GaAsショットキ
ダイオードと本発明からなるアルミニウムによる表面清
浄化を行ない、製造したTa−GaAsショットキダイ
オードの電圧電流特性の実験結果を示したものである。
FIG. 2(e) shows that in order to completely form a Schottky junction, a Kunkle layer 8 of a high melting point transition metal is deposited, and furthermore, an undying layer 8 is deposited.
It is shown that a gold layer 9 is successively deposited on the tantalum layer 8 for the purpose of coating. In FIG. 2(f), the gold layer 9 and tantalum layer 8 other than the electrode portions are removed by etching using the glazma etching technique, and then 2-nopping and polyzono-nobbing are performed on the back surface of the 1+GaAs substrate 4 to completely remove the entire wafer layer. 10
In order to form an ohmic electrode with a thickness of 0 to 120 μm, gold-darmanium alloy 10 is deposited on the entire polished surface, and then heat-treated in a 400°C furnace for 10 minutes to form an ohmic electrode. This shows the final shape of the ohmic electrode. Aluminum has a lower deep impurity level density in GaAs than other metals, and in this sense it acts as an inert metal with respect to GaAs, and is extremely effective in the present invention. The figure shows the experimental results of the voltage-current characteristics of a Ta--GaAs Schottky diode manufactured by the conventional method and a Ta--GaAs Schottky diode manufactured by surface cleaning with aluminum according to the present invention.

第3図から明らかなように本発明によりショットキ接合
の逆方向リーク電流を減少させることができる。ここで
、Aは本発明方法になるもの、Bは従来方法でのものを
示す。
As is clear from FIG. 3, the present invention can reduce the reverse leakage current of the Schottky junction. Here, A indicates the method according to the present invention, and B indicates the method according to the conventional method.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、GaAsウェハの主
表面上に電極を形成するにあたり、あらかじめGaAg
ウェハの主表面上にアルミニウムを蒸着させ熱処理し、
しかるのち、蒸着したアルミニウム層及び熱処理によっ
て形成された砒化ガリウムとアルミニウムの反応生成f
tlエツチング除去しておき、次にGaAsウェハの主
表面に所要金属を蒸着して接合電極を形成することによ
り、GaAsウェハ表面に付着している不純物や重金属
を、GaAsウェハに細管損傷を与えることなく確実に
除去することができ、清浄なG aAsウェハ表面が得
られるので、ショットキ接合の逆方向リーク電流の減少
や電極金属とGaAsウェハとの接触抵抗を接触面全面
にわたって均一に。
As described above, according to the present invention, when forming an electrode on the main surface of a GaAs wafer, GaA
Aluminum is vapor-deposited and heat-treated on the main surface of the wafer,
Thereafter, the reaction product f of gallium arsenide and aluminum formed by the vapor-deposited aluminum layer and heat treatment
By removing the tl etching and then depositing the required metal on the main surface of the GaAs wafer to form a bonding electrode, impurities and heavy metals adhering to the surface of the GaAs wafer can be removed by causing capillary damage to the GaAs wafer. Since it can be removed reliably and a clean GaAs wafer surface can be obtained, the reverse leakage current of the Schottky junction is reduced and the contact resistance between the electrode metal and the GaAs wafer is made uniform over the entire contact surface.

かつ低抵抗で形成できる。また、薄いGaAtAs層を
除去するだけで清浄なGaAgクエハ表面が得られるの
で、動作層厚の薄いG aA s半導体装置の電極を形
成する場合に極めて有効な手段を提供できる。
Moreover, it can be formed with low resistance. Furthermore, since a clean GaAg wafer surface can be obtained simply by removing the thin GaAtAs layer, it is possible to provide an extremely effective means for forming electrodes of GaAs semiconductor devices having a thin active layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体装置の製造方法υておける製造工
程を示す図、第2図は本発明の一実施例における製造工
程を示す図、第3図は本発明に係るノー17)キダイオ
ードの′戊王−電流特性の一例を従来と比較して示す特
性図である、。 I・・・n+GaAs基板、2・・・2酸化シリコノ膜
、3・・・電極金属、5・・・工ぎクキシャルn型層、
6・・・アルミニウム層、7・・・GaAtAs 層、
8・・・タフタル層、9・・・金層。 出願人代理人 弁理士 鈴 江 武 産米1図 (a) (b)
FIG. 1 is a diagram showing a manufacturing process in a conventional semiconductor device manufacturing method υ, FIG. 2 is a diagram showing a manufacturing process in an embodiment of the present invention, and FIG. 3 is a diagram showing a manufacturing process in an embodiment of the present invention. FIG. 2 is a characteristic diagram showing an example of the current characteristics of the 'Booh-current characteristic in comparison with the conventional one. I... n+GaAs substrate, 2... silicon dioxide film, 3... electrode metal, 5... engineered axial n-type layer,
6... Aluminum layer, 7... GaAtAs layer,
8... Taftal layer, 9... Gold layer. Applicant's representative Patent attorney Takeshi Suzue Rice production Figure 1 (a) (b)

Claims (1)

【特許請求の範囲】[Claims] 砒化ガリウムウェハの主表面上にあらかじめアルミニウ
ムを蒸着、熱処理し、しかる後蒸着したアルミニウム層
及び熱処理によって形成された砒化ガリウムとアルミニ
ウムの反応生成層をエツチング除去し、次にこの砒化ガ
リウムウェハの主表面上に所要金属を蒸着して接合電極
を形成することを特徴とする半導体装置の製造方法。
Aluminum is vapor-deposited and heat-treated on the main surface of the gallium arsenide wafer in advance, and then the vapor-deposited aluminum layer and the reaction product layer of gallium arsenide and aluminum formed by the heat treatment are removed by etching. 1. A method of manufacturing a semiconductor device, comprising forming a bonding electrode by vapor-depositing a required metal thereon.
JP11217283A 1983-06-22 1983-06-22 Manufacture of semiconductor device Pending JPS604214A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11217283A JPS604214A (en) 1983-06-22 1983-06-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11217283A JPS604214A (en) 1983-06-22 1983-06-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS604214A true JPS604214A (en) 1985-01-10

Family

ID=14580046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11217283A Pending JPS604214A (en) 1983-06-22 1983-06-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS604214A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997020342A1 (en) * 1995-11-29 1997-06-05 Simage Oy Forming contacts on semiconductor substrates for radiation detectors and imaging devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997020342A1 (en) * 1995-11-29 1997-06-05 Simage Oy Forming contacts on semiconductor substrates for radiation detectors and imaging devices
AU713954B2 (en) * 1995-11-29 1999-12-16 Simage Oy Forming contacts on semiconductor substrates for radiation detectors and imaging devices
US6046068A (en) * 1995-11-29 2000-04-04 Simage Oy Forming contacts on semiconductor substrates radiation detectors and imaging devices

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