JPS6394673A - Manufacture of schottky barrier semiconductor device - Google Patents
Manufacture of schottky barrier semiconductor deviceInfo
- Publication number
- JPS6394673A JPS6394673A JP24059186A JP24059186A JPS6394673A JP S6394673 A JPS6394673 A JP S6394673A JP 24059186 A JP24059186 A JP 24059186A JP 24059186 A JP24059186 A JP 24059186A JP S6394673 A JPS6394673 A JP S6394673A
- Authority
- JP
- Japan
- Prior art keywords
- thin layer
- layer
- metal layer
- schottky barrier
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004888 barrier function Effects 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 17
- 239000010936 titanium Substances 0.000 claims abstract description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000007738 vacuum evaporation Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910000927 Ge alloy Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 206010057040 Temperature intolerance Diseases 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 235000013601 eggs Nutrition 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000008543 heat sensitivity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高耐圧が得られるショットキバリア半導体装
置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a Schottky barrier semiconductor device that can obtain a high breakdown voltage.
ショットキバリア半導体装置は、その旨速かつ低損失で
ある利漬Ｚ生かして、高周波繁流回ｗＩＪに広（オリ用
されている。しかし、ショットキバリア半導体装置はｐ
ｎ接合素子に比べて高耐圧が得難いのが実状で、耐圧に
関して答に改良の余地がある。Schottky barrier semiconductor devices are widely used in high-frequency heavy-flow circuits, taking advantage of their high speed and low loss dielectric Z. However, Schottky barrier semiconductor devices are
The reality is that it is difficult to obtain a high breakdown voltage compared to an n-junction element, and there is room for improvement in terms of breakdown voltage.
ショットキバリア半導体装置の高耐圧化ケはかる之めに
、第３図に示すフィールドプレートを設けｔ構造、第４
図に示すガードリングを設けた構造、あるいはこれらを
組合わせ之構造が多用されている。In order to increase the breakdown voltage of the Schottky barrier semiconductor device, a field plate shown in FIG.
A structure provided with a guard ring as shown in the figure, or a structure in which these are combined are often used.
第３図のフィールドプレート構造においては、電極（２
）のうち絶縁膜（３）の上に延在する部分（２ａ）が、
フィールドプレートと呼ばれ、その下のｎ形半導体領域
［１１０表面近傍における電界集中を緩和する。In the field plate structure shown in Fig. 3, the electrode (2
), the portion (2a) extending over the insulating film (3) is
It is called a field plate and relieves electric field concentration near the surface of the n-type semiconductor region [110] below.
ところで、フィールドプレートによる高耐圧化では、絶
縁Ｍ（３）の開孔端（３ａ）の傾斜角度が耐圧に微妙な
影響を与える。このｔめ、ｊ＆適な軸斜角度？得るため
に、多重絶鰍膜を用Ｉ／′１ｔす、厳密なエツチング制
８１を行うなど、大きな効果を得ようとすれば製造プロ
セスか複雑化する。By the way, when increasing the withstand voltage using a field plate, the inclination angle of the opening end (3a) of the insulation M (3) has a subtle effect on the withstand voltage. This t, j & suitable axis inclination angle? In order to obtain a large effect, the manufacturing process becomes complicated, such as by using multiple insulating membranes or carrying out a strict etching process81.
第４図のガードリング構造においては、＊極（４）と半
導体領域（１）の間に形成されるショットキバリアを包
囲するｐ形振状領域（５）と、この環状領域（５）＋
を更に包囲するｐ刑場状領域（６）とが形成されている
。（７１は絶縁膜である。環状領域＋５１１６１はガー
ドリングあるいはフィールドリミッティングリングと呼
ばれ１表面近傍における電界集中を緩和する。In the guard ring structure shown in FIG. Furthermore, a surrounding p-punishment area (6) is formed. (71 is an insulating film. The annular region +51161 is called a guard ring or a field limiting ring and relieves electric field concentration near one surface.
ところで、ガードリングによる高耐圧化では、環状領域
＋５１１６１の寸法及び位看が耐圧に大きく影響するの
で、厳密な設計及び高精度なフォトエツチング技術が要
求はれる。このｔめ、環状領域ｆ５１ （６＋り形成す
るための拡散工程が加わることで製造プロセスが長び（
こととも合わゼて、製造プロセスが複雑化する。By the way, when increasing the withstand voltage by using a guard ring, the dimensions and position of the annular region +51161 greatly affect the withstand voltage, so strict design and highly accurate photo-etching technology are required. The manufacturing process becomes longer due to the addition of a diffusion step to form the annular region f51 (6+).
Combined with this, the manufacturing process becomes more complex.
そこで本発明の目的し１．比較的藺単な製造プロセスで
、かつ礒実に高耐圧が得られるショットキバリア半導体
装置の製造方法を提倶することにある。Therefore, the purpose of the present invention is to: 1. It is an object of the present invention to provide a method for manufacturing a Schottky barrier semiconductor device that uses a relatively simple manufacturing process and can provide a fairly high breakdown voltage.
上記問題点を解決し、上記目的を達成するｔめの本発明
は、ショットキバリア？得るためのノ（す丁金属層を半
導体領域上に形成し、かつ前記）（す了金属層Ｚはぼ隣
接して包囲するようにチタンを主成分とする薄層を前記
半導体領域上に形成した俊に、酸化雰囲気中で熱処理ケ
施し、前記ナタン乞主成分とする薄層に熱感ｕ１？施し
た薄層を少なくとも前記バリア金属層の周辺に最終的に
残存させることを特徴とするショットキバリア半導体装
置の製造方法に係わるものである。The third aspect of the present invention that solves the above problems and achieves the above objects is a Schottky barrier. In order to obtain a metal layer Z, a thin layer mainly composed of titanium is formed on the semiconductor region so as to surround the metal layer Z. A schottky characterized in that the thin layer containing the nathanum main component is heat-treated in an oxidizing atmosphere, and a thin layer obtained by applying heat sensitivity to the thin layer containing the nathanum main component ultimately remains at least around the barrier metal layer. The present invention relates to a method for manufacturing a barrier semiconductor device.
チタンを主成分とする薄層に熱処理を施すことによって
形成される薄層は、ショットキバ１１″７に逆バイアス
が印刀口されたとき、半導体領域の表面領域における電
界集中を緩和するように作用する。The thin layer formed by heat-treating the thin layer mainly composed of titanium acts to alleviate the electric field concentration in the surface area of the semiconductor region when a reverse bias is applied to the Schottky bar 11''7. do.
〔第１の実施例〕
次に、本発明の第１の実施例に係わるショットキバＩ＋
７半導体装箭及びその製造方法を説明する。[First Example] Next, Schottkyba I+ according to the first example of the present invention
7. A semiconductor device and its manufacturing method will be explained.
第１図はショットキバリア半導体装置（ショットキ・ダ
イオード）を製造工程順に１素子分について示す。この
ショットキバリア半導体装置を製造する際には、まず、
第１図囚に示す、ＧａＡｓ （ヒ化ガリウム）から成る
半導体基板ｏＩＩを用意する。FIG. 1 shows one element of a Schottky barrier semiconductor device (Schottky diode) in the order of manufacturing steps. When manufacturing this Schottky barrier semiconductor device, first,
A semiconductor substrate oII made of GaAs (gallium arsenide) as shown in FIG. 1 is prepared.
この半導体領域上１は、比較的厚いｎ刑基板領域［１２
＋の上に比較的薄いｎ′″形領域Ｕをエピタキシャル成
長ざ上次ものである。ｎ−影領域０３＋の不純物一度は
２Ｘ１０ｃｍ ％厚さは２０μｍである。Above this semiconductor region 1 is a relatively thick substrate region [12
A relatively thin n''' type region U is epitaxially grown on top of the n-shaded region 03+.
次に、第１図ＣＢ）に示す如（、ｎ−影領域（＋３）の
上に全面的にりｌ（チタン）の薄層（１４）を真空蒸着
で形成し、史にその上に全面的［Ａｌ（アルミニウム）
Ｎ４卵を真空蒸着で形成する。Ｔ１の薄層ｈａは約５０
′Ａと極めて薄く形成し、Ａ１層α９は約１μｍの厚ジ
に＋
形成する。更に、ｎ 影領域（１２の表面Ｃ下面）［Ａ
ｕ （金） −（ｊｅ （ゲルマニウム合金）から成る
オーミック接触の電今αｅを真空蒸着により形成する。Next, as shown in Figure 1CB), a thin layer (14) of titanium (titanium) is formed entirely on the n-shaded area (+3) by vacuum evaporation. target [Al (aluminum)
N4 eggs are formed by vacuum evaporation. Thin layer ha of T1 is approximately 50
The A1 layer α9 is formed to have a thickness of approximately 1 μm. Furthermore, n shadow area (lower surface of surface C of 12) [A
An ohmic contact electrode αe made of u (gold)-(je (germanium alloy) is formed by vacuum evaporation.
次［、第１図（Ｃ）に示ＴｔｌＯ（，７オトエツチング
によ、９ＡＩ層西の一部をエツチング除去し、ショット
キバリアを形成すべき領域に対応させてバリア金属層と
してのＡ１層（１５ａ）を残存ざセる。史に、フォトエ
ツチングにより素子の周辺領域（多数の素子か形成され
た大面項生導体基板から各素子に分割するときの切断ラ
イン近傍）から薄層（１４）を除去り、Ａ１層（１５ａ
）の下部にある薄＃（１４ａ）とこれを包囲する薄層
（１４ｈ）を残存はせる。Next, as shown in FIG. 1(C), a part of the west side of the 9AI layer was etched away by etching, and the A1 layer as a barrier metal layer ( 15a) remains.In history, a thin layer (14) is removed from the peripheral area of the device (near the cutting line when dividing a large-area raw conductor substrate on which many devices are formed into individual devices) by photoetching. was removed, and the A1 layer (15a
) and the thin layer (14h) surrounding it remain.
次に、第１図（Ｑに示すものに、５７Ｇの０２ガスと９
５％のＮ２ガスから成る酸化性雰囲気中で、３８０℃、
３０秒の熱処理を施す。この熱処理の結果。Next, add 57G of 02 gas and 9
380°C in an oxidizing atmosphere consisting of 5% N2 gas,
Heat treatment is performed for 30 seconds. The result of this heat treatment.
ＡＩ Ｒ（１５ａ）は、その下の薄層（１４ａ）を介し
てｎ−影領域０３）に対してショットキバリアを形成す
る。The AI R (15a) forms a Schottky barrier to the n-shadow region 03) via the underlying thin layer (14a).
このショットキバリアはＡ１とＧａＡｓのショットキバ
リアと同等の特性を有する。薄層（１４ａ）がどのよう
な形で残存しているかは足かで番まない。従って、第１
図０では、 Ａ１層（１５ａ ）と＊層（１４ａ）を合
わせたものをバリア金属層ａη即ちタイオードの一方の
′を極として図示されている。第１図（０ＯＮ層（１４
ｈ ）は、酸化されて第１図［Ｆ］のチタン酸化物を含
む薄層０８１となる。この薄層０８１は、チタン酸化物
層であっても、全領域が安定なチタン酸化物かつ絶縁物
とみｔｊせるＴｉＱ２ （２酸化チタン）ではないと推
定ばれる。すなわち、薄層（１８１のうちｎ−影領域０
３）に隣接するイｌ１ＩＩは、 Ｔｉが十分に酸化され
ておらず。This Schottky barrier has properties similar to those of A1 and GaAs. The shape of the thin layer (14a) remaining does not depend on the size of the foot. Therefore, the first
In FIG. 0, the combination of the A1 layer (15a) and the * layer (14a) is illustrated with the barrier metal layer aη, that is, one ' of the diode, as the pole. Figure 1 (0ON layer (14
h) is oxidized to become a thin layer 081 containing titanium oxide as shown in FIG. 1 [F]. Although this thin layer 081 is a titanium oxide layer, it is presumed that the entire region is not TiQ2 (titanium dioxide), which can be considered to be a stable titanium oxide and insulator. That is, thin layer (n of 181 - shadow area 0
In I1II adjacent to 3), Ti is not sufficiently oxidized.
Ｔ１リッチな（化学８ｍ的にＴｉＱ、と比べてＴＩの組
成比が大きい状態を言う）チタン酸化物となっており、
微かに導電性か認められる高抵抗領域になっているもの
と推定される。まｔ、薄層０８１の表面側（上部）はチ
タン酸化物で、薄層（１８１のｎ−影領域０に隣接する
極く薄い領域は尚抵抗層として働くチタン金属領域と１
−で残存しているとも推定はれる。穴だし、これら２つ
の推定構造も、厳密に区別できるものではない。It is a titanium oxide that is T1-rich (in chemical terms, the composition ratio of TI is larger than that of TiQ).
It is presumed to be in a high resistance region with slight conductivity. The surface side (upper part) of the thin layer 081 is made of titanium oxide, and the extremely thin area adjacent to the n-shaded area 0 of the thin layer 081 is a titanium metal area that acts as a resistive layer.
It is also estimated that it remains in -. Unfortunately, these two estimated structures cannot be strictly distinguished.
次に、第１図■に示す如く、′Ｒ層（１８１のトを保婦
膜ａ９で被借して、ショットキバリア半導体装置を完成
はせる。保護膜ａ９は、ＣＶＤ法により形成し念Ｓ Ｉ
Ｏｔ膜Ｃシリコン岬化膜）または８ ｒ ３Ｎ ４模（
シリコン窒化膜）、あるいは塗布法により形成しｔポリ
イミド樹脂膓などとする。Next, as shown in FIG. I
Ot film C silicon cape film) or 8 r 3N 4 model (
A silicon nitride film) or a polyimide resin film formed by a coating method is used.
こうして製作したショットキバリア半導体装置（ショッ
トキ・り゛イオード）は、２５０ｖの耐圧（降伏電圧）
を示した。これは、上記ｎ−形領領域０；引不純物濃度
におけるバルク耐圧（１１％（ＩＦｉｌの中央領域の耐
圧）にほぼ等しい。２５０ｖ印加時のｎ−影領域０３の
表面を走査型電子顕微鏡で観察したところ、最大電界の
生じている位置が電極Ｏｅの端部から３５μｍ程度離れ
た位＃にあった。また、薄層０８１を除去すると、最大
電界の位置は！Ｔｈ（１６１の端部付近にあり、耐圧は
約１００ＶＶｃ低下した。これらのことから、薄層ｆ１
８１が表面領域での電界集中を緩和する効果を強く発揮
していることがわかるー〔第２の実施例〕
次に、第２図を参照して第２の実施例に係わるショット
キバリア半導体ｉｔ及びその製造方法を説明する。The Schottky barrier semiconductor device (Schottky diode) manufactured in this way has a withstand voltage (breakdown voltage) of 250V.
showed that. This is approximately equal to the bulk breakdown voltage (11% (withstand voltage of the central region of IFil) at the n-type region 0; draw impurity concentration).The surface of the n-shade region 03 when 250V is applied is observed with a scanning electron microscope. As a result, the position of the maximum electric field was found to be approximately 35 μm away from the end of the electrode Oe. Furthermore, when the thin layer 081 was removed, the position of the maximum electric field was !Th(near the end of the electrode Oe). Yes, the withstand voltage decreased by about 100VVc.From these reasons, the thin layer f1
It can be seen that the Schottky barrier semiconductor IT according to the second example, with reference to FIG. and its manufacturing method will be explained.
まず、第２図囚に示す（ｊａＡ ｓ基板αＤを用意する
。First, a substrate αD shown in FIG. 2 is prepared.
この基板旧ｉは第１図囚のものと同一なものである。This board old i is the same as the one shown in Figure 1.
次に、ｎ−影領域（１３）の上に全面的に’ｈの薄層を
Ｘ空Ｍ着した後、フォトエツチングによりショットキバ
リアを形成すべき中央部及び素子の周辺領域からＴｉの
４）−を除去し、第２図の）に示す厚さ約５０ＸのＴｉ
Ｏ薄層■を形成する。Next, after depositing a thin layer of 'h' on the entire surface of the n-shaded area (13), a layer of Ti (4) is applied from the central area where a Schottky barrier is to be formed and the peripheral area of the device by photo-etching. - is removed, and a Ti layer with a thickness of about 50X as shown in Figure 2) is removed.
Form a thin layer of O.
次に、ＡＩを全面的に真空蒸着し、フォトエツチングに
よりショットキバリアを形成すべき中央部のみに摩さ約
１μｍのＡ１層ＣＩ！１１を残存させる。なお、Ａ１の
全面蒸着後のフォトエツチング前に、ｎ 影領域α３の
表面にＡｕ −Ｇｅ合金から成るｔ極（１ｂ）を形成す
る。Next, AI was vacuum-deposited on the entire surface, and by photoetching, a layer of AI of about 1 μm was polished only in the central part where a Schottky barrier was to be formed. 11 will remain. Note that before photoetching after the entire surface vapor deposition of A1, a t-pole (1b) made of an Au--Ge alloy is formed on the surface of the n-shaded region α3.
次に、第１の実施例と同じ熱処理を酸化雰囲気中で行う
。第２図（０でＡｉ層Ｃ？１１のうち薄Ｉ′！１１ｃ１
ｇの上に延性していた周辺部分も、第１の実施例で述べ
たように、ショットキ式１１丁を形成する。そこで、熱
処理後を示す第２図０では、第２図（０のＡｌ７ＩＣＩ
！υとこれに被復；れてい之薄層のの一部を合わせてバ
リア金属層のと図示されている。薄層−身の残りの部分
は酸化づれて第２図■に示す薄Ｉ＠器となる。Next, the same heat treatment as in the first example is performed in an oxidizing atmosphere. Figure 2 (thin I'!11c1 of Ai layer C?11 at 0
The peripheral portion, which was ductile above g, also forms a Schottky 11-gun, as described in the first embodiment. Therefore, in Fig. 2 0 showing the state after heat treatment, the Al7ICI of Fig. 2 (0)
! υ and a portion of this thin layer are shown as a barrier metal layer. The remaining part of the thin layer is oxidized and becomes the thin layer shown in Figure 2 (■).
この薄層のは第１図０で示すＮ ＃ １８１と同じもの
である。This thin layer is the same as N # 181 shown in FIG.
次に、第２図［Ｆ］に示す如く、第１の実施例と同様に
保護膜α９を老成してショットキバリア半導体装置を完
成づせる。Next, as shown in FIG. 2F, the protective film α9 is grown to complete the Schottky barrier semiconductor device in the same manner as in the first embodiment.
この第２の実施例の構造のショットキバリア米導体装置
の耐圧は、第１図に示すショットキツクリア半導体装置
のそれとほぼｌｌｆｆｌ−であつｔｏ〔変Ｉヒ例〕
本発明は、上述の実施例に限定ばれるものでなく、神々
臂形可卵ｔｆものである。倒えば、チタンの薄層（１４
）（イ）は、Ｉｎ ｆ ８ｎを性別したＴ１層などＴｉ
を主成分とするものでもよい。テ之ｎ−形領域（１３）
は、Ｕａｋｓ ＶＣ限ることなく、ＩｎＰ（燐化インジ
ウム）等のｍ−ｖ族化合物半導体、又は更に別の半導体
であってもよい□。ＴＩの薄層α４）■の厚さと熱処理
の条件も檜々選釈できる。薄層（１４）■の厚ばは２０
〜３００Ａ、更に望！しくは３０〜２００Ａか好適範囲
である。２０Ａと言えば数原子層の厚はで、これ以上薄
くすると、均一な薄層を形成することも難しくなってく
るし、熱処理条件の設定も難しくなり、結果と【て安定
して高耐圧を得るのが難しくなる。３００Ａを越えると
、最適な熱処理条件が高温及び長時間化して生産性か低
下する。熱処理温度は、２００〜５００℃、更に望１し
くは３００〜４００℃か好適範囲である。２００℃未満
では熱処理が長時間化するし、５００℃を越テると熱処
理が短時間になり過き°たり、バリア金属や半導体領域
に悪影響を与える恐れも出て（る。The breakdown voltage of the Schottky barrier semiconductor device having the structure of the second embodiment is approximately lffl- that of the Schottky barrier semiconductor device shown in FIG. It is not limited to, but it is a God-shaped TF. If you fall over, a thin layer of titanium (14
) (b) is a Ti layer such as a T1 layer which is a gender of In
It may be one whose main component is Ten-n-type area (13)
is not limited to Uaks VC, and may be an m-v group compound semiconductor such as InP (indium phosphide) or another semiconductor. The thickness of the TI thin layer α4) and the heat treatment conditions can also be selected accordingly. The thickness of the thin layer (14)■ is 20
~300A, even more desired! The preferred range is 30 to 200 A. Speaking of 20A, it is only a few atomic layers thick, and if it is made thinner than this, it becomes difficult to form a uniform thin layer, and it becomes difficult to set the heat treatment conditions, resulting in a stable high breakdown voltage. becomes difficult. When it exceeds 300 A, the optimum heat treatment conditions become high temperature and long, resulting in a decrease in productivity. The heat treatment temperature is preferably in the range of 200 to 500°C, more preferably 300 to 400°C. If it is less than 200°C, the heat treatment will take a long time, and if it exceeds 500°C, the heat treatment will be too short and may have an adverse effect on the barrier metal or semiconductor region.
熱処理時間は、生産性と制御性を考えると、薄層０４）
■の厚こと熱処理温度等を訓整して、５秒〜２時間の範
囲に収めるのか望！しい。Considering productivity and controllability, the heat treatment time is determined by thin layer 04)
I hope to be able to adjust the thickness, heat treatment temperature, etc. in ■ to keep it within the range of 5 seconds to 2 hours! Yes.
上述から明らかな如く、本発明によれば、比較的単純な
工程でショットキバリア半導体装置の耐圧を大＠に向上
ζせることができる。As is clear from the above, according to the present invention, the withstand voltage of a Schottky barrier semiconductor device can be greatly improved by a relatively simple process.
第１図（４）〜［Ｆ］は本発明の第１の実施例に係わる
ショットキバリア半導体装置を工程順に示す断面図。
第２図囚〜■は本発明の第２の実施例に係わるショット
キバリア半導体ｅｆｆｔを工程ＩＩＩＩＫ示す断面図。
第３図及び第４図は従来のショットキバリア半導体装置
を示す断面図である。
ロト・・半導体基板、ａ３・・・ｎ−影領域、０４・・
・１゛ｌ薄層、ａ９・・・Ａ１層、 （１７１・・・バ
リア金属層、０８１・・・Ｔｉ酸化物を含む薄層。
代 理 人 筒 野 則 次第１崗
第２図FIGS. 1(4) to 1(F) are cross-sectional views showing the Schottky barrier semiconductor device according to the first embodiment of the present invention in the order of steps. FIGS. 2A to 2C are cross-sectional views showing the Schottky barrier semiconductor effect according to the second embodiment of the present invention in step IIIK. 3 and 4 are cross-sectional views showing a conventional Schottky barrier semiconductor device. Roto...semiconductor substrate, a3...n-shadow area, 04...
・1゛l thin layer, a9...A1 layer, (171...barrier metal layer, 081...thin layer containing Ti oxide. Agent Nori Tsutsuno Figure 2)
Claims (4)
導体領域上に形成し、かつ前記バリア金属層をほぼ隣接
して包囲するようにチタンを主成分とする薄層を前記半
導体領域上に形成した後に、酸化雰囲気中で熱処理を施
し、前記チタンを主成分とする薄層に熱処理を施した薄
層を少なくとも前記バリア金属層の周辺に最終的に残存
させることを特徴とするショットキバリア半導体装置の
製造方法。(1) A barrier metal layer for obtaining a Schottky barrier was formed on the semiconductor region, and a thin layer mainly composed of titanium was formed on the semiconductor region so as to substantially adjacently surround the barrier metal layer. A Schottky barrier semiconductor device characterized in that the thin layer containing titanium as a main component is then heat-treated in an oxidizing atmosphere so that the thin layer that has been heat-treated remains at least around the barrier metal layer. Production method.
分とする薄層とこの薄層上に形成された金属層とから成
るものであり、前記熱処理前の前記バリア金属層を包囲
する前記チタンを主成分とする薄層は、前記バリア金属
層のチタンを主成分とする薄層に連続し且つ同時に形成
されたものである特許請求の範囲第１項記載のショット
キバリア半導体装置の製造方法。(2) The barrier metal layer before the heat treatment is composed of a thin layer containing titanium as a main component and a metal layer formed on this thin layer, and the barrier metal layer surrounding the barrier metal layer before the heat treatment is The method for manufacturing a Schottky barrier semiconductor device according to claim 1, wherein the thin layer mainly composed of titanium is formed continuously and simultaneously with the thin layer mainly composed of titanium of the barrier metal layer. .
特許請求の範囲第１項又は第２項記載のショットキバリ
ア半導体装置の製造方法。(3) The method for manufacturing a Schottky barrier semiconductor device according to claim 1 or 2, wherein the semiconductor region is a III-V group compound semiconductor.
金属層であり、前記III−Ｖ族化合物半導体は砒化ガリ
ウムである特許請求の範囲第１項記載のショットキバリ
ア半導体装置の製造方法。(4) The method for manufacturing a Schottky barrier semiconductor device according to claim 1, wherein the barrier metal layer is a metal layer containing aluminum as a main component, and the III-V group compound semiconductor is gallium arsenide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24059186A JPS6394673A (en) | 1986-10-09 | 1986-10-09 | Manufacture of schottky barrier semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24059186A JPS6394673A (en) | 1986-10-09 | 1986-10-09 | Manufacture of schottky barrier semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6394673A true JPS6394673A (en) | 1988-04-25 |
| JPH0515311B2 JPH0515311B2 (en) | 1993-03-01 |
Family
ID=17061783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24059186A Granted JPS6394673A (en) | 1986-10-09 | 1986-10-09 | Manufacture of schottky barrier semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6394673A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5221638A (en) * | 1991-09-10 | 1993-06-22 | Sanken Electric Co., Ltd. | Method of manufacturing a Schottky barrier semiconductor device |
| EP0579286A2 (en) * | 1988-11-11 | 1994-01-19 | Sanken Electric Co., Ltd. | Method of fabricating a semiconductor device with Schottky barrier |
| JP2002334998A (en) * | 2001-05-08 | 2002-11-22 | Mitsubishi Electric Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| JP2006287264A (en) * | 2006-07-24 | 2006-10-19 | Nissan Motor Co Ltd | Silicon-carbide semiconductor device |
| JP2007227495A (en) * | 2006-02-22 | 2007-09-06 | Mitsubishi Electric Corp | Fabrication process of sic semiconductor device, and sic semiconductor device |
-
1986
- 1986-10-09 JP JP24059186A patent/JPS6394673A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0579286A2 (en) * | 1988-11-11 | 1994-01-19 | Sanken Electric Co., Ltd. | Method of fabricating a semiconductor device with Schottky barrier |
| EP0579286A3 (en) * | 1988-11-11 | 1994-09-07 | Sanken Electric Co Ltd | Method of fabricating a semiconductor device with schottky barrier |
| US5221638A (en) * | 1991-09-10 | 1993-06-22 | Sanken Electric Co., Ltd. | Method of manufacturing a Schottky barrier semiconductor device |
| JP2002334998A (en) * | 2001-05-08 | 2002-11-22 | Mitsubishi Electric Corp | Silicon carbide semiconductor device and manufacturing method therefor |
| JP2007227495A (en) * | 2006-02-22 | 2007-09-06 | Mitsubishi Electric Corp | Fabrication process of sic semiconductor device, and sic semiconductor device |
| JP2006287264A (en) * | 2006-07-24 | 2006-10-19 | Nissan Motor Co Ltd | Silicon-carbide semiconductor device |
| JP4586775B2 (en) * | 2006-07-24 | 2010-11-24 | 日産自動車株式会社 | Silicon carbide semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0515311B2 (en) | 1993-03-01 |
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