JPS59126651A - Program circuit device in redundancy circuit - Google Patents

Abstract

PURPOSE:To enable circuit design with a single power source without the necessity of impressing a high voltage by utilizing the latch-up phenomenon of a complementary field effect transistor. CONSTITUTION:In order to fuse a fuse 19, first when an address is selected by setting the output of a control circuit 13 at an ''H'' level, the output of an address decoder 12 turns at an ''L'' level. Therefore, a p-MOSFET 17 comes to an ON-state. Next, when a negative surge voltage is impressed on an input terminal 16, an n-p-n transistor 32 comes to an ON-state, and a current flows, in the direction from an output terminal 22 to the input terminal 16, through the base resistor 31 of a p-n-p transistor 30, thus leading the transistor 30 to an ON- state. Accordingly, the current flows from the output terminal 22 to a ground point 21 through the base resistor 34 of an n-p-n transistor 33, resulting in the ON-state of the n-p-n transistor 33; so-called a latch-up phenomenon occurs. Consequently, the fuse 19 fuses by the flow of this high current to said fuse, the output terminal 22 turns at the ''L'' level, and then becomes a mode whereby a redundant memory is driven.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a program circuit that blows out a fuse in a redundant circuit portion of a semiconductor memory device having a redundant portion in order to activate the portion.

[Prior art]

A conventional device of this type is shown in FIG. FIG. 1 shows an example of a program circuit in a redundant circuit,
In the figure, (1) is an n-channel type derangement field effect transistor (hereinafter referred to as n-DMO8).

). (2) is a terminal to which a high voltage V is applied, and is connected to the drain of the n-DMO8 (1). (3) is an n-channel field effect transistor (hereinafter referred to as nMO8), and (4) is an nM
This is an input terminal for applying a signal to the gate of O8(3). (5) is connected to the source of nMO8 (3) at a low potential point and is normally grounded. (6) is the output line, n −
connected to the source and gate of DMOS (1);
It is also connected to the drain of nMO8(3). (7
) nMO8, the output #(6) is connected to the gate of nMO8(7), and the source of nMO8(7) is grounded. The fuse (8) is made of polycrystalline silicon and is blown by flowing a high current. (9)
It is a high potential point (voo) and is connected to one end of the fuse (3). The other end of the fuse (8) is connected to the drain of nMO8 (7), and OI is the output terminal (F), n
MO8 (connected to the drain of 7J and is the output terminal of this program circuit). Also, (11) is n-DMO8, the source and gate of n-DMO8 (1) are grounded, and the drain is connected to the output terminal QQ. It is connected.

Explain the operation arbitrarily. The input terminal (4) is normally a tube (
+all) level, and when in this state, nMO
8 (3) is in the ON state and the output line (6) is at ground level. Therefore, nMO8 (7) is in the OFF state,
The output terminal of the program circuit is at the level q1)l'1l-H11, and the redundant memory is not activated at this time. Next, when a low (IILII) L/bevel signal is applied to the input terminal (4), nM O5 (3) turns OFF, the output line (6) becomes a high potential, and a high current flows to nM OBC7). flows. Therefore, the fuse (8) is blown and the output of the program circuit becomes the IIL11 level, thereby entering the mode in which the redundant memory is driven.

Since the conventional device is constructed as described above, a high current is required to blow the fuse, and therefore a high voltage must be applied, and a high voltage circuit is required for this purpose. There was a drawback.

[Summary of the invention]

This invention was developed in order to eliminate the drawbacks of the conventional ones as described above, and by utilizing the latch amplifier phenomenon of complementary field effect transistors, it can be used in redundant circuits that do not require high voltage and high-mounted circuits. A program circuit device is provided.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, (12 is an address decoder, 04 is a program control circuit, circle is a two-man AND gate,
The output of the address decoder θ and the output of the program control circuit are input.

(I5) is a program enable circuit, and its end is an input terminal, which is connected to the input of the program enable circuit 05). Oη is a p-channel field effect transistor (hereinafter referred to as pMO8), and Oη is a high potential point (■C
C) connected to the source of pMO8Qη, and p
The output of the AND gate (14) is connected to the gate of MO8Qη. (I9) is a fuse made of polycrystalline silicon, and the fuse is n-DMO8. Q]) is a low potential point (ground) to which the gate and source of the n-DMO8 are connected. @ is the output terminal of this program circuit. One end of fuse 4 is connected to the drain of pM OSQ, and the other end of fuse α9 is connected to n-
The drain of the DMO8 (20) and the output terminal of the program enable circuit 05) are connected, and also connected to the output terminal.

Figure 3 shows the program enable circuit (
I6) is a cross-sectional view showing the detailed configuration of I6). In the figure, @
rI'in-type semiconductor substrate, ■ is the first p-shade region formed on a part of the surface of the substrate, and object is the second p-shade formed on the other part of the surface of the substrate. Area, (e) is the board ■
A first n-shaded region is formed on the surface of the substrate (2) and has a higher impurity concentration than the substrate (2), and @ is formed on the surface of the first p-shaded region and has a higher impurity concentration than the substrate A third p shadow region (E) having a higher impurity concentration than the substrate (4) and a second and third n The second p-shaded region (to) and the first n-shaded region (to) are connected to the output terminal. Figure 4 explains the operation of the program enable circuit shown in Figure 3. In FIG. 4, which is a cross-sectional view including the bipolar transistor hidden inside, (1) shows the second p-type impurity region as the emitter, the substrate (2) as the base, and the first region as the emitter. (c) is a pnp transistor whose collector is the p-type impurity region cI19, and cll) is the pace resistance of this pnp-type transistor q. This is a first npn type transistor in which the first p-type impurity region (material) is used as a pace and the substrate layer is used as a collector.Similarly, (to) is a second n-type impurity region (c).
This is a second npn type transistor having an emitter, a first p type impurity region (c) as a base, and a substrate as a collector. (b) is the base resistance of this npn type transistor (g).

Next, the operation of the embodiment of this invention will be explained. First, a normal state in which redundant memory is not used will be described. In Fig. 2, the output of the program control circuit is 1 except when programming, that is, when fuse tt@ is blown.
It is at IL11 level, and the output of the address decoder is -11L level when an address is selected.
The logic configuration is such that the level is IIHII when not selected. Therefore, under normal conditions, AND game) (14)
The output of is II L I+ level, pMO8Q7)
is in the ON state, so the output terminal (a) of the program circuit is at the IIH11 level.

Next, a method for blowing out the fuse 99) will be explained. First, the output of the program control circuit j3) is
When the address is set to the level and an address is selected, the output of the address decoder H becomes the IILI+ level. Therefore pMo S
Oη becomes ON state. Next, in this state, when a negative surge voltage is applied to the input terminal (0) in Figure 4, when a negative surge voltage is applied to the input terminal (4), the output terminal (4), that is, the npn type transistor )'s collector is V. . Since the foot is on the level and the pace is grounded,
When the npn transistor (2) is in the ON state, current flows from the output terminal (2) through the input terminal (in the direction of I@, the base resistor C31 of the pnp transistor (7)), and the current flows inside the pnp transistor. becomes ON state. Therefore,
A current flows from the output terminal - to the ground point Qυ through the base resistor (to) of the npn transistor (to), and the npn transistor (to) turns on, and the 'PnP transistor q and npn transistor are turned on. A so-called ratte-up phenomenon occurs in which a high current flows from the output terminal to the ground point <29. Therefore, this high current flows to fuse 9), fuse 4 melts, and the output terminal @
The level becomes 1ltIIL11, and the mode becomes such that the redundant memory can be driven.

Furthermore, if the address is not selected even if the output of the program control circuit is set to IIHI+ level, that is, if the output of address decoder fl is at IIH11 level, pMo8(
+7) is OFF. Therefore, the fuse 09) will not blow out. In the above embodiment, a structure in which a negative surge voltage is applied to the input terminal (power terminal) has been described, but it is also possible to operate with a positive surge voltage. This is a circuit diagram showing another example of a program-enabled circuit used in that case.
In the example of FIG. 5, the first p shadow region (
In place of the third n-shaded area provided on the surface of (c), a fourth p-shaded area μs is provided on the surface of the n-type substrate (a) independently of the first p-shaded area (material). This is the input terminal (16)
The circuit of FIG. 3 operates similarly to the circuit of FIG. 3 with a positive cage voltage applied to the input terminal (+6) as described above.

〔Effect of the invention〕

As explained above, in this invention, the latch amplifier phenomenon of complementary field effect transistors is used as a fuse blowing means, so there is no need to apply a high voltage as in the conventional case, and circuit design using a single power supply is possible. becomes possible.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a program circuit in a conventional redundant circuit, Figure 2 is a circuit diagram showing a block configuration of a program circuit according to an embodiment of the present invention, and Figure 3 is a program enabler used in which invention. FIG. 4 is an equivalent circuit diagram for explaining the operation of the program enable circuit; FIG. 5 is a cross-sectional view showing an example of the circuit configuration; FIG. 5 is a diagram showing another example of the configuration of the program enable circuit used in the present invention. FIG. In the figure, (121 is an address decoder, t131i
j) ~ program control circuit, (14) is AND circuit, U3
1f'l program enable circuit, θ6) is an input terminal, (17) is pMO8 (second conduction type channel field effect transistor'), (19) is a fuse, (20) is n-
DMO8 (first conduction type channel tapered field effect transistor), ■υ is the ground point, cAI''i output terminal, □ is the semiconductor substrate, □ is the first p-type (second conduction type) region, (2) is the second p-type (second conductivity type) region, (e) is the first first conductivity type region, (a) is the third second conductivity type region,
Kan is the second first conductivity type region, Kan is the third first conductivity type region, and Zeng is the fourth second conduction type region. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno (1 other person) Figure 1 Figure 2,! ' / ll l / Figure 3 J Figure 4 J Figure 5 Continuation of amendment (voluntary) 1. Indication of the case Japanese Patent Application No. 58-3144 No. 3, Relationship with the person making the amendment case
2J'112-3 Marunouchi, Chiyoda-ku, Tokyo First name
(601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent 5, Claims column of the specification to be amended and Brief description of drawings column 6, Contents of the amendment (1) Specification amend the scope of the claims as per the attached appendix. (2) Page 11, lines 16, 17 and 2 of the specification
In line 0, and in the first line (two places), second line (two places), third line, and fourth line of page 12, the words "conduction" are all corrected to "conduction." 7. Documents showing the scope of claims after correction of list of attached documents One or more copies Claims (1) A first 21st type region formed in a part of the main surface of a 14ILE type semiconductor substrate; , a second second conductivity type region formed in another portion of the main surface of the semiconductor substrate and having a higher impurity concentration than the first second conductivity type region; and a second second conductivity type region having a higher impurity concentration than the semiconductor substrate. a third second conductivity type region formed in a part of the surface of the first second conductivity type region and having a higher impurity concentration than the first second conductivity type region; and a second first conductivity type region having an impurity concentration higher than that of the semiconductor substrate, and a third region having an impurity concentration higher than the semiconductor substrate formed in another part of the surface of the first second conductivity type region. a fourth second conductivity type region formed in another part of the main surface portion of the semiconductor substrate and having a higher impurity concentration than the first second conductivity type region; The second first conductivity type region and the third second region! type region is grounded, and the third first conductivity type region or the fourth conductivity type region is grounded.
The second conductivity type region is connected to the input terminal, and the first conductivity type region is connected to the input terminal.
The first conductivity type region and the second second conductivity type region are provided with a program enable circuit device connected to an output terminal, and the All-D circuit obtains the AND of the output of the address decoder and the output of the program control circuit. A fuse is connected between the drain of the field effect transistor of the second conductivity type channel, the output of which is supplied to the gate, and the source of which is connected to the power supply, and the output terminal; The drain of a depletion field effect transistor of one conductivity type channel is connected, and by applying a trigger surge voltage of a desired polarity to the input terminal, a latch-up phenomenon is caused in the program enable circuit device and the fuse is blown. A program circuit device in a redundant circuit, characterized in that: (2) A program circuit device in a redundant circuit according to claim 1, wherein the fuse is made of polycrystalline silicon.

Claims (2)

[Claims] (1) a first second conductivity type region formed in a part of the main surface of the semiconductor substrate of the first conductivity type; and a first second conductivity type region formed in another part of the main surface of the semiconductor substrate; a second conduction type region having a higher impurity concentration than the conduction type region; and a first conduction type region having a higher impurity concentration than the semiconductor substrate;
a conduction type region, a third second conductivity type region formed in a part of the surface of the first second conductivity type region and having a higher impurity concentration than the first second conductivity type region, and the semiconductor substrate. a second first conductivity type region having a higher impurity concentration; and a second first conductivity type region formed in another part of the surface of the first second conductivity type region and having a higher impurity concentration than the semiconductor substrate. a second conductivity type region or a fourth second conductivity type region formed in another part of the main surface portion of the semiconductor substrate and having a higher impurity concentration than the first second conductivity type region; The first conductivity type region and the third second conductivity type region are grounded, and the third first conductivity type region or the fourth conductivity type region is grounded.
the second conductivity type region is connected to the input terminal, and the first conductivity type region is connected to the input terminal;
and a program enable circuit device in which the first conductivity type region and the second second conductivity type region are connected to an output terminal, and the output of the address decoder and the output of the program control circuit are logically ANDed. A fuse is connected between the drain of the field effect transistor of the second conduction type channel, whose gate is supplied with the output of the AND circuit whose source is connected to the power supply, and the output terminal, and the gate and source are connected to the output terminal. The drain of the depletion field effect transistor of the grounded first conduction type channel becomes disconnected and causes a ratt-up phenomenon in the program enable circuit device by applying a trigger surge voltage of a desired polarity to the input terminal. 1. A program circuit device in a redundant circuit, characterized in that the fuse is fused by the fuse. (2) A program circuit device in a redundant circuit according to claim 1, wherein the fuse is made of polycrystalline silicon.