JPH04253417A - Level shift circuit - Google Patents

Abstract

PURPOSE:To prevent a through current by detecting the through current at the first and second bipolar transistors for through current detection of a detec tion circuit and turning off first and second field-effect transistors to cut current. CONSTITUTION:The connecting points of NFET 1 and 2 and resistors 100 and 101 are respectively connected to the base electrodes of NPN transistors 7 and 8, the emitters are connected to a ground line GND, and the collectors are connected to the bases of PNP transistors 9 and 10. The emitters of the PNP transistors 9 and 10 are connected to a power supply VDD 2 at a high level, and the collectors are connected to the gates of PMOSFET 5 and 6 provided between PMOSFET 3 and 4 for level shifter and the power supply VDD 2. When the through current starts flowing, the NPN transistors 7 and 8 are turned on, thus, the PNP transistors 9 and 10 are turned on as well, and the PMOSFET 5 and 6 are turned off.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit, and more particularly to a level shift circuit for semiconductor integrated circuits.

0002

2. Description of the Related Art As shown in FIG. 2, a conventional level shift circuit includes N-type MOSFETs 201 and 202 that operate with low-level signals IN1 and IN2, and a P-type MOSFET 203 connected to a high-level power supply VDD2. ,204
The P-type MOSFETs 203 and 204 were connected to the drains of the N-type MOSFETs 202 and 201.

Next, the operation of the conventional example will be explained. Low level input signals IN1 and IN2 are complementary to each other. Therefore, when the N-type MOSFET 201 is on, the N-type MOSFET 201
ET202 is always off, and N-type MOSFET201
When is off, N-type MOSFET 202 is always on.

[0004] When N-type MOSFET 201 is on, N-type MOSFET 202 is off, and N-type MOSFET 202 is off.
Since MOSFET 201 is on, the gate of P-type MOSFET 204 becomes ground level (GND) and turns on. Therefore, a high level (VDD2 level) signal is output to the output OUT. On the other hand, since the P-type MOSFET 204 is on, the gate of the P-type MOSFET 203 becomes a high level VDD2, and the P-type MOSFET 203 is turned off.

On the contrary, when the N-type MOSFET 201 turns off, the N-type MOS 202 turns on, and the P-type MOSFE
The gate potential of T203 decreases, and the P-type MOSFET20
3 turns on. When the P-type MOSFET 203 is turned on, the potential of the gate of the P-type MOSFET 204 increases, and the P-type MOSFET 204 is turned off. therefore,
The output OUT becomes the ground level.

[0006]

[Problem to be Solved by the Invention] In this conventional level shift circuit, when the input signal is inverted, depending on the timing of the inversion, a state occurs in which both the P-type MOSFET and the N-type MOSFET connected in series are turned on. However, at this time, there is a problem that a through current flows from the high level power supply VDD2 to the ground line GND.

[0007]

[Means for Solving the Problems] The gist of the present invention is to provide a first field effect transistor connected between a power supply line and a ground line and including a first field effect transistor of one conductivity type and a second field effect transistor of the other conductivity type. a series circuit; a second series circuit connected between a power supply line and a ground line and including a third field effect transistor of one conductivity type and a fourth field effect transistor of the other conductivity type; A set of input signals is supplied to the gates of the four field effect transistors, the gates of the first and third field effect transistors are connected to the drains of the second and fourth field effect transistors, and the output is output from the drain of the third field effect transistor. In the level shift circuit that obtains the
, a second current interrupting field effect transistor is interposed therebetween, detecting the through current of the first and second series circuits, and turning off the first and second current interrupting field effect transistors. This is because a detection circuit including a bipolar transistor is provided.

[0008]

[Operation of the invention] When a through current flows through the first series circuit and the second series circuit, the first and second through current detection bipolar transistors of the detection circuit respectively detect the through current, and the first through current detecting bipolar transistor detects the through current.
, turns off the second current cutoff field effect transistor.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a level shift circuit according to a first embodiment of the present invention. In this embodiment, N-type MOSFET1
, 2 and the ground line GND, and connect the connection point between the N-type FETs 1, 2 and the resistors 100, 101 to N
It is connected to the base electrodes of PN transistors 7 and 8, respectively, its emitter is connected to the ground line GND, and its collector is connected to the bases of PNP transistors 9 and 10. The emitters of the PNP transistors 9 and 10 are connected to a high-level power supply VDD2, and the collectors are connected to a P-type MOSFE for level shifter.
P-type MOS provided between T3, 4 and power supply VDD2
It is connected to the gates of FETs 5 and 6, and is further connected to the ground line GND through resistors 102 and 103.

When the through current begins to flow, the NPN transistors 7 and 8 turn on, and as a result, the PNP transistor 9
, 10 are also turned on, and the P-type MOSFETs 5 and 6 are turned off. Since the P-type MOSFETs 5 and 6 cut off the current path, no through current flows.

FIG. 3 shows a second embodiment of the invention. Components that are the same as those in the first embodiment are designated by the same reference numerals, and descriptions thereof will be omitted. A P-type MOSFET is connected between P-type MOSFETs 3 and 4 and power supply VDD2.
SFETs 5 and 6 are interposed, and the P-type MOSFETs 5,
The source of PNP transistor 6 is connected to the power supply VDD2 via the bases of PNP transistors 9 and 10 and resistors 120 and 121.
The emitters of the NP transistors 9 and 10 are connected to the power supply VDD2, and the collectors are connected to the ground line GND through the gates of the P-type MOSFETs 5 and 6 and resistors 130 and 131.

When the through current begins to flow, the PNP transistors 9 and 10 are turned on and the P-type MOSFETs 5 and 6 are turned off. Therefore, the current path is cut off and no through current flows.

FIG. 4 shows a third embodiment of the present invention,
Components that are the same as those in the first embodiment are given the same reference numerals. P-type MOS
N-type M between FET3, 4 and N-type MOSFET1, 2
OSFET140, 141 are provided, and N-type MOSFET1
, 2 are connected to the ground line GND through resistors 150 and 151. The sources of the N-type MOSFETs 1 and 2 are connected to the bases of the NPN transistors 7 and 8, the emitters of the NPN transistors 7 and 8 are connected to the ground line GND, and the collectors are connected to the gates of the N-type MOSFETs 140 and 141 and the resistors 160 and 1.
61 to the power supply VDD2.

When the through current begins to flow, the NPN transistors 7 and 8 are turned on, so that the N-type MOSFET 1
40 and 141 are turned off, and no through current flows.

When a conventional level shift circuit is connected between a DC 100V power supply 500 and ground as shown in FIG. 5, and the voltage of inputs IN1 and IN2 is changed and the output current is measured, the SPICE simulation The results are shown in FIG.

On the other hand, when the level shift circuit of the present invention is configured as shown in FIG. 7 and a SPICE simulation is performed,
The results shown in FIG. 8 are obtained. Comparing FIG. 6 and FIG. 8, it can be seen that the power consumption has been reduced to 1/6.

[0018]

As explained above, according to the present invention, since the bipolar transistor for detecting through current turns off the transistor for cutting off current, it is possible to obtain the effect that through current can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a level shift circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional level shift circuit.

FIG. 3 is a circuit diagram of a level shift circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a level shift circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional level shift circuit used in SPICE simulation.

FIG. 6 is a graph showing SPICE simulation results of the circuit shown in FIG. 5;

FIG. 7 is a circuit diagram showing a level shift circuit according to the present invention used in SPICE simulation.

FIG. 8 is a graph showing SPICE simulation results of the circuit shown in FIG. 7;

[Explanation of symbols]

1 P-channel MOSFET (first field-effect transistor) 2 P-channel MOSFET (second field-effect transistor) 3 N-channel MOSFET (third field-effect transistor) 4 N-channel MOSFET (fourth field-effect transistor) 5 P Channel type MOSFET (first current cutoff field effect transistor) 6 P channel type MOSFET (second current cutoff field effect transistor) 7 NPN bipolar transistor (first through current detection transistor) 8 NPN bipolar transistor (second through current detection transistor) (detection transistor) 9 PNP bipolar transistor (first through current detection transistor) 10 PNP bipolar transistor (second through current detection transistor)

Claims (4)

[Claims] 1. A first series circuit including a first field effect transistor of one conductivity type and a second field effect transistor of the other conductivity type connected between a power supply line and a ground line; a second series circuit including a third field effect transistor of one conductivity type and a fourth field effect transistor of the other conductivity type connected between the transistors; In a level shift circuit that supplies an input signal, connects the gates of the first and third field effect transistors to the drains of the second and fourth field effect transistors, and obtains an output from the drain of the third field effect transistor, the first, A first system in which first and second current-blocking field-effect transistors are interposed in the second series circuit, and the through-current of the first and second series circuits is detected to turn off the first and second current-blocking field-effect transistors. , a level shift circuit comprising a detection circuit including a second through-current detection bipolar transistor. 2. The first and second current-blocking field-effect transistors are one-conductivity-type field-effect transistors connected in series to the first and second series circuits, and the detection circuit is comprised of the second and fourth field-effect transistors. first and second resistors interposed between the source and the ground line, and the first and second one-carrier type resistors whose emitters are connected to the ground line and whose bases are connected to the sources of the second and fourth field effect transistors, respectively. A second through-current detection bipolar transistor, whose base is connected to the collectors of the first and second through-current detection bipolar transistors, respectively, is connected between the power supply line and the gates of the first and second current-blocking field-effect transistors. 2. The level shift circuit according to claim 1, further comprising interposed third and fourth bipolar transistors of different carrier type. 3. The first and second current interrupting field effect transistors are field effect transistors of one conductivity type connected in series to the first and second series circuits, and the detection circuit is connected to the power supply line and the first and second series circuits. first and second resistors interposed between the sources of the three field effect transistors; and a power line whose bases are connected to the sources of the first and third field effect transistors, respectively;
First and second through-current detection bipolar transistors of other carrier type interposed between the gates of the first and second current-blocking field-effect transistors, and the first and second current-blocking field-effect transistors. 2. The level shift circuit according to claim 1, further comprising third and fourth resistors interposed between the gate and the ground line. 4. The first and second current-blocking field-effect transistors include first and second field-effect transistors and a third,
A field effect transistor of a different conductivity type interposed between the fourth field effect transistor and the detection circuit includes first and second resistors interposed between the sources of the second and fourth field effect transistors and the ground line. and first and second one-carrier type through currents whose bases are respectively connected to the sources of the second and fourth field effect transistors and which are interposed between the gates of the first and second current-blocking field effect transistors and the ground line. The detection bipolar transistor and the third and fourth current cutoff field effect transistors are interposed between the gates of the first and second current cutoff field effect transistors and the power supply line.
2. The level shift circuit according to claim 1, further comprising a resistor.