JP2984362B2 - Output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to an output circuit for transmitting a signal between ICs via a transmission line.

(Prior art) Output circuits for performing signal transmission between ICs include ECL circuits and CMOS circuits.
The circuit is better. Therefore, when transmitting signals between the CMOSIC and ECLIC, a method of inputting and outputting signals in accordance with ECL logic is adopted. In this case, in a CMOS IC, there is a method of providing an ECL output circuit on the same chip as the CMOS IC by a BiCMOS process in which a bipolar element and a CMOS can be formed on the same chip. CMOS logic
By configuring the output unit with ECL, signal output can be performed at high speed and signal transmission can be unified to ECL logic.

However, when compared in the development phase, the bipolar device manufactured by the BiCMOS process does not operate faster than the device manufactured by the single bipolar process, and the CMOS device manufactured by the BiCMOS process uses the single CMOS process. Development is lagging, for example, the degree of integration is not as high as that of manufactured devices.

Therefore, a circuit that outputs ECL logic with a CMOS output circuit is conceivable.However, since a CMOS transistor has a smaller mutual conductance than a bipolar transistor, it is difficult to output an ECL logic signal with an output circuit using a CMOS transistor. Was.

In general, the relationship between the drain current Id flowing through a MOS transistor and the gate-source electrode voltage Vgs is expressed by the following equation.

(Vgs−Vth) ² = k * Id where Vth is a threshold voltage and k is a constant. To output the ECL logic, it is necessary to respond to the logic signal "H".
It is assumed that a drain current of about 6 [mA] flows when corresponding to 24 [mA] and the logic signal "L". From the above equation, if the drain current of the CMOS transistor changes four times, Vgs
-Vth will change twice. For example, assuming that the value of Vgs-Vth is 0.6-0.8 [V], Vgs-Vth needs a further variation of 0.6-0.8 [V] to change the drain current four times. Therefore, there is a problem in terms of circuit configuration, for example, a voltage source for complementing the current driving force must be newly added. There is also a method of outputting the ECL logic by making the structure of the MOS transistor depletion type, but the manufacturing process of the IC becomes complicated. There has been a problem in that characteristics of each element vary.

(Problems to be Solved by the Invention) When a large-scale system is configured by logic ICs, the signal transmission between the ICs is unified to the ECL logic, whereby the operation of the entire system can be performed at high speed.

However, when a circuit that outputs the ECL logic using CMOS transistors is configured, there is a problem in terms of a circuit configuration and an element manufacturing process.

An object of the present invention is to provide a CMOS output circuit that outputs ECL logic by adding a simple circuit to the output stage of a CMOS IC.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, according to the present invention, a first electrode in which a drain electrode is connected to a first reference potential and a gate electrode is connected to a logic circuit. A MOS transistor and the first
A first current source which is connected in parallel to the MOS transistor of which the current value changes according to the logical value of a signal from the logic circuit;
An output terminal in which a source electrode of the MOS transistor and an output terminal of the first current source are commonly connected, and a terminating resistor having one end connected to the output terminal via a transmission line. Provide an output circuit.

(Operation) The logic signal transmitted from the logic circuit gives a logic value of either “H” or “L”, and the current source provided in the output circuit has two types according to the logic value of the logic signal. It has a function of outputting a current. The current output from the output circuit flows through the transmission line to the terminating resistor, thereby transmitting a signal to the second IC circuit.

According to the circuit configuration of the present invention, by using a MOS transistor and a current source that generates a current value according to the logic value of a logic signal, the current driving power is extended as compared with a conventional MOS transistor output circuit. A CMOS output circuit can be configured. As a result, even in a CMOS output circuit, signal transmission by ECL logic can be performed with a simple configuration.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

 FIG. 1 is a configuration diagram showing an embodiment of the present invention.

The drain electrode of the transistor 2 is connected to the first reference potential 6, and the source electrode is connected to the output terminal 9. A current source 3 is connected in parallel with the transistor 2. The current source 3 outputs two types of currents having different values according to the logic value of the logic signal from the logic circuit. The output terminal 9 is connected to the source electrode of the transistor 2 and the output terminal of the current source 3, and the signal current is transmitted to the terminating resistor 5 via the transmission line 4.

The operation of this circuit will be described. It is assumed that two types of currents having different values are output to the current source 3 according to the logical value of the logical signal. That is, when the logic value of the logic signal from the logic circuit is "H", the current I1 flows through the current source 3, and when the logic value is "L", the current I2 flows. Note that I1 is larger than I2. By arranging this current source in parallel with the transistor, a MOS transistor having a small current driving capability is complemented, and a current output of ECL logic is enabled.

That is, when the logic value of the logic signal is “H”, a combined current of the drain current of the transistor 2 and the current I 1 of the current source 3 is output from the output terminal 9 and flows to the terminating resistor 5 via the transmission line 4. As a result, the logical value “H” is transmitted to the output terminal 8. On the other hand, when the logic value of the logic signal is “L”, the current I 2 of the current source 3 is output from the output terminal 9 and flows through the transmission line 4 to the terminating resistor 5. As a result, the output terminal 8
Is transmitted with the logical value "L". According to such a configuration,
ECL logic can be output by a CMOS output circuit to which a current source whose output current changes according to the logic value of the logic signal is added.

Next, the embodiment shown in FIG. 2 will be described. This is configured by adding an additional circuit to the signal input stage from the logic circuit in the circuit shown in FIG.

The transistors 21 and 22 are a P-channel transistor and an N-channel transistor, respectively, which are connected in series to form a so-called inverter circuit. The source electrode of the transistor 23 is connected to a voltage source 26 via a current source 24.
, And the drain electrode is connected to the voltage source 6 via the resistor 25. Further, the drain electrode of the transistor 23 is connected to the gate electrode of the transistor 2. The transistor 2 and the current source 3 constitute the circuit shown in FIG. 1, and the output terminal 9 is connected to the terminating resistor 5 via the transmission line 4.

The operation of the circuit shown in FIG. 2 will be described. Transistor 2
And the current source 3 are provided in parallel at the output stage of the circuit,
It has the same configuration as the circuit shown in the figure. The current source 24 has a function of changing the output current according to the logic value of the logic signal. If the logic value of the logic signal is "H", it is assumed that no current flows through the current source 24, When the value is “L”, it is assumed that the current I3 flows through the current source 24.

Consider a case where the logic value of the logic signal is “H”. Since the terminal 27 becomes “L” by the inverter constituted by the transistors 21 and 22 and the current value of the current source 24 becomes zero,
28 has the same potential as the power supply voltage 6 and outputs a logical value "H". At this time, the current corresponding to the logical value "H" is supplied to the current source 3.
Since I1 flows, the I1 flows to the terminating resistor 5 via the transmission line 4, so that the logical value "H" can be transmitted to the output terminal 8. Conversely, when the logic value of the logic signal is "L", the terminal 27 becomes the logic value "H" and the current value of the current source 24 becomes I3. At this time, the potential of the terminal 28 becomes (V66−I3 * R25) in consideration of the voltage drop of the resistor 25. (However, V6
6 is a reference potential of the voltage source 6, and R25 is a resistance value of the resistor 25. This potential is received by the gate electrode of transistor 2,
The logical value “L” is output to the output terminal 8. At this time, the setting of the potential “L” is determined by the combined current of the drain current of the transistor 2 and the current value of the current source 3 and the terminating resistor 5. Even with this circuit configuration, a CMOS output circuit that outputs the ECL logic can be realized.

In particular, by adjusting the magnitude of the current value of the current source 3 when the logic value of the logic signal is “L” in this circuit, the magnitude of the current flowing through the transistor 2 can be adjusted. For example, assume that the voltage source 6 is grounded and the voltage source 7 is -2 [V], and the ECL logic output is assumed. The current of the current source 3 is set to 10 [m
A], a current of approximately 14 [mA] flows through the transistor 2. When the current of the current source 3 is set to 24 [mA], the transistor 2 is cut off. This current is also defined by the threshold voltage of the transistor and the ratio of the gate length to the gate width.

FIG. 3 shows the circuit shown in FIG.
5 is a configuration example of a circuit in the case of replacing with. When the logic value of the logic signal is "H", the current I1 flows through the current source 3 substantially in the same manner as the circuit shown in FIG. 2, so that the logic value "H" is output to the output terminal 8. . When the logic value of the logic signal is “L”, the terminal 27 becomes “H”, so that a current flows through the transistor 23 and a potential determined at the potential drop of the resistor 25 is generated at the terminal 28. The potential of the terminal 28 is the gate potential of the transistor 2. In response to this, a signal of a logical value of “L” is transmitted to the output terminal 8. Terminal at this time
Since the potential of 28 is determined by the voltage drop of resistor 25,
The output signal potential can be defined by the resistance ratio between 25 and 32.

The current source 3 of the circuit shown in FIG. 3 has a function of changing the output current according to the logic level of the logic signal. FIG. 4 shows a circuit in which the function of the current source 3 is replaced by a transistor to form a circuit.

This is obtained by replacing the voltage source 3 with a transistor 41 in the circuit shown in FIG. Transistor 41 is P
The channel transistor is configured by connecting the gate electrode to the terminal 27, connecting the source electrode to the voltage source 6, and connecting the drain electrode to the output terminal 9. The transistor 41 conducts current when the terminal 27 is at “L”,
Is "H", the current does not flow, and therefore has a function of outputting a current according to the logical value of the logical signal. Therefore, by replacing the current source 3, a circuit configuration can be realized. In this way, instead of using a current source whose output current changes according to the logic value of the logic signal, a transistor that changes the drain current by receiving the gate electrode potential according to the logic value of the logic signal can also be used as an ECL logic. A signal can be output.

FIG. 5 shows an embodiment in which a resistor is required in addition to the circuit configuration of FIG. This is achieved by inserting a resistor 51 between the transistor 41 and the voltage source 6. The operating principle is the same as that of the circuit shown in FIG.

In particular, according to this configuration, by setting the resistance value of the resistor 51, the transistor 41 is set to be smaller than in the case of the circuit shown in FIG.
The current value flowing through can be set with high accuracy. When the resistance of the resistor 51 is set, the value of the current flowing through the transmission line to the terminating resistor is also defined.
The output potential of the output terminal 8 can be adjusted by the ratio of the resistance value to the output terminal 8.

FIG. 6 shows an embodiment in which a differential pair transistor is used in a logic signal input stage. In this embodiment, a differential input circuit is added to a signal input stage from a logic circuit in the embodiment shown in FIG.

The configuration of this circuit will be described. The transistors 61 and 62 are differential pair transistors, and complementary input signals are transmitted to the gate electrodes of these differential pair transistors, respectively. The source electrode of the transistor is connected to the voltage source 6 via resistors 67 and 68, respectively, and the common drain electrode is connected to the resistor 69.
To the voltage source 26 via Terminal 63 is transistor 61
And is connected to the gate electrode of the transistor 66. Similarly, terminal 64 is the source electrode of transistor 62 and is connected to the gate electrode of transistor 65. The source electrode of the transistor 65 and the drain electrode of the transistor 66 are connected to the output terminal 9, and the output terminal 9 is connected to the transmission line 4.
To the terminating resistor 5.

Next, the circuit operation will be described. The logic value of the logic signal is "H"
Consider the case An “H” signal is input to the gate electrode of the transistor 61, and an “L” signal is input to the gate electrode of the transistor 62 via an inverter circuit. At this time, a current flows through the transistor 61, and a potential is determined at the terminal 63 by the ratio of the resistor 67 and the resistor 69. Since no current flows through the transistor 62, a potential equal to the reference potential of the voltage source 6 is generated at the terminal 64. Since drain currents flow through the transistors 65 and 66, a combined current of these drain currents is output to the output terminal 9 and transmitted to the terminating resistor 5 via the transmission line 4. This corresponds to the logic value "H" of the logic signal. When the logic value of the logic signal is “L”, no current flows through the transistor 61 and the terminal 63 has the same potential as the reference potential of the voltage source 6. No current flows through the transistor 66 in response to the potential of the terminal 63. Also transistors
Since drain current flows through 62, terminal 64 is connected to resistors 68 and 69
A potential determined by the ratio of the resistance value to Upon receiving the potential of the terminal 64, a drain current flows through the transistor 65. When the drain current flows through the terminating resistor 5, a potential is generated at the output terminal 8, and a signal having a logical value "L" is transmitted.

Even with such a configuration, it is possible to provide a CMOS circuit that outputs an ECL logic signal by using a transistor whose current value changes in accordance with the logic value of a logic signal as a component.

In particular, in the circuit shown in this embodiment, there is one input line for the logic signal from the logic circuit, but the input stage may be any input signal that can drive a differential pair transistor. Therefore, the input line may be composed of one or two input lines on condition that complementary logic signals are input to the two differential input terminals.

With the above circuit configuration, a CMOS output circuit that outputs an ECL logic signal is realized.

In each of the circuits shown in the above embodiments,
The MOS transistor made of Si was explained.
The same effect can be obtained even if the circuit is configured using a MESFET made of GaAs or the like instead of the FET.

[Effects of the Invention] According to the present invention, by configuring a CMOS output circuit that outputs ECL logic using a current source whose current value changes according to the logical value of a logical signal, an EC using only a CMOS process is provided.
Signal transmission of L logic can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an embodiment in which an additional circuit is added to the input stage of the circuit shown in FIG. 1, and FIG. 3 is a diagram shown in FIG. FIG. 4 is a diagram showing another embodiment in which an additional circuit is added to the input stage of the circuit, FIG. 4 is a diagram showing an embodiment in which the current source of the circuit shown in FIG. 1 is replaced by a transistor, and FIG. FIG. 6 is a diagram showing another embodiment in which the current source of the circuit shown in FIG. 6 is replaced by a transistor. FIG. 6 is a diagram showing an embodiment in which a differential circuit is added to the input stage of the circuit shown in FIG. 2,21,22,23,41,61,62,65,66,72,73 …… transistors,
3,24 ... current source, 25, 32, 51, 67, 68, 69 ... resistor, 4 ...
Transmission line, 5 ... Terminating resistor, 6,7,26,71 ... Voltage source, 8,27,
28, 63, 64 ... terminals, 1 ... logic circuits.

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Shigeru Tanaka 1 Toshiba Research Institute, Komukai, Kawasaki-shi, Kanagawa Prefecture (58) Field surveyed (Int.Cl. ⁶ , DB name) / 0175,19 / 0185

Claims (7)

(57) [Claims] 1. A first MOS transistor having a drain electrode connected to a first reference potential, a gate electrode connected to a logic circuit, and a first MOS transistor connected in parallel to the first MOS transistor to receive a signal from the logic circuit. A first current source whose current value changes in accordance with a logical value; an output terminal in which a source electrode of the first MOS transistor and an output terminal of the first current source are commonly connected; And a terminating resistor connected to the output terminal via the output terminal. 2. The output circuit according to claim 1, wherein a second reference potential is connected to the other end of the terminating resistor, and a voltage between both ends of the terminating resistor is taken out as an output. 3. The logic circuit according to claim 1, wherein a P-channel transistor and an N-channel transistor are connected between a first reference potential connected to one end of the logic circuit and a third reference potential connected to the other end of the logic circuit. Are connected in series, the input terminal is connected to each gate electrode of the P-channel transistor and the N-channel transistor, the common drain electrode is connected to the gate electrode of the second N-channel transistor, and the second N An input having a drain electrode of the channel transistor connected to the third reference potential via a second current source, and a source electrode of the second N-channel transistor connected to the first reference potential via a resistor; 2. The output circuit according to claim 1, wherein the output circuit comprises a stage circuit. 4. The output circuit according to claim 1, wherein said first current source comprises a P-channel transistor whose gate electrode is commonly connected to a gate electrode of said second N-channel transistor. . 5. The first current source comprises: a P-channel transistor having a gate electrode commonly connected to a gate electrode of the second N-channel transistor; and a first current source connected to a source electrode of the P-channel transistor and the first reference potential. 2. The output circuit according to claim 1, wherein the output circuit comprises a resistor connected therebetween. 6. The logic circuit according to claim 1, wherein a P-channel transistor and an N-channel transistor are connected between the first reference potential and the third reference potential.
A channel transistor is connected in series, an input terminal is connected to each gate electrode of the P-channel transistor and the N-channel transistor, and a common drain electrode and a second
Is connected to the gate electrode of the N-channel transistor of
A drain electrode of the second N-channel transistor is connected to the third reference potential via a second current source, and a source electrode of the second N-channel transistor is connected to the first reference potential via a resistor. 6. The output circuit according to claim 5, comprising an input stage circuit connected to the input circuit. 7. The logic circuit according to claim 1, wherein a P-channel transistor and an N-channel transistor are connected between the first reference potential and the third reference potential.
A channel transistor is connected in series, an input terminal is connected to each gate electrode of the P-channel transistor and the N-channel transistor, and a common drain electrode and a second
Is connected to the gate electrode of the N-channel transistor of
A drain electrode of the second N-channel transistor is connected to the third reference potential via a second current source, and a source electrode of the second N-channel transistor is connected to the first reference potential via a resistor. 6. The output circuit according to claim 5, comprising an input stage circuit connected to the input circuit.