JP3768201B2 - CMOS output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CMOS output circuit for preventing latch-up in a complementary metal-oxide semiconductor (CMOS) type semiconductor integrated circuit.
[0002]
[Prior art]
FIG. 2 is a schematic cross-sectional view of a CMOS output circuit in a conventional general CMOS type semiconductor integrated circuit, and FIG. 3 shows a connection relationship between bipolar transistors and resistors formed parasitically in the CMOS output circuit of FIG. It is a circuit diagram.
[0003]
The CMOS output circuit shown in FIG. 2 is formed on, for example, an N-type substrate (substrate) 1. A P-well 2 is formed in the N-type substrate 1, a P-channel MOS transistor (hereinafter referred to as “PMOS”) 10 is formed on the main surface of the substrate 1, and further on the main surface of the P-well 2. An N-channel MOS transistor (hereinafter referred to as NMOS) 20 is formed. The PMOS 10 includes a source 10S and a drain 10D made of a p ⁺ diffusion layer formed on the main surface of the substrate 1, and a gate 10G formed between the source 10S and the drain 10D. The NMOS 20 is composed of a source 20S and a drain 20D made of an n ⁺ diffusion layer formed on the main surface of the P well 2, and a gate 20G formed between the source 20S and the drain 20D. Further, an n ⁺ diffusion layer 31 is formed in the vicinity of the source 10S of the PMOS 10 and a p ⁺ diffusion layer 32 is also formed in the vicinity of the source 20S of the NMOS 20.
[0004]
The source 10S and n ⁺ diffusion layer 31 of the PMOS 10 are connected to a high-level power supply (hereinafter referred to as VCC), the gate 10G of the PMOS 10 and the gate 20G of the NMOS 20 are commonly connected to the input terminal IN, and the drain 10D of the PMOS 10 and the drain of the NMOS 20 20D is commonly connected to the output terminal OUT. The source 20S and the p ⁺ diffusion layer 32 of the NMOS 20 are connected to a low power supply (hereinafter referred to as VSS).
[0005]
In such a CMOS output circuit, as shown in FIG. 3, bipolar transistors T1, T2, T3, T4 and a parasitic resistance R2 are usually formed in a parasitic manner. In FIG. 2, a PNP transistor T1 is formed parasitically between the drain 10D and the P well 2, and a PNP transistor T3 is also formed between the source 10S and the P well 2. Further, parasitic NPN transistors T2 and T4 are also formed between the substrate 1 and the source 20S and drain 20D. The bases of the transistors T1 and T3 are connected to the n + diffusion layer 31, and the bases of the transistors T2 and T4 are connected to the p + diffusion layer 32.
[0006]
Further, as shown in FIG. 3, a parasitic resistance R1 is formed in the P-well 2, which is the collector of the transistor T1, the base of the transistor T2, the collector of the transistor T3, the base of the transistor T4, and the emitter of the transistor T2. And VSS. The resistor R2 in the substrate 1 is connected between VCC and the emitter of the transistor T3 and the base of the transistor T1, the collector of the transistor T2, the base of the transistor T3, and the collector of the transistor T4. Note that i1 and i2 in FIG. 3 are collector currents.
[0007]
In this type of CMOS output circuit, when an “H” level (VCC level) signal is input to the input terminal IN, the PMOS 10 is turned off, the NMOS 20 is turned on, and the output terminal OUT is turned “L” level (VSS level). ) When an “L” level signal is input to the input terminal IN, the PMOS 10 is turned on, the NMOS 20 is turned off, and the output terminal OUT is set to the “H” level.
[0008]
[Problems to be solved by the invention]
However, in the CMOS output circuit configured as described above, a latch-up phenomenon peculiar to the CMOS circuit occurs due to a trigger (generally, a voltage applied higher than the VCC level or a voltage applied lower than the VSS level) from the output terminal OUT. There was a problem that it was easy to do.
[0009]
Here, the mechanism leading to the occurrence of latch-up will be described with reference to FIG. For example, when a trigger voltage higher than the VCC level is applied to the output terminal OUT, the transistor T1 is turned on. As a result, the collector current i1 flows from the output terminal OUT to the VSS through the transistor T1 and the parasitic resistance R1 of the P well 2. At this time, the base potential of the transistor T2 rises due to the parasitic resistance R1 in the P-well 2, and the base and emitter of the transistor T2 are forward-biased and turned on. When the transistor T2 is turned on, the collector current i2 of the transistor T2 flows from the VCC through the resistor R2 in the substrate 1 and further flows to the VSS through the transistor T2. Therefore, the resistor R2 in the substrate 1 causes the transistor T2 The base potential of T3 drops, and the base and emitter are forward biased and turned on.
[0010]
Thus, when the transistors T2 and T3 are turned on, positive feedback is applied to them, and even if there is no trigger from the output terminal OUT, a current continues to flow from VCC to VSS, so-called a latch-up state. This may cause malfunction of the integrated circuit, melting of the power supply line, or destruction of the element.
[0011]
Similarly, when a trigger voltage lower than the VSS level is applied to the output terminal OUT, the transistors T4, T3, and T2 are turned on in the order of the transistors T4, T3, and T2, and the latch-up state is also reached. .
[0012]
The present invention provides a CMOS output circuit that solves the problem that the prior art has had that latch-up is likely to occur due to a trigger from the output terminal OUT and it is difficult to reduce it with a relatively simple configuration. It is to provide.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a first invention of the present invention is a CMOS output circuit that operates by being supplied with a high voltage and a low voltage, and includes a substrate having a main surface, a first MOS transistor, It has a second MOS transistor and resistance means. The first MOS transistor is formed in a first region of the main surface of the substrate, and is connected to a source of a first conductivity type to which one of the high voltage or the low voltage is supplied, and the output terminal A drain of the first conductivity type is included. The second MOS transistor is formed in a second region of the main surface of the substrate, and is connected to a source of a second conductivity type to which the other of the high voltage or the low voltage is supplied, and the output terminal A drain of the second conductivity type; Further, the resistance means has a number of contacts with the source arranged in series with the first MOS transistor, and a number of contacts with the drain arranged in series with the first MOS transistor. Is connected in series to the source of the first MOS transistor formed by reducing the number of the first MOS transistors.
[0014]
The second invention is a CMOS output circuit which operates by being supplied with a high voltage and a low voltage, and is different from the first invention in the same substrate and the first and second MOS transistors as in the first invention. Resistance means. The resistor means has a smaller number of contacts with the source arranged in series with the second MOS transistor than a number of contacts with the drain arranged in series with the second MOS transistor. In this way, the source of the second MOS transistor formed is connected in series.
[0015]
A third invention is a CMOS output circuit which operates by being supplied with a high voltage and a low voltage, and includes a substrate having a main surface, a first MOS transistor, a second MOS transistor, and resistance means. ing. The first MOS transistor is formed in a first region of the main surface of the substrate, extends in a predetermined direction with a certain width when viewed from the main surface of the substrate, and one of the high voltage and the low voltage is The first conductivity type source to be supplied and the first conductivity type extending in parallel to face the first conductivity type source with a constant width as viewed from the main surface of the substrate and connected to the output terminal And a first gate extending between the first conductivity type source and the first conductivity type drain and connected to the input terminal.
[0016]
The second MOS transistor is formed in a second region of the main surface of the substrate, extends in the predetermined direction with a constant width when viewed from the main surface of the substrate, and is the other of the high voltage and the low voltage And a second conductivity type source that is supplied in parallel with the source of the second conductivity type with a constant width when viewed from the main surface of the substrate and is connected to the output terminal. A drain of a conductivity type; and a second gate extending between the source of the second conductivity type and the drain of the second conductivity type and connected to the input terminal. Further, the resistance means has a plurality of contacts arranged in series along the longitudinal direction on the source of the first MOS transistor, and the number of contacts arranged in the longitudinal direction on the drain of the first MOS transistor. Are connected in series to the source of the first MOS transistor formed by reducing the number of contacts arranged in series along the line.
[0017]
A fourth invention is a CMOS output circuit which operates by being supplied with a high voltage and a low voltage, and is different from the third invention in the same substrate and the first and second MOS transistors as in the third invention. Resistance means. The resistance means has a plurality of contacts arranged in series along the longitudinal direction on the source of the second MOS transistor, and the number of contacts arranged along the longitudinal direction on the drain of the second MOS transistor. Are connected in series to the source of the second MOS transistor formed by reducing the number of contacts arranged in series.
[0018]
According to the first to fourth inventions, the number of the plurality of contacts on the source side of the MOS transistor is made smaller than the number of the plurality of contacts on the drain side, and the high voltage (VCC) and the low voltage (VSS). By adding a resistance component (resistance means) in series to the emitter part of the bipolar transistor that is parasitically formed between the two , the resistance component (resistance means) of the bipolar transistor when the trigger voltage is applied to the output terminal is added . Transition to the on state is suppressed. Therefore, the problem can be solved.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 4 is a circuit diagram of a connection relationship between a parasitic bipolar transistor and a resistor in a CMOS output circuit showing the principle of the embodiment of the present invention. Elements common to those in FIGS. Is attached.
[0020]
The CMOS output circuit of FIG. 4 has a structure in which parasitic resistors R3 and R4 as resistance means are added in series to the emitter of the parasitic NPN transistor T2 and the emitter of the PNP transistor T3 shown in FIG. Others are the same as the conventional structure. That is, the CMOS output circuit of FIG. 4 has a structure in which parasitic resistors R3 and R4 are added in series to the sources 10S and 20S of the PMOS 10 and NMOS 20 of FIG.
[0021]
In the CMOS output circuit of FIG. 4, for example, when a trigger voltage higher than the VCC level is applied to the output terminal OUT as in the conventional description, the emitter and base of the transistor T1 are forward-biased and turned on. The base potential of the transistor T2 rises due to the parasitic resistance R1 in the P-well 2, and the emitter-base is forward-biased, and the transistor T2 is turned on. Thus, the transistors T1 and T2 are turned on as in the conventional case, but the collector current i2 flowing through the resistor R2 in the substrate 1 is limited by the resistor R3 connected in series with the emitter of the transistor T2. As a result, the decrease in the base potential of the transistor T3 is moderated. As a result, the transistor T3 does not easily shift to the on state, so that the transistors T2 and T3 are not positively fed back to each other, and the latch-up state is hardly generated.
[0022]
Conversely, even when a trigger voltage lower than the VSS level is applied to the output terminal OUT, the collector current of the transistor T3 is limited by the resistor R4 connected in series to the emitter of the transistor T3. It becomes difficult to shift to the on-state, thereby preventing the occurrence of latch-up. Accordingly, the latch-up can be accurately reduced with a simple structure in which parasitic resistors R3 and R4 are added to the emitter portions of the transistors T2 and T3 formed in a parasitic manner.
[0023]
FIG. 1 is a schematic layout diagram of a CMOS output circuit showing an embodiment of the present invention using the principle of FIG.
[0024]
In this CMOS output circuit, for example, a plurality of PMOSs 10 as second MOS transistors are formed in the second region on the main surface of the N-type substrate (substrate) 1, and the main of the P well 2 as the first region is formed. A plurality of NMOSs 20, which are first transistors, are formed on the surface. The PMOSs 10 are arranged in the horizontal direction as viewed from the main surface of the substrate 1 shown in FIG. 1, and the NMOSs 20 are arranged in the horizontal direction below these PMOSs 10.
[0025]
Each PMOS 10 includes a source 10S extending in the vertical direction with a constant width and connected to VCC, a drain 10D extending in parallel to the source 10S with a constant width and connected to the output terminal OUT, 10S and a gate 10G extending between the drain 10D and connected to the input terminal IN. Each NMOS 20 includes a source 20S extending in the vertical direction with a constant width and connected to VSS, and a drain 20D extending in parallel to face the source 20S with a constant width and connected to the output terminal OUT. The gate 20G extends between the source 20S and the drain 20D and is connected to the input terminal IN.
[0026]
A plurality of contacts 41 are arranged in series along the longitudinal direction (vertical direction) on the source 10S of each PMOS 10, and a plurality of contacts 41 are also arranged along the longitudinal direction (vertical direction) on the drain 10D. The contacts 42 are arranged in series. Similarly, a plurality of contacts 51 are arranged in series along the longitudinal direction (longitudinal direction) on the source 20S of each NMOS 20 and further along the longitudinal direction (vertical direction) on the drain 20D. A plurality of contacts 52 are arranged in series.
[0027]
In order to add the parasitic resistances R3 and R4 of FIG. 4 as resistance means, the number of contacts 41 on the source 10S side of the PMOS 10 is made smaller than the number of contacts 42 on the drain 10D side. Thus, the contact resistance component of the source 10S portion is increased. Similarly, the number of contacts 51 on the source 20S side of the NMOS 20 is made smaller than the number of contacts 52 on the drain 20D side to increase the contact resistance component of the source 20S portion. Thereby, the parasitic resistances R3 and R4 can be easily added, and the latch-up can be accurately reduced.
[0028]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. Examples of such modifications include the following.
[0029]
(A) In the above embodiment, the parasitic resistances R3 and R4 are respectively formed on the sources 10S and 20S side of the PMOS 10 and the NMOS 20, but even if the parasitic resistance R3 or R4 is formed on either of them, the output terminal OUT Latch-up can be reduced depending on the polarity of the trigger voltage applied to.
[0030]
(B) In the above embodiment, the CMOS type integrated circuit formed on the N type substrate 1 has been described. However, the CMOS type integrated circuit formed on the P type substrate has the same operation as the above embodiment. The effect is obtained.
[0031]
【The invention's effect】
As described above in detail, according to the first to fourth inventions, the number of contacts on the source side of the MOS transistor is made smaller than the number of contacts on the drain side, and a high voltage ( Since a resistance component (resistance means) is added in series to the emitter portion of the bipolar transistor formed parasitically between VCC) and the low voltage (VSS), the bipolar at the time of applying the trigger voltage by the resistance component (resistance means). Transition of the transistor to the on state is suppressed, and the occurrence of latch-up can be accurately reduced with a simple structure.
[Brief description of the drawings]
FIG. 1 is a schematic layout diagram of a CMOS output circuit showing an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of a conventional CMOS output circuit.
3 is a circuit diagram showing a connection relationship between a parasitic bipolar transistor and a resistor in the CMOS output circuit shown in FIG. 2;
FIG. 4 is a circuit diagram of a connection relationship between a parasitic bipolar transistor and a resistor in a CMOS output circuit showing the principle of the embodiment of the present invention.
[Explanation of symbols]
1 N-type substrate 2 P well 10 PMOS
10D, 20D Drain 10G, 20G Gate 10S, 20S Source 20 NMOS
T1, T3 PNP transistor T2, T4 NPN transistor R1, R3, R4 Parasitic resistance R2 N-type substrate resistance IN Input terminal OUT Output terminal VCC High level power supply VSS Low level power supply 41, 42, 51, 52 Contacts

Claims (4)

A CMOS output circuit that operates by being supplied with a high voltage and a low voltage,
A substrate having a main surface;
A source of a first conductivity type formed in a first region of the main surface of the substrate and supplied with one of the high voltage and the low voltage; and a drain of the first conductivity type connected to an output terminal. A first MOS transistor;
A second conductivity type source formed in a second region of the main surface of the substrate and supplied with the other of the higher voltage or the lower voltage, and a drain of the second conductivity type connected to the output terminal; and a second MOS transistor having,
The first MOS transistor is formed by making the number of contacts with the plurality of sources arranged in series less than the number of contacts with the plurality of drains arranged in series of the first MOS transistors. Resistance means connected in series to the source of the first MOS transistor;
CMOS output circuit, characterized in that it comprises a. A CMOS output circuit that operates by being supplied with a high voltage and a low voltage,
A substrate having a main surface;
A source of a first conductivity type formed in a first region of the main surface of the substrate and supplied with one of the high voltage and the low voltage; and a drain of the first conductivity type connected to an output terminal. A first MOS transistor;
A second conductivity type source formed in a second region of the main surface of the substrate and supplied with the other of the higher voltage or the lower voltage, and a drain of the second conductivity type connected to the output terminal; A second MOS transistor having
The second MOS transistor is formed by making the number of contacts with the plurality of sources arranged in series smaller than the number of contacts with the plurality of drains arranged in series of the second MOS transistors. Resistance means connected in series to the source of the second MOS transistor;
A CMOS output circuit comprising: A CMOS output circuit that operates by being supplied with a high voltage and a low voltage,
A substrate having a main surface;
A first conductivity type formed in a first region of the main surface of the substrate, extending in a predetermined direction with a constant width when viewed from the main surface of the substrate, and supplied with one of the high voltage or the low voltage A source; a drain of the first conductivity type extending in parallel opposite the source of the first conductivity type with a constant width as viewed from the main surface of the substrate; and the first conductivity type connected to an output terminal; A first MOS transistor having a first gate extending between the source of the type and the drain of the first conductivity type and connected to the input terminal;
A second conductivity type formed in a second region of the main surface of the substrate, extending in the predetermined direction with a constant width when viewed from the main surface of the substrate, and supplied with the other of the high voltage or the low voltage The second conductivity type drain connected in parallel to the source of the second conductivity type and connected to the output terminal with a constant width as viewed from the main surface of the substrate; A second MOS transistor having a second conductivity type and a second gate extending between the second conductivity type source and the second conductivity type drain and connected to the input terminal ;
The number of contacts arranged in series along the longitudinal direction on the source of the first MOS transistor is equal to the number of contacts arranged in series along the longitudinal direction on the drain of the first MOS transistor. Resistance means connected in series to the source of the first MOS transistor formed by reducing the number of contacts arranged ,
CMOS output circuit, characterized in that it comprises a. A CMOS output circuit that operates by being supplied with a high voltage and a low voltage,
A substrate having a main surface;
A first conductivity type formed in a first region of the main surface of the substrate, extending in a predetermined direction with a constant width when viewed from the main surface of the substrate, and supplied with one of the high voltage or the low voltage A source; a drain of the first conductivity type extending in parallel opposite the source of the first conductivity type with a constant width as viewed from the main surface of the substrate; and the first conductivity type connected to an output terminal; A first MOS transistor having a first gate extending between the source of the type and the drain of the first conductivity type and connected to the input terminal;
A second conductivity type formed in a second region of the main surface of the substrate, extending in the predetermined direction with a constant width when viewed from the main surface of the substrate, and supplied with the other of the high voltage or the low voltage The second conductivity type drain connected in parallel to the source of the second conductivity type and connected to the output terminal with a constant width as viewed from the main surface of the substrate; A second MOS transistor having a second conductivity type and a second gate extending between the second conductivity type source and the second conductivity type drain and connected to the input terminal;
A plurality of contacts arranged in series along the longitudinal direction on the source of the second MOS transistor are arranged in series along the longitudinal direction on the drain of the second MOS transistor. Resistance means connected in series to the source of the second MOS transistor formed by reducing the number of contacts arranged ,
A CMOS output circuit comprising:

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