JPS62115742A - Adjusting method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To cut a fuse stably without latching up a semiconductor integrated circuit by applying fuse cutting voltage, where a parasitic diode is brought to a non-conductive state, to a regulating terminal. CONSTITUTION:P channel MOS transistors 2 and 3 connected at a positive power terminal 1 constitute a current mirror circuit, and the threshold voltage of the P channel MOS transistor 2 and currents determined by the resistance value of a resistor 4 flow through the P channel MOS transistor 2. The P channel MOS transistor 3 functions as the current mirror circuit, and approximately the same currents flow through the transistor 3 when the size of channel regions in the transistors 2 and 3 is equalized. Since the resistance value of a fuse 6 takes approximately several hundred ohm even when it is large at the most, the voltage of a regulating terminal 5 is brought to approximately grounding potential. Voltage lower than grounding potential is applied to the regulating terminal 5 to cut the fuse 6. Accordingly, the regulating terminal 5 rises up to approximately positive supply voltage because the P channel MOS transistor 3 is conducted, and the fan-in level of an inverter 8 reaches a high level.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for adjusting a semiconductor integrated circuit, and in particular, when adjusting a semiconductor integrated circuit using a fuse, the polarity of the voltage applied to the adjustment terminal for cutting the fuse is adjusted to the semiconductor integrated circuit. The present invention relates to a method for adjusting a semiconductor integrated circuit, which is determined by considering the withstand voltage of MOS transistors constituting the circuit.

[Conventional technology]

Conventionally, in order to achieve a reference voltage with high accuracy in semiconductor integrated circuits, multiple sets of high resistance elements and heaters were prepared, pressure was selectively applied to the fuses from adjustment terminals, and the fuses were cut by transient high temperatures. Accordingly, it has been common to adjust semiconductor integrated circuits. In this adjustment method, for example, a high resistance element whose first terminal is connected to a positive power supply, a second terminal of the high resistance element is connected to the first terminal of a fuse and an adjustment terminal to which the entire adjustment voltage is applied, and the second terminal of the fuse is Ground the terminal. With this configuration, the connection point between the second terminal of the high-resistance element and the first terminal of the fuse before cutting the fuse is connected because the resistance value of the fuse is small compared to the resistance value of the high-resistance element. , is determined to be a logical low level.

On the other hand, in an adjustment circuit realized by such a high resistance element and a fuse, after the fuse is cut, the voltage at the connection point is pulled up to the voltage of the positive power supply via the high resistance element. Therefore, the connection point is determined to be at a logic high level.

An example of such a high resistance element connected to the positive power supply side is a P element whose source terminal is connected to the positive power supply, whose gate terminal is connected to an arbitrary DC voltage value, and whose drain terminal is connected to a fuse. Channel MO8) It is often realized by a transistor.

An example of a high resistance element connected to the ground side is to use an N-channel MOS transistor whose source terminal is connected to the ground, whose gate terminal is connected to an arbitrary DC voltage value, and whose drain terminal is connected to a fuse. Common.

[Problem that the invention seeks to solve]

With the conventional adjustment method described above, the voltage value applied to the % adjustment terminal as the power supply voltage decreases to cope with the miniaturization of the gate length of the MOS) transistor and the resulting decrease in the withstand voltage between the source and drain of the MOS) transistor. There are restrictions on

For example, if a high-resistance element is implemented using a P-channel MO8 transistor on the positive power supply voltage, the voltage value that can be applied to the adjustment terminal should be greater than or equal to the voltage value of the positive power supply in order to avoid abnormal operation such as 2. Have difficulty.

On the other hand, the cutting voltage of the fuse needs to be set to a value that has sufficient margin for when the semiconductor integrated circuit is powered on or cut off, and needs to be maintained at about 5 V to IOV, for example.

In this way, considering the reduction in power supply voltage due to miniaturization of the gate length of MOS transistors and the need to secure fuse-cutting voltage, conventional semiconductor integrated circuit adjustment methods have problems such as inability to perform adjustment or a decrease in adjustment yield. there were.

[Means for solving problems]

The method for adjusting a semiconductor integrated circuit of the present invention includes connecting a first terminal of a high resistance element to a first power supply, and applying a voltage to the other terminal of the high resistance element to cut off the first terminal of the fuse and the heater. Connect the adjustment terminal for
When the voltage value of the second power supply is smaller than the voltage value of the first power supply, the fuse is blown by connecting the terminal of the power supply to the second power supply, and applying a voltage smaller than the voltage value of the second power supply to the adjustment terminal. When the voltage value of the second power supply is larger than the voltage value of the first power supply, the heater is cut off by applying a voltage larger than the voltage value of the first power supply to the adjustment terminal. .

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of an equivalent circuit of a first embodiment to which the method for adjusting a semiconductor integrated circuit according to the present invention is applied. P channel MOS transistors 2 and 3 connected to the positive power supply terminal 1 constitute a current mirror circuit, and the P channel MOS transistors 2 and 3 connected to the positive power supply terminal 1 constitute a current mirror circuit.
8) A current determined by the threshold voltage of transistor 2 and the resistance value of resistor 4 flows through P-channel MOS transistor 2.

P-channel MO8) Transistor 3 operates as a current mirror circuit, and if the dimensions of the channel regions of transistors 2 and 3 are the same, approximately the same current flows.

Since the resistance value of the fuse 6 is at most several hundred ohms, the voltage at the adjustment terminal 5 is approximately at ground potential. Therefore, the logic input level of the inverter 8 whose input is connected to the adjustment terminal 5 becomes a low level.

A voltage lower than the ground potential is applied to the adjustment terminal 5 to disconnect the fuse 6. Then, since the P-channel MOS transistor 3 is conductive, the adjustment terminal 5 rises almost to the positive power supply voltage, and the logic input level of the inverter 8 becomes high level. In this way, in order to cut the fuse 6 by applying a voltage below the ground potential (for example, -10■) to the adjustment terminal 5, if the positive power supply voltage is set to 5■, the withstand voltage between the drain and source of the P-channel MOS transistor 3 is 15V. It is necessary to make the train
Although the source-to-source breakdown voltage is predetermined and the gate length is set thick, it is sufficient to use two P-channel MOS transistors in which the P-channel MOS transistor 3 has a vertical product with a common gate electrode.

When a positive voltage (for example, 1oV) is applied to the adjustment terminal 5, the parasitic diode 7 existing between the transistor 3 and the positive power supply terminal 1 becomes conductive, causing the semiconductor integrated circuit to latch up. Since the diode is conductive, it is in a low impedance state, resulting in inconveniences such as the fuse 6 not being able to be cut. In order to avoid such inconveniences, it is effective to cut off the fuse 6 by applying a voltage below the ground potential to the adjustment terminal 5 as in the first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an equivalent circuit of a second embodiment to which the method for adjusting a semiconductor integrated circuit according to the present invention is applied. In FIG. 2, the same parts as in FIG. 1 are designated by the same numbers.

The difference between FIG. 2 and FIG. 1 is that the heater 6 has moved from the ground potential to the positive power supply terminal 1 side. Accordingly, the connection between the N-channel MOS transistors 12 and 13 constituting the current mirror circuit and the resistor 4 that determines the entire current has been changed.

Let us consider cutting the fuse 6 in the same way as in the first embodiment. i?
A positive voltage (for example, 15V) is applied to the J adjustment terminal 5 with respect to the positive power supply terminal 1 (for example, sV), and the IO voltage is applied to both ends of the fuse 6.
It will be cut by applying V. At this time, the drain-source voltage of the channel MOS transistor is 15V.
Therefore, the L dimension of the transistor is determined with consideration given to the withstand voltage, but it is necessary to use a vertically stacked structure of two N-channel MO8) transistors.

In the circuit shown in Fig. 2, if an attempt is made to disconnect the heater 6 by applying the voltage at the adjustment terminal 5 below the ground potential, a parasitic diode will be generated.
'17 may become conductive, causing the semiconductor integrated circuit to double-stir, or cutting the fuse 6 may cause the parasitic diode 17 to become conductive.

Note that the first and second embodiments of the present invention are merely examples, and any constant current source may be used as the high resistance element.

〔Effect of the invention〕

As explained above, the present invention provides a method for adjusting a semiconductor integrated circuit by applying a fuse cutting voltage to the adjustment terminal that makes the parasitic diode non-conductive, thereby preventing latch-up of the semiconductor integrated circuit and stabilizing the fuse. This has the effect that it can be disconnected quickly and that unnecessary fuses are not disconnected when the power is turned on and off.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of an equivalent circuit of the first embodiment of the present invention;
The figure is an explanatory diagram of an equivalent circuit of the second embodiment. 1... Positive power supply terminal, 2, 3... P channel MO8) 7 transistor, 4... Resistor, 5...
...Adjustment terminal, 6...Fuse, 7, 17. Parasitic diode 8...Inverter, 12.13...
・N channel Mth f Figure 82

Claims (2)

[Claims] (1) Connect the first terminal of the high resistance element to the first power supply,
A second terminal of the high resistance element is connected to an adjustment terminal and a first terminal of a fuse, the second terminal of the fuse is connected to a second power supply, and a voltage value of the second power supply is lower than the voltage value of the first power supply. When the voltage value of the power source is small, the fuse is cut by applying a voltage smaller than the voltage value of the second power source to the adjustment terminal, and the voltage value of the second power source is larger than the voltage value of the first power source. A method for adjusting a semiconductor integrated circuit, characterized in that the fuse is sometimes blown by applying a voltage larger than a voltage value of a first power source to the adjustment terminal. (2) The method for adjusting a semiconductor integrated circuit according to claim (1), characterized in that constant current source means constituted by a MOS transistor is used as the high resistance element.