JP2000236022A - Fuse trimming circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent high electric field from being applied to a gate oxide film even if a gate oxide film is thinned by fining of an IC, not by grounding electric potential of a gate electrode of an NMOS transistor which is a protection element but by arranging a fuse resistance and a resistance for voltage division in series. SOLUTION: A fuse trimming circuit comprises a trimming pad terminal 1, a fuse resistance 2 formed of polycrystalline silicon, a protection resistance 3, an NMOS transistor 4 which functions as a protection element for making a current flow, a division resistance to make a potential of the pad terminal 1 and an intermediate potential of a ground line 5 to be applied to a gate electrode of an NMOS transistor and a pull-up transistor 8 for deciding a level of an input circuit 7. Since a voltage obtained by performing voltage division for a voltage applied to the pad terminal 1 is supplied as a gate voltage of an NMOS transistor, a high voltage is not applied to a drain and accordingly high electric field is not also applied to a gate oxide film of the input circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an LCD controller I.
The present invention relates to a fuse trimming circuit of an IC that requires matching of an oscillation circuit or the like, such as C.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional fuse trimming circuit. In order to determine the level of the gate electrode of the input circuit 7, a fuse resistor 2 and a pull-up transistor 8 are used as basic components, and a protection resistor 3 for protecting the inverter from electrostatic damage and a protection NMOS transistor are used. Was. At this time, the gate electrode of the protection NMOS transistor 4 was connected to the ground line 5.

In a fuse trimming circuit, when a voltage is applied to a pad terminal to be trimmed, a current flows through a fuse resistor made of polycrystalline silicon or the like, and the current is generated in proportion to the power represented by resistance * current * current The fuse resistance was blown by heat and trimmed.

[0004]

Problems to be Solved by the Invention As the miniaturization of ICs progresses, the thickness of the gate oxide film becomes thinner, and the withstand voltage of the gate oxide film decreases. For example, in the case of an oxide film of 100 angstroms, an electric field of 10 MV / cm is applied at 10 V. The intrinsic breakdown electric field of the thermal oxide film is about 11 MV / cm
Therefore, if 11 V is applied, the element is destroyed. Further, even if the electric field does not reach the intrinsic breakdown electric field, the higher the electric field is applied, the more the tunnel current flows, so that the damage to the gate oxide film increases, which is a problem in reliability. The drain withstand voltage of the NMOS transistor 4, which is a protection element for flowing a current when static electricity is applied, decreases as the thickness of the gate oxide film becomes thinner.
Before the S transistor 4 released static electricity, a high electric field was applied to the gate oxide film of the inverter 7 and the inverter 7 was destroyed.

[0005] The process of flowing a current by the NMOS transistor as a protection element includes avalanche breakdown of a drain and a bipolar operation between a source, a substrate and a drain. NMO
When the gate electrode of the S transistor is grounded, the avalanche breakdown of the drain first, then the substrate current generated by the avalanche breakdown triggers the source, substrate,
A bipolar operation occurs between the drains and a large current flows. During the bipolar operation, only a low voltage is applied to the drain of the NMOS transistor. However, since the avalanche breakdown of the drain before entering the bipolar operation is usually 12 to 17 V, the voltage has applied to the gate oxide film of the input circuit.

[0006]

According to the present invention, the fuse resistance is blown by heat generated in proportion to the power. A resistor for voltage division is arranged in series so that the potential of the gate electrode of the NMOS transistor becomes an intermediate potential between the drain and the ground line.

Therefore, since a voltage obtained by dividing the voltage applied to the pad terminal is supplied as the gate voltage of the NMOS transistor, the substrate current increases due to channel hot carriers, and the source, substrate, and drain are connected without avalanche breakdown. A large current is allowed to flow in bipolar operation. As a result, a high voltage is not applied to the drain, and a high electric field is not applied to the gate oxide film of the input circuit 7. After blowing the fuse resistor, NMO
Since the gate voltage of the S transistor is fixed to the ground line, the NMOS transistor is normally off.

[0008]

(Embodiment 1) FIG. 1 shows an embodiment of the present invention. The embodiment shows a fuse trimming circuit provided on a P-type substrate. NMO functioning as a pad terminal 1 for trimming, a fuse resistor 2 made of polycrystalline silicon, a protection resistor 3 and a protection element for flowing a current.
It comprises a dividing resistor 6 for applying an intermediate potential between the pad terminal 1 and the ground line 5 to the gate electrodes of the S transistor 4 and the NMOS transistor, and a pull-up transistor 8 for determining the level of the input circuit 7. The following describes each element.

Here, a case where the input circuit 7 is an inverter will be described. The total resistance value of the fuse resistor 2 made of polycrystalline silicon is about 100Ω, but a constricted shape is preferable as shown in FIG. The substrate current that triggers the NMOS transistor to enter the bipolar operation varies depending on the drain structure, but it becomes the largest when the gate voltage is about 1/2 to 1/4 of the drain voltage.
The dividing resistor 6 made of polycrystalline silicon is preferably 100Ω or less. At this time, the time-division resistor 6 should avoid a shape in which current is concentrated as shown in FIG. Here, it is sufficient that the fuse resistor 2 is easier to concentrate current and is more easily blown than the split resistor 6.

In this embodiment, the dividing resistor 6 and the fuse resistor 2
Has been described as polycrystalline silicon, but a laminated film of a silicide film such as WSi and a polycrystalline silicon film or a metal film may be used. The protection resistor 3 may be about 1 kΩ. As a guide, the NMOS transistor 4 acting as a protection element has a transistor width of about 400 μm and a channel length of about 1.0 μm, but these sizes have the ability to drive about 200 mA of current when the transistor is in bipolar operation, and It is good if it does not reach.

Next, the operation at the time of trimming (cutting the fuse resistor) will be described. When a voltage is applied to the pad terminal 1, a current flows to the ground line via the fuse resistor 2 and the split resistor 6. Usually, a voltage pulse of 50 to 100 msec is applied. The potential of the gate electrode of the NMOS transistor 4 becomes an intermediate potential determined by the resistance division ratio between the voltage of the pad terminal and the voltage of the ground line 5, and a substrate current is generated by channel hot carriers to enter a bipolar operation. FIG. 3 shows the process of entering the bipolar operation. In FIG. 3, point A indicates the voltage at which the snapback voltage is entered, and point B indicates the voltage after entering the bipolar operation. The curve in FIG. 3,
Represents the case where the resistance ratio between the fuse resistor 2 and the split resistor 6 is changed. Is NMOS without split resistor 6
14-17 V for transistors. When the value of the dividing resistor 6 is increased, the curve moves in the direction from the beginning, and the snapback voltage at the point A decreases. At this time, the voltage at point B hardly changes.

After the fuse resistor 2 is cut, the gate electrode of the NMOS transistor is fixed to the ground line.
Since the S transistor has already entered the bipolar operation, the bipolar operation continues until the pulse applied to the pad terminal 7 ends. The gate oxide film of the input circuit 7 has a protective N
Before the MOS transistor enters the bipolar operation, the highest voltage is applied. However, the voltage is lower than the snapback voltage at the point A, and is substantially fixed to the voltage at the point B when the MOS transistor is in the bipolar operation. Since the snapback voltage at the point A can be controlled by the resistance ratio between the fuse resistor 2 and the dividing resistor 6, a point A that does not remain on the gate oxide film according to the thickness of the gate oxide film of the input circuit 7 may be selected. . After the fuse resistor 2 is cut, the level of the gate of the input circuit 7 is determined by the pull-up transistor 8, and is fixed to the potential of the power supply line 9, that is, High.

Next, a case where the fuse resistor 2 is not cut will be described. Protection resistor 3, fuse resistor 2, and split resistor 6
The gate level of the input circuit 7 is determined by the sum of the sum and the drive capability of the pull-up transistor 8, but the size of the pull-up transistor 8 and the protection resistance are set so that the gate level of the input circuit 7 is fixed at Low. 3, the sum of the fuse resistor 2 and the split resistor 6 must be determined. If the fuse resistor 2 is not cut, the voltage of the power supply line 9 is divided into the gate electrode of the protection NMOS transistor 4 by the ratio of the on-resistance of the pull-up transistor 8, the protection resistor 3, the fuse resistor 2, and the division resistor 6. However, since the dividing resistor 6 is small, the leakage current of the protection NMOS transistor 4 is very small. If the threshold value of the protection NMOS transistor 4 is increased by ion implantation, the leak current can be further reduced. (Embodiment 2) FIG. 5 shows another embodiment of the present invention. As compared with the first embodiment, a transistor 12 for fixing the output of the input circuit and a transistor 13 for determining the initial value of the output of the input circuit are added instead of the pull-up transistor 8.

In the first embodiment, when the fuse 2 is not cut off, the pull-up transistor 8 is normally on. Therefore, a current is supplied between the power supply line 9 and the ground line 5 via the fuse resistor 2 and the split resistor 6. However, in this embodiment, when the fuse 2 is not cut, the input of the inverter as the input circuit 7 is fixed to Low, so that the transistor 13 for fixing the output of the input circuit is turned off, and the power supply line 9 and the ground are connected. No current flows between the lines 5 so that the consumption current does not increase. At this time, since the gate of the protection NMOS transistor 4 also has the same potential as the ground line, there is no fear of leakage current of the protection NMOS transistor 4.

[0015]

According to the present invention, a fuse trimming circuit in which a high electric field is not applied to the gate oxide film even if the gate oxide film becomes thin due to miniaturization of the IC can be constituted. In the present invention, a fuse trimming circuit on a P-type semiconductor substrate has been described, but an N-type substrate may of course be used.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional technique.

FIG. 3 is a diagram showing the dependence of the current-voltage flowing through the NMOS transistor during fuse trimming on the resistance ratio between the fuse resistance and the division resistance.

FIG. 4 is a plan view of a fuse resistor and a split resistor.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pad terminal 2 Fuse resistor 3 Protective resistor 4 Protective NMOS transistor 5 Ground line 6 Split resistor 7 Input circuit 8 Pull-up transistor 9 Power supply line 10 Polycrystalline silicon 11 Contact 12 Transistor for fixing output of input circuit 13 Input circuit Transistor that determines the initial value of the output

Claims (1)

[Claims] 1. A pad terminal for trimming provided on a P-type semiconductor substrate, a severable fuse resistor connecting one end to the pad terminal, and a ground wire connected to the other end of the fuse resistor. A protection resistor for connecting one end to the pad terminal; a drain connected to the other end of the protection resistor; a source grounded; and a gate electrode connecting the fuse resistor and the split resistor. A protection NMOS transistor coupled to the coupling portion; a pull-up transistor coupled to the protection resistor for hanging a power supply line for determining a level of a trimming terminal; and an input circuit having a gate electrode coupled to the protection resistor. A fuse trimming circuit comprising: