JPS5912625A - Logical circuit - Google Patents

Abstract

PURPOSE:To prevent an excessive current due to short-circuit of output, by detecting the short-circuit with the logical processing between the output and the input to an output circuit in the output circuit of PP drive for turning off the output. CONSTITUTION:The output circuit comprising MOSFETs 11, 12 is driven in the way of push-pull(PP) at an output transistor drive circuit 10. Further, an input signal of the FET11 and the output of the output circuit are inputted to an exclusive OR circuit 20. If a short-circuit takes place at the output terminal, two inputs of an OR20 are opposite in phase each other, its output goes to a high level and the short-circuit of output is to be detected. This high level signal inverts an FF comprising an NOR15 and an inverter 16 to turn on FETs 13, 14, then the FETs 11, 12 are turned off, allowing to prevent a short-circuit current. The excessive current due to the short-circuit of output is prevented in this way.

Description

[Detailed description of the invention] The present invention relates to an output circuit for a logic element.

When constructing a logic circuit using logic elements, it is common practice to commonly connect the inputs and outputs of a plurality of elements to reduce the amount of wiring. In such logic circuits, the output may be short-circuited to ground or the power supply due to a failure of commonly connected logic elements. In general, logic elements have a high output voltage of 2 when a certain amount of current is flowing according to the TTL standard.
．． It is designed to be able to output 4V or more and 0.4V or less as an output low voltage. Therefore, if the output is shorted, 10
A large current of 9 mA or more flows, causing destruction of the element or shortening of its life.

The present invention has been made in view of the above, and an object of the present invention is to prevent excessive current caused by short-circuiting of the output of a logic element. Conventionally,
As a means to prevent such excessive current, there has been a method of inserting a resistor in series with the output, but this resistor naturally has an effect even during normal operation, and is not preferable.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is characterized in that an output circuit is controlled by logic between an output signal of a logic element and an internal signal.1 An embodiment of the present invention will be described below with reference to FIG. In this example, we will discuss the case of an N-channel MOS transistor, but the same applies even if a P-channel transistor or a bipolar transistor is used.

MOS transistors 11 and 12 are connected in series, and 11 and 12 are connected in series.
The drain of 12 is connected to the power supply, the source of 12 is connected to the ground, and an output circuit is constructed in which the common connection point of 11 and 12 is used as an output terminal. 10 is an output drive circuit; 11.
Signals with mutually opposite phases are supplied to the 12 gates, and the output circuit is driven in push-pull mode. , 20 are exclusive ORs, and operate with the output terminal and the input signal to the transistor 11 as inputs. The non-OR 15 and the inverter 16 are cross-coupled to form a flip-flop, the output of the exclusive OR 20 is input, and the output of the inverter 16 drives transistors 13 and 14. transistor 13
．． 14 is connected between the output of the drive circuit 10 and the ground,
Controls the output transistor. transistor 18
is a 1°-order inverter whose load is a depressimine MOS transistor 17, whose gate is connected to the power supply to form a power source detection circuit, and which drives the transistor 19 whose drain is connected to the output of the exclusive OR 20. The circuit operation will be explained below. In this example, since an N-channel MOS transistor is used, the input signal to the output transistor 11 and the output are in phase. Therefore, during normal operation, the two inputs to exclusive OR 20 are always in phase and its output is kept at a low level. However, if the output end is shorted to the power supply or ground, the common-mode relationship is reversed, and 2
0 works. For example, if the output terminal is short-circuited to ground while the output is at a high level, the input to 11 will remain at high level, but the output terminal will become low level due to the short circuit, so the exclusive OR will not be applied. The two inputs are out of phase with each other, and the output is at a high level to detect a short circuit in the output. This high-level signal inverts the next-stage slip-flop composed of a non-OR and an inverter, turning on transistors 13 and 14, so output transistors 11 and 11.
12 is turned off and short-circuit current is prevented.1) The above is the basic operation, but the following points must be taken into consideration.

First, a short-circuit condition is determined. Although the basis of the present invention is to detect logical contradictions between the output and the output circuit drive signal, it is necessary to avoid responding to transient short-circuit conditions that occur during normal operation. During the transition period when the output changes from a high level to a low level or vice versa, there is always a delay in the response of the output to the output circuit drive signal, and during this time a condition similar to a short circuit occurs. In order to prevent this transient short circuit from being determined as a short circuit, the response speed of the detection circuit should be slowed down. The time during which a transient short circuit occurs corresponds to 9 hours for the rise and fall of the output, but this time is a fraction of the delay time or minimum operating cycle time of the entire logic circuit including the output circuit. .

Therefore, by setting the minimum signal to which the detection circuit responds to approximately the minimum cycle time, it is possible to easily configure a detection circuit that does not respond to transient short-circuit conditions during normal operation, but responds only to short-circuit conditions that are longer than the cycle time. can.

The next consideration is operation after a short is detected and the output transistor is turned off. When the output transistor is turned off, the logical contradiction between the drive signal and the output is resolved, so the detection circuit returns to the original state of turning on the output transistor. If this happens, the detection circuit will operate again and turn off the output transistor, causing an oscillation phenomenon. In order to prevent such a phenomenon, once a short circuit is detected and activated, it is necessary to latch the state. In this case, it is appropriate to use a power source to release the latch.

This role is played by the flip-flop and transistors 17 and 1, which are composed of a non-OR and an inverter.
This is a power supply detection circuit configured with 8.19.

Since the slip-flop has a configuration with a non-logical OR input, let us consider the case where both inputs are stable at low levels as an initial state.In this state, the input from the short circuit detection circuit changes to high level. The clip-flop then inverts and the feedback input from the inverter to the non-OR becomes high, again establishing a stable state. Thereafter, even if the input from the detection circuit goes low, the flip-flop can perform the latch function without inverting because one of the non-OR inputs is high.

A flip-flop is reset by turning off the power. In general, flip-flops have two stable states, so it is uncertain which stable state they are in immediately after power is turned on. It is easy to determine the state immediately after the power is turned on by having a The flip-flop can be reset using the power supply by controlling the voltage to remain low until it rises to a certain extent.

The inverter made up of transistors 17 and 18 is 18
Since the gate of the transistor is connected to the power supply, its output changes as shown in FIG. 2 as the power supply voltage increases. Therefore, one input of the flip-flop is kept at a low level until the power supply voltage rises to a certain extent by the transistor 19 which operates in response to this output, thereby satisfying the above condition.

FIG. 3 shows a second embodiment of the present invention, which differs from the first embodiment in that exclusive non-OR is used for short circuit detection.
Therefore, the input signal to the detection circuit is the output signal and the input signal to the output transistor 12, but the other operations are exactly the same as in the first embodiment.

As described above, according to the present invention, a short circuit is detected based on the logic between the output and the input signal to the output circuit, and the output is turned off to prevent the output short circuit current and prevent the destruction or shortening of the life of the logic element. It is possible

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention, and FIG. 2 shows characteristics of a power supply detection circuit composed of MOS transistors 17 and 18. FIG. 3 shows a second embodiment of the invention. 10...Output transistor drive circuit, 11.1
2゜13, 14.18.19... Enhancement men) WMO8 transistor, 17... Depletion type MO8) transistor, 15... Non-OR, 16... ... Inverter, 20 ... Exclusive [13 logical OR, 21 ... Exclusive non-OR. Figure 1 #2 Electric flash source voltage Figure 3

Claims (3)

[Claims] (1) Output control characterized in that in a push-pull driven output circuit, a short circuit in the output is detected by performing logic between the output signal and the input signal to the output circuit, and the output circuit is controlled. logic circuit. (2) The output control logic circuit according to claim 1, wherein the short circuit detection output is latched. (3) The output control logic circuit according to claim 2, wherein the latch is released using a power source.