JPS59125789A - Automatic performer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an automatic performance device that has a storage means for storing musical tone information, reads out the musical tone information from the storage means, and performs a self-playing performance.

[Prior art]

9. In the case of a conventional electronic musical instrument having a storage means, a plurality of keys are operated and musical tone information corresponding to the plurality of keys is recorded in the storage means.9. An electronic musical instrument that reads out the information and simultaneously reproduces and emits the plurality of pieces of musical tone information has not yet been put to practical use.

Furthermore, the Shigeko musical instrument, which allows multi-recording in a disotal manner, has not yet been put to practical use.

[Purpose of the invention]

To provide an automatic performance device capable of recording and reproducing notes such as chords by simple input operations.

Furthermore, it is an object of the present invention to provide an automatic performance device that allows multi-recording with simple input operations.

[Key points of the invention]

When storing musical tone information for the number of chords to be sounded simultaneously in the storage means, for example, recording and playback of chords can be made possible by recording musical tone information including time data indicating that the sounding timings are simultaneous. It is an automatic performance device.

Further, the automatic performance device is such that the storage means is provided with a modulus of areas, and musical tone information from a plurality of areas outside the area is transferred and stored in one of the areas.

The other point is to read out the musical tone information stored in the ifr'' means, perform further performance while listening to the musical tone generated based on this musical tone information, and memorize new musical tone information. This is an automatic performance device that enables so-called multi-event recording.

[+14] Embodiments of this invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the overall configuration of a musical instrument equipped with an automatic performance function. The 8-board switch section 1 is equipped with multiple keys and 41 switches for various effects such as material color, vibrato, sustain, stereo sound image localization, normal rhythm, fill-in rhythm, automatic accompaniment, etc. Furthermore, a switch for automatic performance is provided. For example, reset switch LA, IJ birth switch 1;B.

These functions will be described later. Then, the CPU (central processing unit w) 2 (well, periodically outputs the key signal L through the pass line B1 to switch the keyboard switch section 1,
In addition, in response to this, the keyboard switch unit 1 outputs the output from the key and the switch (g) and sends it to the CPU 2 via the pass line B2.
For example, the musical tone generation section 3 is given musical tone generation command information via the path line B3, and is caused to generate musical tone signals for melody and automatic accompaniment, and is then delivered to the localization control section 4. In addition, C P TJ 21'I"i"i"i" information according to the sound image localization information preset in the RAM (Random Access Memory) 5, which will be described later, is transferred to the pass line B4.
output to the left and right speakers 6 to set the sound image localization for the musical tone signal to the image localization control section 4.
A comparison signal is output to R16L, and a musical tone is emitted.

The RAM 5U:, C, P U 2 is controlled to output and write data in accordance with the address control information supplied to the theater storage unit 7 via the pass line B5. And between CPU2 and RAM5, pass line B
Data is exchanged via 6. In this case, RAM
5 includes musical tone information (hereinafter referred to as melody information for convenience) indicating the pitch, duration, and rest of the song, as well as various information such as tone, vibrato, sustain, sound image localization, fill-in rhythm on/off, etc. Performance information for obtaining effects is stored in different areas. And address counter analysis 7
is provided with independent address counters for each of the melody information and performance musical tone information, so that during automatic performance, the melody information and performance information are updated according to the progress of the melody. , JL is output in parallel and at the same time, so that automatic performance can be performed.In this embodiment, three areas are provided for storing melody information.

The recording section 8 receives the time i and i1 information (data D7=DO) given by the CPU 2 through the pass line B7, and the time information (7''-ta TD7 to TDO) given from the playback section 9 via the pass line Bll. Create a ``Munama Kaihiki'' that represents the note length from ``・(D Quest 7 ~ IO), and set the path line B.
8 to the CPU 2, and is stored in the RAM 5 as the melody information or performance information.

The playback section 9 transfers information according to the melody information and performance information outputted from the RAM 5 during playback to the CPU.
From 2 to pass line B
The time information is provided to the CPU 2 via the IO, and as described above, during recording, time information is provided to the recording section 8. Note that the CPU 2 is a processor that controls all operations of this electronic musical instrument, and the details thereof will be omitted. The recording section 38 and the reproduction section 9 are provided with four identical circuits, each of which operates independently.

The mixbutane section 10 is a circuit that performs a process of synthesizing certain sound information stored in different areas (also referred to as different channels) in the RAM 5 and writing it into one channel. . In that case, mix game 1
27 part 10 and CPU 21M:I, pass line B
12 and B13, necessary data is exchanged, the details of which will be described later. Note that when inputting the combined data obtained by the mix main processing of the mix button section 10 to any channel of RA, ', i 5 O, that channel is An address register (referred to as ADRM) is provided in the address counter section 7.

Next, I will explain the combination of 3i7 and t÷;S8 using E-2-1. PR Lunch]
(Up/down sword counter g-chotsu group, which will be described later in 9,
Katana Bu- [4D7 ~ Transfer case as TDO
The fidget is latched when the CPU 2 outputs the signal LAT. 1. Temporary P in the playback section]
When the rewinding force is applied by operating the reverse switch IB during the raw motion or the bamboo stopper, and then when recording starts anew, the CI of PR Ship 11 is used.
The output data of the full adder at that time is sent via the CPU 2 to the full adder (to be described later) in the playback unit 8 (and conversely, the output data of the full adder at that time is sent to the transfer target group 13 via the CPU 2 as L data D7 to Do). Furthermore, PR launch] 1 Heratsuchi will be carried out.

Then, the data latched to the PR latch 11 is transferred to the subtracter 1.
It is applied to the B input terminals (87 to BO) of No. 4. Further, the data TD7 to TDO are input to the A input terminals (A7 to AO) of the subtracter 14.

Then, the subtracter 14 subtracts the input data of the B input terminal and child from the input data of the A input terminal, and the resultant data is
(2) Send 0 to the RAM 5 via the CPU 2 and store it therein.

These data ■7 to ■0 indicate time data giving key-on time and key-off time in the case of melody information,
On the other hand, in the case of the performance information of an effect, it is time data indicating the period during which the effect occurs. The transfer dart group 12 has the signal CH output from the CPU 2 applied to its dirt via the inverter 15e, and the transfer dart group 13 has the signal CH directly applied to its dirt to control the darts. Ru.

Next, the configuration of the reproducing section 9 will be explained with reference to FIG. The UP/DOWN counter 1 is an 8-bit counter, and after being cleared by the CPU 2 outputting the clear signal CLR at the start of recording or playback,
A counting operation is performed to count clocks based on the signal output by the tempo oscillator 18.

In the drum, the frequency of the oscillation w1 of the tempo oscillator J8 is variable by a tempo volume 19, and the output of the tempo oscillator 18 is input to an AND gate 20. At the end of this AND gate 2o, the W switch of the tempo stop switch ESW is activated to perform gate control, and the output of the AND gate 20 is a T-type flip-front 7°. 21 and transfer gate 23. The set output of Furiragfron 7”21 is as follows:
T-type flip float f22 and transfer case
-) Enter in 24. Furthermore, the cent output of the free lag front f22 is input to the transformer 7 arcade 25.

Each case of the transfer dart 23, 24, and 25 is equipped with a tempo acceleration switch C8W, a normal switch Fsw, and a slow tempo switch DSW, each consisting of a double lock type switch in which only one is in the on state. Each output is applied and dart controlled. Then, each output of each transfer gate 23, 24, 25 is counted as the clock by the UP/aown counter 17.The flip-flops 21, 22 form a dividing circuit, and the tear i'&R For the output of 'r=18, each output of the flip-flops 21 and 22 has a frequency of 1/2.1/4.

The up-power operation and down-count operation of the amplifier counter 17 are controlled by the flip-flop 2, respectively.
This is done by the set output signal UPDWN of 6. That is, the set input terminal S1 and the reset input terminal R of the flip-flop 26 are connected to a forward switch B, SW, which is a double lock type switch, and a reverse switch ASW (same as the reverse switch IB in FIG. 1). Output is input.

Each bit output of the UP/down counter 17 is converted to a corresponding exclusive or dirt 27. In addition to inputting data to each end of f~27°0, recording capital 8 is input as data TD7~TDO.
sent to. In addition, the output of each corresponding bit of the 8-bit weighing NE switch 28 is input to each other end of the exclusive or good 27≠ to 2 information. and exclusive oagu)
The outputs of 27' to 27 and Q are input to the NOR dart 29, and the output of the NOR gate 29 is sent to the CPU as a match signal.
2. That is, exclusive ore number 27Z~2
7F and Noah Gate 29 form a coincidence.

The front 81'' NE latch 28 latches the addition or deenergization result data from the sl:I side terminals S7 to So of the full adder 30 when the CPU 2 outputs the latch clock. When the latch 28 is dead 1 and the articulation operation and playback operation are started, it is cleared by applying the clear signal CLR output from the CPU 2. latte 2
The false data of 8 is returned via the transformer 7 argument group 31 and inputted. In addition, the outputs of the exclusive OR quotes 3277 to 32ρ are input to the 13 input terminals B7 to BO, and the AND gate 3 is input to the carry input terminal CIN.
3 output is Impark 34, Transformer 7 Argut 35
I am inputting it through. Exclusive ORGATE 32z~
After the time data from the PR latch 11 in the recording section 8 is rewound during playback, it is input to each end of 32oQ in response to a key operation when performing a new recording operation for correction. The output of the AND gate 33 is applied to each other end of the transformer 7 through an inverter 34 and a transformer 7 output 35.

The set output of the flip-flop f26 and the signal R output from the CPU are input to the AND gate 33.

This signal R is normally output as 1'', and is temporarily output as 0'' when the recording is stopped. The output of the AND gate 33 is then sent to the CPU 2. Furthermore, the transformer 7 art group 31 and the transfer gate 35 are gate-controlled by the signal CHR output from the CPU 2, but this signal CHR is temporarily output from the CPU 2 as 0'' when making corrections during recording. Furthermore, the latch data of the NE latch output from the transfer gate group 31 is sent to the PR launch 11 when data is modified during reproduction.

Next, referring to FIG. 9, the specific configuration of the mixdown section jO will be explained. Counter (also abbreviated as CNT) 4] is used for mixdown 11. CPU2 when the system opens
After being cleared by the clear signal CLR outputted by the CPU 2, the +l signal outputted by the CPU 2 is inputted as in l1V1 to execute a number of operations. Therefore, the capacity is 8 bits, and the i-number output is input as time data to the input terminal of the coincidence circuit section 420 and the A input terminal A7 of the subtractor 43.
~AO1 Latte (also abbreviated as LASTT) 44 LI
Input to input terminals LI7 to LIO, respectively. The latch data of the latch 44 is applied to the B input terminals 87 to BO of the subtracter 43 via the L output pair ' and the children L7 to LO. The subtracter 43 subtracts the input data to the B input terminal from the input data to the A input terminal with respect to -, and outputs the difference from the time data 0 output terminals 07 to OO to the RAM.
A specified channel in S can be interpreted as one of the composite ports.

The input terminal of the adder 4.5 is RA, and the time data from the two channels to be mixed down is read out and applied to the B input terminal of the adder 45. Each input node has a latch (also called NEXTI) for one of the two channels.
B8) 46 latches time data size or 4t
When the latch (also abbreviated as NEXT2) 47 for the change on the h side is launched, [one key and one data are inputted respectively. The adder 45 straddles the input data to the A input terminal and the input data to the B input terminal, and
The input data to the child are added together, and the resultant data is output as new data from the D output pair or the E output terminal, respectively, and the latch 46 is latched. In addition, lunch 46.47 each, CI) U2
The latch operation is performed at each output of the signals LAI and Li2. At the beginning of the sweet mixdown process, the clear signals C1 and H output from the CPU 2
The latch data of the latch 46.47 is also cleared along with the callan 741 by the match circuit section 42.
is applied to the B input terminal or C input terminal, respectively. Then, the matching circuit section 42 extracts matches and mismatches between the input data to the A input terminal and the input data to the B input terminal according to the Kekoha, outputs matching information E1, and sends it to the CPU 2. Matching or mismatching between the input data to the input terminal and the input data to the C input terminal is detected, and the match (i number E2 is outputted and sent to the CPU 2).

Next, the operation of recording and reproducing two songs with melody progressions shown in FIGS. 8(A) and 8(B) in the RAM 5 will be explained.

First, the case of recording will be explained. In this case, for example, the eighth
[i? 1 (The above-mentioned - melody information of Al is first recorded by key operation of the keyboard switch section 1. Then,
FIG. 3 is a flowchart explaining the recording operation of this melody information.

Note that the numbers 0 to ]7 in FIG. 8 indicate the counting output of the touch g2 counter 41.

Turn on the recording start switch (not shown) for the first channel (CHI). The output is then input to the CPU 2 via the pass line B2, and the CPU 2 accordingly performs the process of step RM, 1 of the flowchart of the third process. That is, the clear signal CL R is sent to the pass line B7.
, Bg, PR latch 1], N E latch 2
8. Clear the UP/down counters 17 respectively. Next, FIG. 8 (A) in the CPU 2 address register section 7
The melody information of the above-mentioned - will be included soon from 17AM5.
The address control information for setting the external initial address for the address callan l(-) for the inner al) 1 channel (Cf-II) is set by inputting it into the path line B5 (step RM2).Next CPU21a, buffer 1
' Output data NOP to B6, R, A, C of M5.
It is inserted into the first address (0 bud address) of I-I 1. FIG. 4 schematically shows the storage state. This data N0P (NO0PERATION) is a gutter of 161 lines of rests that do not produce musical tones.

The CPU 2 increments the address counter (hereinafter simply referred to as the address register) of the address register section 7 by 1 in step RM4, and sets address 1. Next, a process of determining whether or not the reset switch IA has been turned on is performed in step RM5.

This reset switch IA is a switch that is turned on when performing recording correction. When turned on, the process returns to step RMI and is set to the initial state. On the other hand,
When the end key ID is finally turned on, the process advances to step 7'RM6, and it is determined whether the end key ID has been turned on. This end key ID is a switch that is turned on at the end of inputting melody information to write an end code at the end of the melody information input to RAM 5. Therefore, when the end key ID is turned on ( Y rY
EsJ), proceed to step RM7 and perform the above-mentioned process.
Processing is executed. However, the end key ID is rarely turned on now, so proceed to step RM8.
A process for determining whether the reverse switch IB (reverse switch ASW) is turned on is executed. When it is turned on, the process of moving to the recording standby state in step RM9 is executed, but this process will be discussed in detail later. Then, of course, the reverse switch IB is turned on, and the process proceeds to step RM10, where it is determined whether or not the key has been operated. Then, until the two keys of the two first tones of the melody (pitch 03, C3', and 4) of the melody shown in Figure 8 (A) are turned on at the same time as the recording start switch, the chord melody starts playing. During step RMIO1R
M5, RM6, RM8, RM10, . . . are repeated. When the R3 and C3 keys are turned on at the same time, step RMIIK proceeds to determine whether the key is depressed or released.Since the key is depressed, the process proceeds to step RM12, where the CPU 2 first selects the bass tone. In order to indicate that this is the key code and key press data of pitch 03 on the side, musical tone information is calculated by adding data "0" to the MSB (most significant pit) of the key code. Then, it is given to the musical tone creation section 3 via the pass line B3, and the speaker 6R,
Sound emission starts from 6L (step 0RM13). Next, the process proceeds to step RM16, where the CPU 2 sets the signal CH to 0''.
Transfer gate group during normal operation]
2 is kept open at all times, and transfer gate group 13 is kept open at all times.
is kept closed at all times. Therefore, after clearing Stella 7' RM1 as described above in Hayabusa 9, the clock of the set tempo is input and counting operation is started. If set to 1, an up-count operation is in progress or an up-count operation is already in progress.6
1st count output (time data) is data TD7~TDO
as pass line Bll,) transfer gate group 1
PR latch]1 and the A input terminal -\ of the subtracter 14 are inputted through the PR latch]1 and the A input terminal -\ of the subtracter 14. Next, the process of step RM17 is executed, and the signal LA is sent to the CPU2 PR latch 11.
T is applied, the time data being input at that time is latched into the PR latch II, and the latched data is thereafter held and applied to the B input terminal of the subtracter 14. Next, the process proceeds to step RM18, where the subtracter 14 executes an operation to subtract the input data to the B input terminal from the input data to the A input terminal, so that the input data to both input terminals have the same value. Adashi, Shitatata and Yuuga data at that time■
7~■0 is "0" and is stored in the front SR1 address of RAM5. The next address register is incremented by 1 and set to address 2 (step RM19), and this RAM
The key press code already calculated for No. 502 Fya, that is,
The key code (R3) and the key press data (rONJ l are entered (step RM20). Then, the at l/thread raster is increased by +1 and address 3 is set (step RM2).
), the process returns to step RM5.

Next, Stella f, RM5, RM6, RM8, M10
- Processing for the key of pitch C3f' which was turned on at the same time by each process of RM13, RM16 - RM21 is executed in the same way, time data rOJ is written as 1 in address 3 of CHI in RAM5, and time data rOJ is written as 1 in address 4 of CHI in RAM5. The key code (C3If) and key press data (rONJ) are written. The address register is then set to address 5, and the process returns to step RM5. Thus, two musical tones of pitch 03 and C34 are emitted simultaneously as a chord.

Next, when it is determined in step RMIO via Stella fRM5, RM6, and R combination jT8 that the key is released at pitch C3f, the process proceeds to step RM]4 and the previous step e pitch C3 is determined.
In order to indicate that it is key code 1 of f and key release data, execute the process of adding data [ ] to the MSB of the key code. key release code. Then, it is sent to the musical tone generator 1/section 3, whereby the musical tone of pitch 03 is muted (step RM15). Next, when proceeding to step RM]7 via the Stella 7° RMI 6, the PR clutch] is set to UP/d when the key is released.
, when the own counter is 7, the fill data is latched to 1, and can be held from now on, and $$p; B of 14
D is added to the input terminal. Then, -cs, n unit 14 is
4jIWe *1fift 'When making W, subtract the timing data from the previous key press of the pitch C3f key that was being input to the B and , the resulting data is stored, and the time data is stored in the RAM 5 (step RM18). In this case, as shown in FIG. 4, the time data at this time is "5". Then, through each process of steps RM19 and RM20, the first group key code is stored in address 6 of the RAM 5, as shown in FIG. And step RM21
With this, 7 aromatic areas can be specified, and the process returns to Rutep RM5.

Next, when the key of pitch B3 of the second musical tone is pressed, this is determined in step 0RMI O, and step fRM11 is pressed.
The process proceeds to step RM12 via step RM12, and the key press code is hung diagonally in the same manner as when the keys of double height C3 and C34 are operated.

Then, through the process of step RM13, creation and sound emission of a musical tone of υ pitch B3 is started. And step RM16, R
Through each process of M17 and RM18, the PR latch 11 latches the timer when the pitch B3 is pressed, and the subtracter 14 latches the time when the pitch E3 is pressed to the A input terminal. Data is obtained by subtracting the key release time data of the pitch C3t to the B input terminal from the key time data, and R
Written to the 7th incense area of AM5. In this case, as shown in FIG. 4, the one-voice data based on the result data is rlJ. Further, after the processing of the step fRM20 (d1 step RM21 adds fiR, the next 9# ground of AM5), and the process returns to step RM5.

Hereinafter, when the melody is performed at the intervals of j81 according to Fig. 8 (A) K, the same processing as above is performed,
C) i Below the 9@th ring of I, the Norodite T'l of the 3rd easy body and below is included. Then, when the last performance input is completed, turn on the end key ID and store the end code as the data after 147 of the RAI~I Henro Ruby emotion input.

Next, we will explain the process of step M9 when the reverse switch IB is turned on. This reverse switch IBI,'-QJ reversal switch ASW) is turned on when the key operation is close to 4:] when inputting the melody information, and the address register section 7 is set at the desired address 1''V. In this case, when the front perspective switch IB is turned on, the latch data of the PR launch 11 is transferred to the playback section 9 via the CPU 2. N of
It is latched by E clutch 8.

As described above, the 8th [E2i(
After taking note of the melody information in A), this figure 8 (A)
) while playing and encircling the melody information of
The melody information of the song is inserted into the second channel F (hereinafter referred to as CH2) of RAM5. Then, the recording process in this case is shown in Section 3 of the flowchart in Figure 1.
J! 1:) is the same as what I said to him, and as a result,
RAM 5 CB, 2 ICi4 In the state r4 as shown in the 7th shift, i8P! (Includes melody information of Bl song.

Therefore, with reference to the flowchart of the 6th part 1 (A) and (Bl), the town life processing operation of 1 melody in total of 71 ii is explained.

When the regeneration switch for CHI in RAM 5 is turned on, a clear signal is output through the processing of STETSU 7'SM1, and NE clutch 8 and UP/DO in Figure 5 are activated.
w n counter 1 hook: Both are cleared.

Next, the destination @ for the melody information of FIG.
The address is set to address Reno Stuff 7. and R.A.
Processing data "rNOP" (see FIG. 4) is read out from M5 and supplied to the CPU 2 (step 7'SM3).

Then, the address Renostaph is incremented by -1, and address 1 is set (step SM4). Then, the CPU 2 performs a process of determining whether the MSB of the data "NOP" is O" or 1" in step SM5, but in this case, since the data rNOPJ is similar to a rest, the process proceeds to step:7'SM7. A control signal is outputted to the musical tone creating section 3 at the key-off time, and execution of musical tone creation is prohibited.

Further, when the process proceeds to step SM8, the time data rOJ is read from address 1 of the RAM 5, and address register 7 is incremented by 1 to set address 2 (step 5M9).廿ta1
The time data r'0 from the address are taken and B of each group 30 is
Input to the input terminal and then latch the resulting data to NE clutch 8 (Stella 7'SM10% 5M11
). In this case, the 11WjA transfer switch BSW is turned on, and as a result, the flip 70 knob 26 is in the closed state, the AND gate 33 is opened, and the UP/DOWN count 17 is set to 2.・The horn count command is set.The signal R is normally ``1''.
Therefore, the output of the AND gate 33 is normally "1", and the signal is supplied to the CPU 2, and the output of the impark 34 is normally "0", and the output of the AND gate 33 is normally "1". -h 8 supplied to one end of each of 32'r' to 32il+ and the carry input terminal CIN of the full adder 30 via the transfer dart 35.
Note that the signal CHR is normally output as 1'',
Therefore, the transfer dart 35 and the transfer dart group 31 are normally open.

Therefore, in the step SMIO1SM11, the time data "0" is not inverted by the exclusive OR gates 327 to 320 and is sent directly to the full adder 300.
Input to the B input terminal. On the other hand, the output data of NE clutch 8 (8-bit all "O" data) is input to the A input terminal.
is input via the transfer dart group 31, and therefore, the full game result data at that time is often latched into the NE latch 28 as a "0".

Next, in the determination process of Stella 7'SM12, it is determined whether the coincidence signal from the node 29 is output at the level "1".In this case, the exclusive or
UP/d for ports 277 to 270, respectively.

wn counter 1708 bits all “0” data and N
When the latte data of all 8 bits of E clutch 8 is inputted to ``0°'', a match signal of ``1'' level is supplied to CPU 2, and step 7'SM1 is inputted.
Then, it is determined that the 70-count operation is in progress, and the process proceeds to step Sivi3.

Next, in STETSU 7'SM3, from address 2 of C1 (1) of RAM 5, key code "C3" and key press data "0", that is,
The data in FIG. 4 [C3, ON J is read out and the CPU 2
In step SM4, address 3 of CHI in RAM 5 is set. Then, in the Stella fsM5, the key press data "0" is determined k[1', and the process proceeds to step SM6, where a key code "C3" and a key-on signal are given to the musical tone creation section 3)12, and as a result, First, the warning sound of pitch 03 of the first musical tone of the nolody shown in FIG. Then, in the next step SM8, the time data "0" from CHI number 3 in RAM 5 is set to ξh, output power 2, and address 4 in RAM 5 is set in step SM9. Then, the time data "0" is applied to the input terminal of the full adder 300B for one inch.

On the other hand, the NE clutch 8 is connected to the input terminal of the full adder 30.
The time data "0-1" is being input during lunch, therefore, the addition result data 7 of the full adder 30 at that time
4 hours data 1G'', which is N E latch 28
In addition to being newly latched to the exclusive orgo) 2
Applied to 7'4□ to 27 et al. (Step SMII)
. Then, the process proceeds to Stella fS M12, where it is determined whether or not the coincidence signal is output at the "Il+ level", and the Stellar 7'SM is outputted at the "J# level".
The process proceeds to step SM3 via step SM3. Then, in step SM3, data r C3, 4, ON, J in FIG. 4 is read from address 4 of CHI in RAM 5, and then in step SM4, address 5 of CHI in RAM 5 is set. Through each process of step SM5.5IVi6, the musical tone of pitch 03 of the first musical tone is simultaneously started to be emitted as a chord together with the musical tone of pitch 03. In each process of steps SM8 to SMI 1, the RAM 50CHI
The time data "5" is read from address 5 of the full adder 30 and applied to the B input terminal of the full adder 30, and at that time, the time data rOJ is being input to the input terminal of the
Therefore, time data 5, which is the result data, is NE
It is newly latched into the latch 28. Well, CHI in RAM5 is set to address 6. And step 5M
The process proceeds to step 12, and then, until the matching signal of the "1" level is output, the process first proceeds to step 5M14 and the inversion of the UP/DOWN signal is performed, that is, in the present case, It is determined whether or not the reversing switch ASW is turned on, and since it is rNOJ, the process proceeds to step 5M18, and it is determined whether or not the melody information is being corrected and recorded, and since it is rNOJ, the process proceeds to step 5M.
Proceeding to 2Q, it is determined whether the reset switch IA is turned on, and since this is also rNOJ, step 5
Each process subsequent to M12 is repeatedly executed.

Then, when the length of the time data "5" has elapsed from the start of the simultaneous sound generation of the first tones of the key codes "C3, rC3-, -J" and a matching signal of "1" level is output, Stella: 7' Proceed to SM13, then proceed to Stella fsM, 3, and enter the key code "C3tI" from 6# of RAM 5.
” and the key release data “1”, that is, the data rC3, OFF of the 4th figure are read out.

Further, in step SM4, address 7 of the RAM 5 is set. And in Stetsuno SM5, the # key data "1"
is determined, and the process proceeds to step 'SM7, where the musical tone creation section 3
In response, a key-off signal is applied, and the emission of the musical tone with pitch rc3-J among the first musical tones is stopped.

Next, time data "]" is read from address 7 of RAM 5 by Stella fsM8, and address 508 of RAM is set in step SMQl. And step SM
10. SM 11, 4i, gi:! th,
4-time data ``lj'' is directly applied to the full adder 30's Shikuno ``Poko'', and at that time, the time data ``5'' of the previous result data is input to A-person Nor 1ζko. Because I'm doing it, it's full age - 30 power・rab'' and I'm going to force it.
The result data becomes "6", and in addition to being newly latched to NE ratuna 28,
~27-'o'-\ is applied. And step 5M
12, the count value of the up/do w 17 counter 17 increases by the time data ``6''.
j) Bond until the negative needle signal of 1" is output, the above-mentioned step S1\・114, S M l 8.5M20,
The processes of SMl 2, ... are repeated, and during this time, the pitch rC3-! The musical note 'J' is muted, and only the musical note 'M' with pitch 'C3' is sounded. −
Also, when the coincidence number 4H of "1" level is output, Stella f
S Ml 3 K way.

Then proceed to Stella f8M3.

The reproduction processing for the two first musical tones of the chord is thus completed, and the reproduction processing for the second musical tone is then started in the same manner as described above. Then, when the musical tone No. 1 is being played as described above, the melody information of the song is transferred to RA IVY 5.
input to CH2.

Next, as described above, the two songs of FIG.
~, for example, the third channel of 1% AM5 (hereinafter t-x
I am wondering about the process of recording in the area of CH3).

Figure 10 shows the flowchart of the process. First, when the mixdown switch is turned on,
10th? Steps M1, M2, M3 of the flowchart of
, M4 are executed, and a clear signal is output (l), thereby counter 41.Latch (NEXT), 146, Latch (
NEXT2147, Lunch (LASTT), and 44 are all reset (see Figure 9). Next, Swoop M5,
By each process of M6, the above CH in υ address reno 22 part 7
1 address counter (ADRMI and abbreviated as JCH)
Address counter for 2 (abbreviated as AD RM2)
The starting address (address 0) is preset for each.

Next, in step M7, the leading address is also set in the address counter (abbreviated as A, DRM) for CH3. And the next stage 7'! ', 48, latch 4
The matching circuit unit 42 judges whether the data of 6 and the count outputs of the counters 4 and 1 match yb', and now both data (both are "0"). The coincidence signal E1 of the "1" level is outputted and supplied to the CPU 2. Therefore, the CPU 2 starts the process of step M9, and the output of the sigma reducer 43 and the count output of the counter 43 are The data rOJ obtained by subtracting the data 0-1 from the latch 44 from ``o'' is inserted into the area of the O margin of C □H3 (see Figure 11). is set in the latch 44 and held as the previous data (Stella fM10).
Then, the ADRM is incremented by 1 to become the 1 address, and data rNOPJ at the 0 address by the ADR1 of the CHI is read and written to the 1 address of the CH3 (Stella fM12). Then, ADRl is incremented by +1 to set address 1 (step M13), and then the time data "0" at location 1i of CHl is read out and applied to the input terminal of the adder 45, and then to the #-1B input terminal. is added to the time data "0" of the latch 46, and the resulting time data "0" is latched into the latch 46 again (step M14).

Next, ADRI is incremented by 1 to set address 2 (step M15), and then AD RIVI is incremented by 1 to become address 2 (step M1G). Then, the process returns to step M8.

Next, in step M8, it is determined that the coincidence signal E1 of "1" is still being output, and the process proceeds to step M9, in which RAM 5
The subtraction result data of the subtractor 43 is "0" at address 2 of CH3.
One hole is included. Then, the latch 44 has the counter 4 again.
1 count output "0" is latched (step M10),
ADRM is also incremented by 1 and address 3 is set (step M11).

Next, in STETSU 7'M12, there is a CH at the 3rd address of CH3.
Data rc3 and ONJ from address 2 of I are read and written, ADRI is incremented by 1, and address 3 is set (step M13). Next, in step M14, CHl
The adder 45 adds the latch data rOJ of the latch 46 to the time data rOJ at the third address of , and the resulting time data rOJ is obtained and is launched into the latch 46 . Next, in step M15, ADR1 becomes address 4, and in step M16, ADR1 becomes address 4. Then return to Steppi M8.

In this step 'M8, it is still determined that the output of the matching month E1 is "1" h1, and the process proceeds to step M9 again. Then, in the state 7''M9, M1o''c, the result data rOJ of the subtracter 43 is written in the 4th address of husband k, CH3, and the data rOJ is latched in the latch 44 again. Next, in steps Mll and M12, address 5 is set, and then data rC3' from address 4 of CHI is set at address 5! , ONJ
,＞；Escaped and forced into exile. Next, ADRI is incremented by 1 and address 5 is set (step M13), and then in step M14, the time data "5" from address 5 of CHI is extracted to the lunch 46 and the time data of the latch 46 is set to "0".
are added, and as a result, data "5" is latched into the latch 46. Then, in steps M15 and Ml6, AD
Both Rl and ADR81 are set to 6@ground, and the process returns to step 'M8.

In this step M8, a coincidence signal El of o'' is determined due to the discrepancy between the data of the counter 41 and the latch 46, and the Stellar fM17 is approached. Processing in RAM
In other words, the matching circuit section 42 outputs the counting output "O" of the counter 41 and the latch 47.
It judges whether it matches the latte data "0" and gives a coincidence coefficient E2 of 1" to Ift power L and CPU2.
The CPU 2 instructs to proceed to step M18. Then, perform the following steps M18, Ml, 9, D, 120. M
21, M22, M23, M24, and M25 are steps M9 and MlO for the CH1.

Mll, M12, M13, M14, Ivi15, M2C
, and the same processing as CHI is executed for CH2.

That is, in step M18, the subtracter 43 is placed at address 6 of CH3.
The lees bed data "0" is cut in, and the data "0" is latched again in the latch 44 in step M19. Then, in steps M20 and M21, data rNopJ from address 0 of CH2 shown in FIG. 7 is sent to address 7 of 9CH3.
is read out, and the old name appears. Next, ADR2 is +1,
It was designated as address 1 (Stesono M22), and also as Stetsu 7'M.
At 23, the time data "4" at address 1 of CH2 is read out and added to the data "0" of the latch 47 in the adder 45, and as a result, the data "4" is latched in the latch 47. Then, in steps M24 and M2S, ADR2
is set to address 2, ADRM is set to address 8, and then the process returns to step M17.

In the stesonometer M17, the coincidence signal E2 of '0'' is cut off due to the mismatch between the data ``0'' of the counter 41 and the latch data ``4'' of the latch 47, and the process proceeds to step M26, where the data end of CHI and CH2 is determined. Whether or not the end code is present is determined based on the presence or absence of the end code of each channel.
outputs a +1 signal to the counter 41, causing its counting output to be "1". Then, the process returns to step M8.

In this step M8, it is determined that the count output "1" of the counter 41 and the latch data "0" of the launch 46 do not match, and the process proceeds to step M17, and then this step M1
7, it is determined that there is a discrepancy, and the process proceeds to step M26, where the counter 41 is incremented by 1 by the stesono M27 and becomes "2".
” Then return to step M8.

Below, l"5+ at the moss where the value of the counter 41 matches the data "4" of the latch 47, Portrait Steso fM8, M]7
, M2C, M, 27 are each executed twice.

Then, when the value of the counter 41 becomes "4", step M
At step M18, a coincidence is detected at step M17, and at step M18, the calculation result of "4" between the data "4" of the counter 41 and the data "O" of the latch 44 is stored at address 8 of CH3.
” is inserted by 1. In the old Stesono M i 9, the current value "1" of the counter 41 is sent to the latch 14. Next, in step rvi20, M2], data rG3.0 from CI-I 202nd stlI is stored at address 9 of CH3.
1 sun' is zokugomi', history is A D R2 +] Saharu 3
The address was set (Stesono M22), and the sweet Stesono N1
23, the latch 47 is loaded with the time data "i-2" at address 3 of ADR2 and the data "4" of the latch 47 is 0.
3 and this latch 47 (・ζ is the result data “6
' or set.

And Stesono 0M24, M2S, M17, M2C, M
After each process of 27, the process returns to Stesono M8.

The following operation is a repetition of what has been described above, and is shown in Fig. 8 (A
) and (B) are written in CH3 of the RAM 5 in accordance with the respective melody progressions. The resulting glaze is as shown in Figure 11. Ma/ζζ
Silaso 7' M At 26, CHl, C (20 When the data end is determined, proceed to step M28 and
An end mark is written at the end of the H3 data, and the mixdown process is completed. Figure 8 FA in Italy), (13)
In the middle, the number 0.1... shows the count of the counter 41.

In the above example, the number of memory channels for storing d[, melody information, etc.] was set to 3, but it is possible to have 4 or more channels. In addition, one memory can be used as multiple channels (to avoid problems, it is possible to provide a number of channels individually. Instead, the contents of each memory area can be mixed and combined into one memory area. In order to improve musical tone information, musical tone information from other memory areas may be stored in the memory area where the original musical tone information is stored to adjust the melody information.

〔Effect of the invention〕

As explained above, the present invention provides an automatic performance device in which musical tone information of multiple tones to be sounded simultaneously is stored in the storage means.
If you want to memorize it, you can use an automatic performance device that can record and play chords, for example, by memorizing Tojo information including time data indicating that the pronunciation timings are simultaneous. Since this is an automatic performance device that transfers and stores musical tone information from other areas to one area, it requires a significantly smaller number of storage areas, e.g.
It has the advantage of being able to record and play back chords in the area of the fil:I admiration means, and that it is easy and simple to record and play.

Another advantage is that when the mulberry tone reports from each area of the storage means are combined, no inconvenience will occur even if a plurality of musical tone reports are combined in one square at the same time.

Furthermore, when inputting musical tone information into the storage means, the musical tone information stored in one area is read out and the corresponding musical tone is emitted while inputting musical tone information in another area, which has the advantage that input operations are easy to separate. There is.

[Brief explanation of drawings]

Fig. 1 shows the entire cycle of a certain Moko device according to an embodiment of the present invention.
? - Configuration diagram, FIG. 2 is a detailed circuit diagram of the recording unit 8, FIG. 3 is a flowchart of melody information recording processing, and FIG. 4 is a diagram showing the melody information shown in FIG. 8(A) in 0111 of RAM 5. Memory state diagram, No. 5 shows a detailed circuit diagram of PJ student @9, and No. 81 <6 (A) and FB) show a flowchart of the reproduction process of the melody report, respectively.], No. 7
The figure shows the state of the Amelody information shown in the 8th column 1 (B) in CH2 of RAM 5, Figure 8 1 (A),
(B) k:, 2 types of C, respectively! Figure 9 shows the musical score of I ge noropii. Figure 9 is a mixdown analysis. 1
1 and 10 are flowcharts showing the operation of the mixdown processing (1, 1), and a diagram showing the storage state diagram in CH3 of the RAM 5 after the mixdown processing. 1... Gabansu 1 Sochi Department, LA (BSW)...
...Reset switch, 1B...Reverse switch (reverse switch), IC...Ref-1-
9 switch, ], D... End switch, 2.
...CPU, 3...Musical tone creation section, 4...
...Location control section, 5...RAM, 6R16L.
...Speaker, 7...Address recording section, 8...Recording section, 9...Playback section, 10
・・・・・・Mixdown section,】]・・・PR
Latte, 14...subtractor, 17...u
p/dow nh counter, 18/old-f oscillator, 19...tempo volume, 2L
22.26...Nriff 0 frog, 28-=
-NE latch, 30...Full adder, BSW
...Forward switch, C8W...Tempo acceleration switch, 'DSW...Slow tempo switch, ESW...Ten hire) Sopsinch, FSW
...Normal switch, 41 ...Counter, 42 ... Match circuit section, 43 ...Subtractor, 44 Latch, 45 ...・Addition section, 4
6.47...Latch, COX, C'H2, CH
3... Each channel of RAM5. Ship Permit Applicant: Casio Sai1 Computer Co., Ltd. Figure 3, Figure 4, Figure 6, Figure C9) Figure 7, Figure 1j Procedural Amendment (Voluntary) February 14, 1980 Commissioner of the Patent Office Kazuo Wakasugi 1. Indication of the case Patent Application No. 232842 of 1982 2. Name of the invention t for automatic musical instrument 3. Relationship with the person making the amendment Special i! i: Address: 2-6-1 Nishishinka, Shinjuku-ku, Tokyo Name (
144) Casio N Computer Co., Ltd. Representative Kashio
Toshio 4, agent 5, subject of amendment (1) “Detailed description of the invention” in the specification. 6. Contents of the amendment (1) In Meiku I attached to the application, it is written from page 21, line 15 to page 22, line 3: “Then, the processing power of step RM17 is executed, and the CPU 2 sends the signal LAT to the PR clutch 1. "Then, the subtracter 14 performs an operation to subtract the input data from the PR clutch 1 to the B input terminal from the input data to the B input terminal. The input data of is subtracted, and this result is used as time data by CPU2.
Output to. Next, the process of step RM1□ is executed, and C]) U2 applies the signal LAT to the PR latch 11, launches the data being input into the PR clutch 1, and holds the launch data from now on. It is applied to the B input terminal of the subtracter 14. Then step RIS
4 rs, and the time data (subtractor 14
I am corrected. (2) In the 5th line of page 22 of the same book, the phrase “dere” was replaced with “
)”.

Claims (1)

[Scope of Claims] (IJ) A musical tone information input means, a storage means for digitally storing one or more pieces of musical tone information to be produced at the same time, which are reversely inputted from the musical tone information input means, and a musical tone information read from the storage means. and musical tone signal generation means for generating a musical tone signal based on information on one or more musical tones to be simultaneously sounded. The automatic performance device according to claim 1, characterized in that a plurality of pieces of musical tone information including timing information are continuously stored in one area. The automatic performance device according to claim 1, wherein the automatic performance device generates a musical tone signal by determining musical tone information to be simultaneously produced according to the timing information received. The automatic performance device has a plurality of areas, and musical tone information can be stored independently in each area, and furthermore, the automatic performance device has a control means, and the control means adjusts timing information included in each musical tone information. The automatic performance device according to claim 1, wherein the musical tone information stored in the plurality of areas is re-stored in one area by performing the following steps: (5) musical tone information input means; a first storage means for digitally storing the musical tone information reversely inputted from the information input means; a processing means for reproducing the musical tone information stored in the first storage means and emitting a corresponding musical tone; , when different musical tone information is input by the musical tone information input means while the musical tone information stored in the first storage means is reproduced and emitted by the processing means, the different musical tone information is digitally stored. (6) The musical tone information input means includes a keyboard having a plurality of keys. 6. The automatic performance device according to claim 5. The automatic performance device according to claim 5, wherein the first storage means and the second storage means are different areas of the same memory. (8) The first and second storage means are each capable of independently storing musical tone information, and furthermore, the automatic performance device has a control means, and the control means determines the timing included in each musical tone information. Claim 5, wherein the independent musical tone information stored in the first and second storage means is re-stored in the third storage means by adjusting the information. Automatic performance, equipment.