JPH0141000B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a music information synthesis device used, for example, in an automatic performance device.

[Prior Art] For example, there is no automatic performance device that can digitally perform multi-recording, and there has been a strong desire for a model that can perform digital multi-recording.

[Object of the Invention] An object of the present invention is to provide a music information synthesis device that enables digital multiple recording.

[Summary of the Invention] The present invention enables digital multiplex recording by mixing down a plurality of pieces of music information read out according to the time context indicated by each time information. The main point is

[Embodiments] Hereinafter, embodiments in which the present invention is applied to an automatic performance device will be described with reference to the drawings. 1st
The figure is a circuit diagram showing the overall configuration of an electronic musical instrument equipped with an automatic performance function. The keyboard switch section 1 is equipped with multiple keys and various switches for obtaining various effects such as tone, vibrato, sustain, stereo sound localization, normal rhythm, fill-in rhythm, automatic accompaniment, etc. A switch is provided for playing. For example, there are a reset switch 1A, a reverse switch 1B, a record switch 1C, an end key 1D, etc., and these functions will be described later. The CPU (Central Processing Unit) 2 periodically outputs a key scan signal via the bus line B1 to scan the keyboard switch section 1, and in response, the keyboard switch section 1 outputs a key scan signal to scan each key or switch. An output signal is outputted and given to the CPU 2 via the bus line B2. CPU
In response to this, for example, the section 2 provides musical tone generation command information to the musical tone generating section 3 via the bus line B3,
A musical tone signal for a melody or automatic accompaniment is created and supplied to the localization control section 4. Also, CPU2 is
Control information according to sound image localization information preset in a RAM (random access memory) 5, which will be described later, is output to the bus line B4 and given to the sound image localization control section 4 to set the sound image localization for the musical sound signal. Then, corresponding signals are output to the left and right speakers 6R and 6L, and musical tones are emitted.

Data read and write operations of the RAM 5 are controlled in accordance with address control information supplied by the CPU 2 to the address register unit 7 via the bus line B5. Data is exchanged between the CPU 2 and the RAM 5 via the bus line B6. In this case, the RAM 5 contains musical tone information indicating the pitch, note length, and rest of the song (hereinafter referred to as melody information for convenience), tone, vibrato, sustain, sound image localization, fill-in rhythm on/off, etc. Performance information for obtaining various effects is stored in different areas. The address register section 7 is provided with independent address counters for each of the melody information and performance information, so that when automatic performance is performed, the melody information and performance information are set in accordance with the melody progression. As a result, they are read out in parallel and at the same time, allowing for automatic performance. In addition, in this embodiment, there are three areas for storing melody information.
There is one.

The recording section 8 generates time information (data D7 to D0) representing the tone length from the time information (data D7 to D0) given from the CPU 2 via the bus line B7 and the time information (data TD7 to TD0) given from the playback section 9 via the bus line B11. Create data I7 to I0),
Supplied to CPU2 via bus line B8, RAM
5 as the melody information or performance information.

The playback unit 9 receives information in accordance with the melody information and performance information read from the RAM 5 during playback from the CPU 2 via the bus line B9, creates data for playback processing, and sends the data to the bus line B10. and to the recording unit 8 during recording, as mentioned above.
Gives time information. Note that CPU2 is a processor that controls all operations of this electronic musical instrument.
The detailed explanation will be omitted.

The mixdown section 10 is a circuit that performs a process of synthesizing musical tone information written in different areas (also referred to as different channels) in the RAM 5 and writing it into any one channel. In that case, necessary data is exchanged between the mixdown section 10 and the CPU 2 via the bus lines B12 and B13, details of which will be described later. Note that when inputting the synthesized data obtained by the mixdown processing of the mixdown section 10 to any channel of the RAM 5, an address register (referred to as ADRM) for addressing that channel is set in the address register section 7.
It is set in.

Next, the configuration of the recording section 8 will be explained with reference to FIG. The PR latch 11 normally contains count output data TD7 of an UP/down counter in the playback section 9, which will be described later.
~TD0 is input via the transfer gate group 12, and when the CPU 2 outputs the signal LAT, it is latched. Also, when the playback operation is temporarily stopped during playback, rewind is performed by operating the reverse switch 1B, and then recording is started anew, the latch data of the PR latch 11 is
The output data of the full adder at that time is sent to the transfer gate group 1 via the CPU 2 as data D7 to D0.
It is further latched to PR latch 11 via 3. The data latched into the PR latch 11 is applied to the B input terminals (B7 to B0) of the subtracter 14. In addition, the A input terminal of the subtracter 14 (A7 to A
0), the data TD7 to TD0 are input.
The subtracter 14 subtracts the input data at the B input terminal from the input data at the A input terminal, and sends the resulting data I7 to I0 to the RAM 5 through the CPU 2 for storage. In the case of melody information, these data I7 to I0 indicate time data giving a key-on time and key-off time, and on the other hand, in the case of the automatic performance information of an effect, they are time data indicating the generation period of the effect. The transfer gate group 12 has the signal CH output from the CPU 2 applied to its gate via the inverter 15, and the transfer gate group 13 has the signal CH directly applied to its gate, so that both gates are controlled. .

Next, the configuration of the reproducing section 9 will be explained with reference to FIG. The UP/down counter 17 is an 8-bit counter, and after being cleared by the CPU 2 outputting a clear signal CLR at the start of recording or playback, it counts clocks based on the signal output by the tempo oscillator 18. Perform the action.

In addition, the frequency of the oscillation output of the tempo oscillator 18 is variable by a tempo volume 19, and the output of the tempo oscillator 18 is input to an AND gate 20. The output of the tempo switch ESW is input to the other end of the AND gate 20 for gate control, and the output of the AND gate 20 is input to a T-type flip-flop 21 and a transfer gate 23. Further, the set output of the flip-flop 21 is connected to the T-type flip-flop 22 and the transfer gate 24.
Enter. Furthermore, the set output of flip-flop 22 is input to transfer gate 25.
Each of the transfer gates 23, 24, and 25 has an output of a tempo acceleration switch CSW, a normal switch FSW, and a slow tempo switch DSW, each of which is a triple lock type switch in which only one is in the on state. applied and gated. and each transfer gate 2
Each output of 3, 24, 25 serves as the clock.
It is counted by the UP/down counter 17. Thus, the flip-flops 21 and 22 form a frequency dividing circuit, and the frequencies of the outputs of the flip-flops 21 and 22 are 1/2 and 1/4, respectively, of the output of the tempo oscillator 18.

The up-count operation and down-count operation of the up-down counter 17 are controlled by the set output signal UPDOWN of the flip-flop 26, respectively. That is, flip-flop 26
The outputs of a forward switch BSW and a reverse switch ASW (same as the reverse switch 1B in FIG. 1) each consisting of a double lock type switch are input to the set input terminal S and the reset input terminal R of the switch.
Each bit output of the UP/down counter 17 is input to one end of each of the corresponding exclusive OR gates ₂₇₇ to ₂₇₀ , and is also sent to the recording section 8 as data TD7 to TD0. Also exclusive or gate 2
Corresponding bit outputs of an 8-bit capacity NE latch 28 are input to the other ends of the pins ₇₇ to ₂₇₀ . Then, each output of the exclusive OR gates 27 ₇ to 27 ₀ is input to the NOR gate 29, which further inputs the NOR gate 2
The output of 9 is supplied to the CPU 2 as a coincidence signal. That is, the exclusive OR gates 27 ₇ to 27 ₀ and the NOR gate 29 form a matching circuit.

The NE latch 28 latches the addition or subtraction result data from the S output terminals S7 to S0 of the full adder 30 when the CPU 2 outputs a latch clock. In addition, the NE latch 28 controls the CPU 2 at the start of recording and playback operations.
It is cleared by applying the clear signal CLR output by . A input terminal A7 of the full adder 30~
The latch data of the NE latch 28 is fed back through the transfer gate group 31 and input to A0. Further, the outputs of the exclusive OR gates 32 ₇ to 32 ₀ are input to the B input terminals B7 to B0, and the output of the AND gate 33 is input to the carry input terminal CIN via the inverter 34 and the transfer gate 35. There is. Therefore, exclusive or gate 32 _7
〜320 At each end is a PR latch 11 in the recording section 8.
After rewinding time data during playback, the time data is input in response to a key operation when performing a new recording operation for correction. Further, the output of the AND gate 33 is applied to each other end via an inverter 34 and a transfer gate 35.

The AND gate 33 has a flip-flop 26
The set output of and the signal R output by the CPU are input. This signal R is normally output as "1", and temporarily becomes "0" during the recording correction.
is output as The output of the AND gate 33 is then sent to the CPU 2. Also, transfer gate group 31 and transfer gate 35
is gate-controlled by the signal CHR output from the CPU 2, and this signal CHR is a signal that is temporarily set to "0" and output from the CPU 2 when corrections are made during recording. Furthermore, the latch data of the NE latch 28 output from the transfer gate group 31 is sent to the PR latch 11 when data is corrected during reproduction.

Next, the specific configuration of the mixdown section 10 will be explained with reference to FIG. The counter (also abbreviated as CNT) 41 is cleared by the clear signal CLR output by the CPU 2 at the start of the mixdown process, and then inputs the +1 signal output by the CPU 2 to execute a counting operation. Its capacity is 8 bits, and its counting output is sent as time data to the A input terminal of the coincidence circuit section 42, the A input terminals A7 to A0 of the subtracter 43, and the latch (also abbreviated as LASTT) 44. LI input terminal LI
7 to LI0, respectively. The latch data of the latch 44 is then transmitted through the L output terminals L7 to L0.
It is applied to the B input terminals B7 to B0 of the subtracter 43. The subtracter 43 subtracts the input data to the B input terminal from the input data to the A input terminal, and outputs the time data of the difference to the 0 output terminals 07 to 00.
It is output from the RAM 5 and written to the specified channel in the RAM 5 as one of the composite data.

Time data from two channels to be mixed down in the RAM 5 are read out and applied to the A input terminal of the adder 45. Further, the B input terminal or the C input terminal of the adder 45 is provided with time data latched by a latch 46 for one of the two channels (also abbreviated as NEXT1) or a latch for the other channel (also abbreviated as NEXT2). (abbreviated) 47 is latched time data is input respectively. The adder 45 adds the input data to the A input terminal and the input data to the B input terminal or the input data to the C input terminal, and outputs the resulting data as new time data to the D output terminal or the E input terminal, respectively. It is output from the output terminal and latched into latch 46 or latch 47. Note that the latches 46 and 47 are
The latch operation is performed when the CPU 2 outputs the signals LA1 and LA2. Furthermore, at the start of the mixdown process, the latches 46 and 47 are activated by the clear signal CLR output from the CPU 2.
is also cleared along with the counter 41.

Each latch data of the latches 46 and 47 is sent to the B input terminal or the C input terminal of the coincidence circuit section 42, respectively.
applied. Then, the coincidence circuit section 42 detects the coincidence or mismatch between the input data to the A input terminal and the input data to the B input terminal, and outputs a coincidence signal E1 and sends it to the CPU 2. The match signal E2 is detected and sent to the CPU2.

Next, the second part of the melody progression shown in Figure 8A and B, respectively.
We will explain the operation of recording and playing back one song to RAM5. First, the case of recording will be explained. in this case,
For example, the melody information of the song shown in FIG. 8A is first recorded by key operations on the keyboard switch section 1. FIG. 3 is a flowchart illustrating the recording operation of this melody information. In addition, the 8th
Numbers 0 to 17 in the figure indicate the count outputs of the counter 41.

Which channel (for example,
Turn on the recording start switch (not shown) for the first channel (CHI). Then, the output is input to CPU2 via bus line B2, and the output is input to CPU2 via bus line B2.
In response to this, step RM1 of the flowchart of FIG. 3 is performed. That is, clear signal
Output CLR to bus lines B7 and B9, respectively, and PR
Clear the latch 11, NE latch 28, and UP/down counter 17, respectively. Next, the CPU 2 inputs the address counter for the first channel (CHI) in the RAM 5 into which the melody information of the song shown in FIG. 8A in the address register section 7 will be written.
In order to set the first address, address control information is output to bus line B5 and set (step
RM2). Next, CPU2 sends data to bus line B6.
Output NOP and write it to the first address (address 0) of CHI in RAM5. FIG. 4 schematically shows the memory state. Therefore, the NOP of this data
(NO OPERATION) is data similar to a rest that does not produce musical tones. Above is step RM3
This is the process. Then, the CPU 2 increments the address counter (hereinafter simply referred to as the address register) of the address register section 7 by 1 in step RM4, and sets address 1. Next, in step RM5, it is determined whether or not the reset switch 1A has been turned on. Therefore, this reset switch 1A is
This is a switch that is turned on when making recording corrections. When turned on, the process returns to step RM1, and
Set to initial state. On the other hand, if the end key 1D has not been turned on, the process proceeds to step RM6, where it is determined whether or not the end key 1D has been turned on. This end key 1D is a switch that is turned on at the end of inputting melody information to write an end code at the end of the melody information input into the RAM 5. Therefore, when the end key 1D is turned on ( If Y (YES), the process advances to step RM7 and the above-mentioned processing is executed. However, since the end key 1D is not turned on at this time (N "NO"), the process advances to step RM8, and a process for determining whether or not the reverse switch 1B (reverse switch ASW) is turned on is executed. When it is turned on, the process of moving to the recording standby state in step RM9 is executed, and this process will be explained in detail later. And now, of course, reverse switch 1
Since B is not turned on, the process proceeds to step RM10, where it is determined whether or not a key has been operated. And Figure 8A
The two first notes of the melody (pitch C3, C3#
Steps RM10, RM5, RM6,
RM8, RM10,... are repeated. and C
3. When the C3# keys are turned on at the same time, the process proceeds to step RM11, where a process to determine whether the key is pressed or released is executed.Since the keys are pressed, the process proceeds to step RM12, where the CPU 2 first turns on the bass tone. To show that it is the key code and key press data for pitch C3 on the side,
Tone information is calculated by adding data "0" to the MSB (most significant bit) of the key code. Then, it is applied to the musical tone generator 3 via the bus line B3, and the speakers 6R and 6L start emitting the sound (step RM13). Next step RM
16, the CPU 2 sets the signal CH to "0", and thereafter, in normal times, the transfer gate group 12
are kept open at all times, and transfer gate group 1 is kept open at all times.
3 is always closed. As a result, after the above-mentioned clearing process of step RM1 is performed in the playback section 9, the clock of the set tempo is input and the counting operation is performed.
The forward switch BSW is now turned on, the flip-flop 26 is set, and the UP/UP count operation is in progress.
The count output (time data) of the down counter 17 is transferred to the bus line B11 as data TD7 to TD0.
PR latch 1 via transfer gate group 12
1 and is input to the A input terminal of the subtracter 14. Then, the subtracter 14 subtracts the input data to the A input terminal from the input data from the PR latch 11 to the B input terminal, and outputs this result to the CPU 2 as time data. Next, the process of step RM ₁₇ is executed, and the CPU 2 sends a signal to the PR latch 11.
LAT is applied, the data being input at that time is latched in the PR latch 11, and the latched data is thereafter held and applied to the B input terminal of the subtracter 14. Next, the process proceeds to step _RM18 , where the time data (the input data to both input terminals of the subtracter 14 are the same value, so the resultant data I7 to I0 at that time are "0") is transferred to the RAM 5. Written to address 1. Next, the address register is incremented by 1 to set address 2 (step RM19), and the previously calculated key press code, that is, the key code C3 and key press data "ON" are written to address 2 of RAM 5. (Step RM20). Then, the address register is incremented by 1 to set address 3 (step RM2), and the process returns to step RM5.

Next, step RM5, RM6, RM8, RM
Through each process of 10 to RM13 and RM16 to RM21, the process for the key of pitch C3# that was turned on at the same time is executed in the same way, and time data "0" is written to address 3 of CHI in RAM5, and time data "0" is written to address 4. The key code C3# and key press data (“ON”) are written. The address register is then set to address 5, and the process returns to step RM5. Then pitch C
Two musical tones, 3 and C3#, are emitted simultaneously as a chord.

Next, when it is determined in step RM10 via steps RM5, RM6, and RM8 that the key has been released at pitch C3#, the process proceeds to step RM14, where the key code and key release data for pitch C3# are determined. In order to indicate that there is a key code, data "1" is added to the MSB of the key code to create a key release code. Then, it is sent to the musical tone generating section 3, whereby the musical tone of the pitch C3# is muted (step RM15). Then the above steps
When proceeding to step RM17 via RM16, the PR latch 11 has the UP/UP signal at the time of the key release operation.
The time data of the down counter 17 is newly latched, held thereafter, and applied to the B input terminal of the subtracter 14. Then, the subtracter 14 subtracts the time measurement data at the time of the key press of the key of pitch C3#, which was being input to the B input terminal, from the time measurement data input to the A input terminal at the time of the key release operation, and the resultant data is obtained. and writes the time data to address 5 of RAM 5 (step RM18). In this case, as shown in FIG. 4, the time data at this time is "5". Then, the key release code is written into address 6 of the RAM 5 through the processes of steps RM19 and RM20, as shown in FIG. and step
Address 7 is specified by RM21, and step RM
Return to 5.

Next, when the key of pitch B3 of the second musical tone is pressed,
This is determined in step RM10, and the process proceeds to step RM12 via step RM11.
The key press code is calculated in the same way as when operating each key of pitches C3 and C3#. And step RM13
Through the process, the creation and emission of a musical tone of pitch B3 is started. And steps RM16, RM17,
Through each process of RM18, PR latch 11 has the following:
At the same time, the time data when the pitch B3 key is pressed is latched, and the subtracter 14 calculates the separation of the pitch C3# from the time data when the pitch E3 key is pressed to the A input terminal to the B input terminal. Data is obtained as a result of subtracting the clock data of the key hour, and is written to address 7 of the RAM 5. In this case, as shown in FIG. 4, the time data based on the result data is "1". Also,
After the processing of step RM20, step RM
21 specifies the next 9th address in RAM5, and the process returns to step RM5.

Hereinafter, when the melody is played at time intervals according to FIG. 8A, the same processing as described above will be performed.
Below CHI address 9 in RAM 5, melody information starting from the third tone is written. When the last performance input is completed, the end key 1D is turned on and the end code is written into the RAM 5 as the last data of the melody information.

Next, the process of step RM9 when the reverse switch 1B is turned on will be explained. This reverse switch 1B (reverse switch ASW) is turned on when a key operation is made incorrectly when inputting the melody information, returns the address register section 7 to the desired address, and sets the correct melody information to a standby state where it can be recorded. In that case, when the reverse switch 1B is turned on, the latch data of the PR latch 11 at that time is
It is latched by the NE latch 28 of the playback section 9 via the CPU 2.

In the above manner, CHI of RAM5 is
After writing the melody information, this Figure 8A
While playing and listening to the melody information in Figure 8B.
The melody information of the song is written to the second channel of RAM5 (hereinafter referred to as CH2). The recording process in this case (i.e., the process in the flowchart in Figure 3) is the same as that described above, and as a result, CH2 of RAM 5 has the state shown in Figure 7. Melody information of the song shown in Figure 8B is written.

Therefore, the melody reproduction processing operation will first be explained with reference to the flowcharts of FIGS. 6A and 6B.

First, when the playback switch for CH1 of RAM 5 is turned on, a clear signal is output through the processing in step SM1, and the NE latch 28 in FIG.
Both the UP/down counters 17 are cleared. Next, in step SM2, the leading address for the melody information of FIG. 8A written in CH1 of the RAM 5 is set in the address register section 7.
Processing data "NOP" (see FIG. 4) is then read out from the RAM 5 and supplied to the CPU 2 (step SM3). And address register 7 is +1
and address 1 is set (step SM4).
Then, the CPU 2 performs a process of determining whether the MSB of the data "NOP" is "0" or "1" in step SM5, but in this case, since the data is "NOP" which is similar to a rest, the process proceeds to step SM7. A control signal corresponding to a key-off signal is output to the musical tone generating section 3, and execution of musical tone generation is prohibited. Further, when proceeding to step SM8, time data "0" is read from address 1 of RAM 5, and address register 7 is incremented by 1 to set address 2 (step SM9). Also, the time data "0" from address 1 is input to the B input terminal of the full adder 30, and the resulting data is then latched in the NE latch 28 (steps SM10, SM11). In this case, the forward switch BSW is now turned on, and as a result, the flip-flop 26 is in the set state, the AND gate 33 is opened, and the up/down counter 17 is given an up count command. There is. The signal R is normally output as "1", so the output of the AND gate 33 is normally "1", and the signal is
At the same time as being supplied to the CPU 2, the output of the inverter 34 normally becomes "0" and the exclusive OR gate 3
2 ₇ to 32 ₀ and the carry input terminal CIN of the full adder 30 through a transfer gate 35. Note that the signal CHR is normally output as "1", therefore,
The transfer gate 35 and the transfer gate group 31 are normally open.

Therefore, in steps SM10 and SM11, the time data "0" is set to the exclusive OR gate 3.
27 to 320, the signals are input to the B input terminal of the full adder 30 as they are without being inverted. On the other hand, the output data of the NE latch 28 (8-bit all "0" data) is input to the A input terminal to the transfer gate group 31, and therefore the full adder result data at that time becomes "0".
It will be latched to NE latch 28.

Next, in step SM12, it is determined whether the match signal from the NOR gate 29 is output at the "1" level. In this case, the exclusive OR gates 277 to 270 are UP/DOWN, respectively.
8-bit all “0” data of counter 17,
The latch data of all 8 bits "0" of the NE latch 28 is input, and therefore a "1" level match signal is supplied to the CPU 2.
The process advances to step SM13, and it is determined that the up-count operation is in progress, and step SM13 is reached.
It will proceed to step 3.

Next, in step SM3, CH1 of RAM5 is
From the address, key code "C3" and key press data "0",
That is, the data "C3, ON" in FIG. 4 is read out and input to the CPU2, and also in step SM4.
Address 3 of CH1 of RAM5 is set. Then, in step SM5, it is determined that the key press data is "0", and the process proceeds to step SM6, where the musical tone creation section 3
, a key code "C3" and a key-on signal are given, and as a result, the musical tone of pitch C3 of the first musical tone of the melody shown in FIG. It turns out. In the next step SM8, time data "0" is read from address 3 of CH1 of RAM5, and in step SM9, address 4 of RAM5 is set. The time data "0" is applied as is to the B input terminal of the full adder 30. on the other hand,
NE latch 28 to the A input terminal of full adder 30
is being latched and time data “0” is being input.
Therefore, the addition result data of the full adder 30 at that time is equal to the time data "0", and it is
In addition to being newly latched to NE latch 28,
It is applied to the exclusive OR gates ₂₇₇ to ₂₇₀ (step SM11). Then, the process proceeds to step SM12, where it is determined whether or not the coincidence signal is output at the "1" level.
Proceed to. And with this step SM3
The data “C3#, ON” in FIG. 4 is read from address 4 of CH1 of RAM5, and then the step SM
4 sets address 5 of CH1 of RAM5,
Further, through each process of steps SM5 and SM6, the musical tone of the first musical tone having a pitch C3# is simultaneously started to be emitted as a chord together with the musical tone having a pitch C3. In each process of steps SM8 to SM11, RAM5 is
Time data "5" is read from address 5 of CH1 and applied as is to the B input terminal of the full adder 30. At that time, time data "0" is being input to the A input terminal, but Then, the resulting data, time data 5, is newly latched into the NE latch 28. Further, CH1 of RAM5 is set to address 6. And step SM1
2, and then proceeds to step SM14 until a "1" level match signal is output.
It is determined whether or not the UP/down signal is inverted, that is, in this case, whether the reverse switch ASW is turned on or not. Since it is not turned on and the answer is "NO", the process proceeds to step SM18, where the melody information is corrected and recorded. It is determined whether the reset switch 1A is on or not, and since the answer is "NO", the process proceeds to step SM20, where it is determined whether the reset switch 1A has been turned on, and since this is also "NO", the process returns to step SM12. Each process is executed repeatedly.

Then, when the length of the time data "5" has elapsed from the start of the simultaneous sound generation of the first tones of the key codes "C3 and C3#" and a match signal of the "1" level is output, the process proceeds to step SM13. Then, the process advances to step SM3, and the key code "C3#" and key release data "1" are input from address 6 of RAM5, that is,
The data "C3#, OFF" in FIG. 4 is read out.
Further, in step SM4, address 7 of RAM5 is set. Then, in step SM5, the key release data "1" is determined, and the process proceeds to step SM7, where a key code "C3#" is sent to the musical tone creation section 3.
A key-off signal is given, and the emission of the musical tone of pitch "C3#" among the first musical tones is stopped.
Next, step SM8 reads time data "1" from address 7 of RAM5, and step _SM9 reads out time data "1" from address 7 of RAM5.
In this case, address 8 of RAM5 is set. and,
Through steps SM10 and SM11, the time data "1" is input as is to the B input terminal of the full adder 30, and at that time, the A input terminal is
Since the time data "5" of the previous result data is input, the addition result data output from the full adder 30 is "6", and in addition to being newly latched to the NE latch 28, the exclusive OR gate 27 ₇
~27 applied to ₀ . Then, the process proceeds to step SM12, and until the count value of the up/down counter 17 reaches the time data ``6'' and a coincidence signal of ``1'' is output, the process proceeds to the step SM1 described above.
The processes of 4, SM18, SM20, SM12, etc. are repeated, and during this time, the musical tone with pitch "C3#" among the first musical tones is muted, and only the musical tone with pitch "C3" is produced. are doing. When a match signal of "1" level is output, the process advances to step SM13, and then to step SM3.

The reproduction process for the two first musical tones of the chord is thus completed, and thereafter the reproduction process for the second musical tone is started in the same manner as described above. Then, while the first musical tone is being reproduced as described above, it is played according to FIG. On the other hand, during recording, it is possible to rewind by operating the reverse switch 1B, and then to perform a key operation while the sound is being reproduced to immediately shift to the recording state. That is, key-on is determined at step _SM19 , and the process proceeds to step _SM21 , where processing for transitioning to the recording state is performed. In other words, the full adder 30 temporarily executes a subtraction operation, and from the cumulative time data latched to the NE latch 28,
The result of subtracting the current time data of RAM5 is
Latch NE latch 28, move to PR latch 11,
The latch data of this NE latch 28 is transferred. Then, after returning the full adder to addition operation,
The subtraction result of the subtracter 14 is written to the RAM 5, the key press code of the currently keyed-on key is written to the next address, and the address is further incremented by one. Thereafter, the process proceeds to RAM ₅ in Figure 3.

Next, as described above, CH1 and CH of RAM5
The following describes the process of combining the two songs A and B in FIG. 8, which were respectively recorded on 2, by the mixdown process of the mixdown section 10, and recording them, for example, in the area of the third channel (hereinafter referred to as CH3) of the RAM 5. FIG. 10 shows a flowchart for this purpose.

First, when the switch for mixdown is turned on, step M in the flowchart in Figure 10 is executed.
1, M2, M3, and M4 are respectively executed, and by outputting the clear signal, the counter 41, latch (NEXT1) 46, latch (NEXT2), 47,
Both latches (LASTT) 44 are reset (see Figure 9). Next, through the processes of steps M5 and M6, the start address (address 0) is preset in the address counter (abbreviated as ADR1) for CH1 and the address counter (abbreviated as ADR2) for CH2 in the address register section 7, respectively.
Next, in step M7, a leading address is also set in the address counter (abbreviated as ADRM) for CH3. In the next step M8, the matching circuit section 42 determines whether the data of the latch 46 and the count output of the counter 41 match, and therefore, both data are now "0".
The match signal E1 of "1" level is outputted and supplied to the CPU 2. Therefore, the CPU 2 starts the process of step M9 and selects the latch 4 from the result data of the subtracter 43, that is, the counting output "0" of the counter 1.
The data “0” obtained by subtracting the data “0” from 4 is CH
3, address 0 area (see FIG. 11). Next, the count output "0" of the counter 41 is set in the latch 44 and held as the previous data (step M10). Then, in step M11, the ADRM is incremented by 1 to become the 1st address, and the ADR of CH1 is then added to the 1st address of CH3.
Data "NOP" at address 0 by 1 is read out and written (step M12). And ADR1
is incremented by +1 and set to address 1 (step M1).
3) Next, the time data "0" at address 1 of CH1 is read out and applied to the A input terminal of the adder 45,
It is added to the time data "0" of the latch 46 to the B input terminal, and the resulting time data "0" is latched again to the latch 46 (step M14). Next, ADR1 is incremented by 1 to set the 2nd address (step M15), and then ADRM is incremented by 1 to become the 2nd address (step M16). And step M8
Return to

Next, in step M8, it is determined that the coincidence signal E1 of "1" is still being output, and the process proceeds to step M9, where the subtraction result data "0" of the subtracter 43 is written to address 2 of CH3 of the RAM 5. Then, the count output "0" of the counter 41 is latched again in the latch 44 (step M10), and ADRM is + again.
1 and set address 3 (step M1).
1). Next, in step M12, the 3rd part of CH3
Data from address 2 of CH1 at address "C3, ON"
is read and written, and ADR1 is incremented by 1 to set address 3 (step M13). Next, in step M14, the time data "0" of the 3rd address of CH1 is set to the latch data "0" of the latch 46.
The time data "0" is obtained as a result of adding the data in the adder 45, and is latched in the latch 46. Next, in step M15, ADR1 becomes address 4,
Further, in step M16, ADRM becomes address 4. Then, the process returns to step M8.

In this step M8, it is still determined whether the coincidence signal E1 of "1" is output, and the process proceeds to step M9 again. And in steps M9 and M10, respectively,
The result data of subtractor 43 is “0” at address 4 of CH3
is written, and data "0" is latched in the latch 44 again. Next, in steps M11 and M12, address 5 is set, and then CH1 is set at that 5th address.
Data "C3#, ON" from address 4 is read and written. Then ADR1 is +1 and becomes 5.
The address is set (step M13), and then in step M14, the time data "5" from address 5 of CH1 is read out to the latch 46 and added to the time data "0" of the latch 46, resulting in data "5". ” is latched to latch 46. Then, in steps M15 and M16, address 6 is set for both ADR1 and ADRM, and the process returns to step M8.

In this step M8, a coincidence signal E of "0" is generated due to a mismatch between the data of the counter 41 and the latch 46.
1 is determined, and the process proceeds to step M17. In step M17, the same process as M8 is executed on CH2 of RAM5.
That is, the coincidence circuit unit 42 determines whether the count output "0" of the counter 41 and the latch data "0" of the latch 47 match, and outputs a coincidence signal E2 of "1".
Give to CPU2. Thereby, the CPU 2 instructs to proceed to step M18. With a screw, follow the steps M18, M19, M20, M21, M2
2, each process of M23, M24, and M25 is performed by the CH
Each step M9, M10, M11, M for 1
12, M13, M14, M15, and M16, respectively, and the same processing as CH1 is executed for CH2.

That is, in step M18, the result data "0" of the subtracter 43 is written to address 6 of CH3, and in step M19, the data "0" is latched in the latch 44 again. And steps M20 and M21
Therefore, CH2 shown in Figure 7 for address 7 of CH3
Data "NOP" from address 0 is read and written. Next, ADR2 is incremented by 1 to become address 1 (step M22), and in step M23, the time data "4" of this one character position of CH2 is read out and added to the data "0" of the latch 47 in the adder 45. As a result, data "4" is latched in latch 47. And step M24,
In M25, ADR2 is set to address 2, and
ADRM is set to address 8, then step M
Return to 17.

At step M17, a coincidence signal E2 of "0" is determined based on the mismatch between the data "0" of the counter 41 and the latch data "4" of the latch 47, and the process proceeds to step M26, where it is determined whether or not it is the data end of CH1 and CH2. This is determined based on the presence or absence of the end code of the channel, and it is not the data end, so the process proceeds to step M27, where the CPU 2 outputs a +1 signal to the counter 41 to set its counting output to "1". Then, the process returns to step M8.

In this step M8, it is determined that there is a mismatch between the count output "1" of the counter 41 and the latch data "0" of the latch 46, and the process proceeds to step M17. Further, in step M27, the counter 41 is incremented by 1 to become "2", and the process returns to step M8.

Thereafter, until the value of the counter 41 matches the data "4" of the latch 47, the steps M8,
M17, M26, and M27 are each executed twice.
When the value of the counter 41 becomes "4", a match is detected in step M17 via step M8, and in step M18, the data "4" of the counter 41 and the data "0" of the latch 44 are set at address 8 of CH3. The subtraction result "4" is written. At step M19, the latch 44 is set to the current value "4" of the counter 41. Next step M2
0, M21, data "G3, ON" from address 2 of CH2 is written to address 9 of CH3, and
ADR2 is incremented by +1 and address 3 is set (step M22). Also, in step M23, latch 47 is set.
Then, the time data "2" at address 3 of ADR2 is added to the data "4" in the latch 47, and the resulting data "6" is set in the latch 47. And steps M24, M25, M17, M
After the processing in steps M26 and M27, the process returns to step M8.

The following operation is a repetition of what has been described above, and composite data is written into CH3 of the RAM 5 in accordance with the progression of each melody of the songs A and B in FIG. The results are as shown in FIG. Also, in step M26, CH1, CH
When the data end of 2 is determined, step M2
8, an end mark is written at the end of the CH3 data, and the mixdown process ends.
In FIGS. 8A and 8B, the numbers 0, 1, . . . indicate the counts of the counter 41.

In the above embodiment, the number of channels of the memory for storing melody information and the like is three, but it may be four or more. Furthermore, instead of using one memory as a plurality of channels, a plurality of memories may be individually provided. Furthermore, when mixing down the contents of each memory area and storing musical tone information in one memory area, the musical tone information of other memory areas can be mixed down to the memory area that stores the original musical tone information by adjusting the timing information. It may be memorized.

〔Effect of the invention〕

As explained above, according to the present invention, the plural pieces of piece information read out are mixed down according to the time order indicated by the respective time information, so that digital multiplexing is possible. Recording can be made possible.

[Brief explanation of drawings]

FIG. 1 is an overall circuit configuration diagram of an electronic musical instrument according to an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of the recording section 8.
3 is a diagram showing a flowchart of recording processing of melody information, FIG. 4 is a storage state diagram of melody information shown in FIG. 8A in CH1 of RAM 5, and FIG.
6 is a detailed circuit diagram of the playback unit 9, FIGS. 6A and 6B are flowcharts showing the reproduction processing of the melody information, and FIG. 7 is the storage of the melody information shown in FIG. 8B in CH2 of the RAM 5. FIGS. 8A and 8B are diagrams showing musical scores of the two types of melody information, FIG. 9 is a detailed circuit diagram of the mixdown section 10, and FIG. 10 is a flowchart explaining the operation of mixdown processing. The figure shown in FIG. 11 is a diagram showing the storage state in CH3 of the RAM 5 after mixdown processing. 1...Keyboard switch section, 1A (BSW)...Reset switch, 1B...Reverse switch (reverse switch), 1C...Record switch, 1D...
...End switch, 2...CPU, 3...Musical tone creation section, 4...Stereolocation control section, 5...RAM, 6R,
6L...Speaker, 7...Address register section,
8...Recording section, 9...Playback section, 10...Mixdown section, 11...PR latch, 14...Subtractor,
17...up/down counter, 18...tempo oscillator, 19...tempo volume, 21, 22,
26...Flip flop, 28...NE latch, 30...Full adder, BSW...Forward switch, CSW...Tempo acceleration switch, DSW...Slow tempo switch, ESW...Tempo switch,
FSW...Normal switch, 41...Counter,
42... Matching circuit section, 43... Subtractor, 44...
Latch, 45... Adder, 46, 47... Latch, CH1, CH2, CH3... Each channel of RAM5.

Claims (1)

[Claims] 1. A music information storage means 5 for storing music information consisting of musical sound information input from the musical sound information input means 1 and time information indicating the time when the musical sound information was input.
and a music information reading/writing means 2 for reading/writing the music information to the music information storage means; and at least two pieces of music information read by the music information reading/writing means.
a new music information creation means 10 for creating new music information in which the at least two pieces of music information are mixed down according to the temporal relationship indicated by the respective time information; and the music information reading/writing means. The music information synthesis device is characterized in that, in addition to reading the at least two pieces of music information, the new music information created by the new music information creation means is written into the music information storage means. . 2. The musical piece information synthesis device according to claim 1, wherein the musical tone information comprises pitch information of musical tones and information indicating the start or stop of pronunciation of musical tones. 3 The musical tone information storage means has a plurality of storage areas for storing the musical piece information, and the musical piece information reading/writing means reads the new musical piece information created by the new musical piece information creating means, Claim 1 or 2, characterized in that the music information is written in a storage area different from the storage area in which the at least two pieces of music information are stored, out of a plurality of storage areas of the music information storage means. music information synthesis device.