JPH01315793A - Automatic playing device - Google Patents

Abstract

PURPOSE:To perform correction in a short time by making reverse sound production by reading out musical sound information recorded in a memory in an opposite direction so that a point to be corrected can be searched in a short time and newly inputting the musical sound information after canceling the reverse sound production in finding the point to be corrected. CONSTITUTION:A sound recording state can be stated immediately while a melody recorded in a sound recording section 8 is reproduced by making rewinding by operating a reverse switch 1B and a key operation in the course of sound reproduction. In other word, when a key 'ON' is discriminated, a process for shifting to the sound recording state is performed. A full-adder 30 tentatively executes subtraction for subtracting the current time data of a RAM 5 from the cumulative time data of an NE latch. Then the NE latch latches the newly calculated time data and transfers the data to a PR latch 11. The full-adder 30 is returned to the adding operations and a subtracted result of a subtractor 14 is written in the RAM 5 so as to advance the address by one. Thus the correction can be performed smoothly and a new sound recording information inputting state is set in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic performance device that performs automatic performance by reading musical tone information stored in a memory.

[Prior Art] Traditionally, users have been able to freely perform ``musical performance related to one movement''.
Preset information into memory in real time.

An automatic performance device is known that performs automatic performance by sequentially reading out the preset musical tone information.

However, in this type of automatic performance device, if the user makes a mistake in inputting musical tone information, the user will write down the address to the beginning of the musical tone information input so far, that is, to the beginning of the memory, and then
Furthermore, musical tones are emitted based on the previously inputted musical tone information, and if the musical tone information is entered at an incorrect location, the musical ax information is corrected by re-inputting the musical tone information from that location.

[Problems with the prior art] Therefore, once the user makes a mistake in inputting musical tone information, it is necessary to return the address to the beginning of the musical tone information input so far, that is, the beginning of the memory, which takes time. Since musical tones are emitted based on the musical tone information inputted up to that point from the beginning of the musical tone information to the point where the musical tone information was input incorrectly, there is a problem in that it takes even more time.

In addition, when a musical tone is emitted to search for a location where the 2ff information should be corrected as described in , when the musical tone is emitted to search for the location where the 2ff information should be corrected, immediately when the location where the 2ff information should be corrected is reached, the musical tone information is immediately changed from the musical tone emission state. to the recording state of
There is also a problem in that it is difficult to input musical tone information continuously in terms of timing.

[Object 1 of the Invention] This invention has been made in view of the above-mentioned problems, and an object thereof is to provide an automatic performance device that can smoothly modify input musical instrument information in a short period of time. shall be.

[Summary of the Invention] In order to achieve the above object, the present invention first of all has the following features:
By reading out the musical tone information recorded in the memory in the reverse direction, it is possible to perform reverse sweating of the musical tone, thereby reducing the time required to search for a correction point.Secondly, when a point to be corrected is found, , just by canceling this reverse sound emission, 1
If you switch to the normal musical tone release state and input new musical tone information in this normal musical tone release state, the musical tone output state immediately shifts to the musical tone information recording state and the newly input musical tone information is input. By making it possible to record musical tone information,
The main point is to facilitate the timing of inputting new musical tone information when correcting musical tone information.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings. 1st
The figure is a circuit diagram showing the overall configuration of an electronic musical instrument equipped with an automatic performance function. The keyboard switch section l is equipped with multiple keys and various switches for obtaining various effects such as tone, vibrato, sustain, stereo sound localization, normal rhythm, fill-in rhythm, automatic accompaniment, and automatic performance. A switch is provided for 6 e.g.

These include a recent switch IA, a reverse switch IB, a record switch IC, an end key ID, etc., and their functions will be described later. And CPU・(central processing unit)
2 periodically outputs a key scan signal via the pass line Bl to scan the keyboard switch section l, and in response, the keyboard switch section l outputs output signals from the six keys and switches. and is sent to the CPU 2 via the pass line B2. In response to this, for example, the CPU 2 gives musical sound generation command information to the music 1-key creation section 3 via the pass line B3, causes it to create a musical sound signal of a melody or automatic accompaniment, and supplies it to the localization 1tjj control section 4. . tacPU2 is! Describe! Control information according to the a image localization information preset in the RAM (77 dumb access memory) 5 is output to the pass line B4 and given to the sound image localization control section 4, and the sound image localization for the Moeki Music #1 signal is performed. is set, the corresponding signals are output to the left and right speakers 6R16L, and musical tones are emitted.

The RAM 5 reads data and -! ) are controlled. Data is exchanged between the CPU 2 and the RAM 51ii1 via the pass line B6. in this case,
RAM5 contains the pitch of the song.

Musical sound information indicating B length and rests (hereinafter referred to as melody information as appropriate), and performance information for obtaining various effects such as tone, vibrato, sustain, sound image localization, and fill-in rhythm on/off are different. Each area is memorized.

The address register section 7 is provided with independent address counters for each of the melody information and the performance information, so that during automatic performance, the melody information and the performance information are set according to the progress of the melody. , are read out simultaneously in parallel, allowing for automatic performance. In this embodiment, three areas are provided for storing melody information.

The recording section 8 receives the last 1 river information (data D7 to DO) received from the CPU 2 via the pass line B7 and the +1 raw section 9.
Maki+111 f given via the pass line Bll from
Good news (data T D 7 to T D O) Karat &
The time information (data I7 to IO) representing the data is created and supplied to the CPU 2 via the pass line B8.

It is written into the RAM 5 as the melody information or performance information.

The playback unit 9 receives information from the CPU 2 via the pass line B9 according to the melody information and @performance information read from the RAM 5 during playback, creates data for i++ raw processing, and sends the data to the pass line BIO. Intermediate CP
In addition to U2, as mentioned above, when recording,
Time information is given to the recording section 8. Note that the CPU 2 is a processor that controls all operations of this electronic musical instrument, and a detailed explanation thereof will be omitted.

The mixdown unit 10 is configured to perform different areas (
This is a circuit that performs a process of synthesizing information written in different channels (also referred to as different channels) and writing it into any one channel. In that case, necessary data is exchanged between the mixdown section 10 and the CPU 2 via the pass lines B12 and B13, details of which will be described later. Note that when the composite data obtained by the mixdown process of the mixdown unit 10 is input to any channel of the RAM 5, an address register (referred to as ADRM) for addressing that channel is provided in the address register unit 7. It is being

Next, the configuration of the twelve sweat sections 8 will be explained with reference to FIG. P
The R latch 11 normally has an up
/ d o w n counter count output data TD7~
The signal LAT is input as TDO through the transfer gate group 12, and is latched when the CPU 2 outputs the signal LAT. Furthermore, when the playback operation is temporarily stopped during playback, rewinding is performed by operating the reverse switch IB, and then recording is started anew, the latch data of the PR latch 11 is transferred to the playback unit 8 via the CPU 2. The output data of the full adder at that time is sent to the full adder to be described later, and conversely, the output data of the full adder at that time is sent to the data D7 via the CPU2.
~DO, the PR latch 11 is further latched via the transfer gate group 13. And PR Lunch 11
The latched data is sent to the B input terminal (B7) of the subtracter 14.
~BO). Further, the data TD7 to TDO are input to the A input terminals (A7 to AO) of the subtracter 14. Then, the subtracter 14 subtracts the input data of the B input terminal T from the input data of the A input terminal, and as a result, the data
7-IO is sent to the RAM 5 via the CPU 2 and stored therein. In the case of melody information, the data (7) to (4) indicate time data giving the key-on time and key-off time, while in the case of the performance information of the effect, they are time data indicating the generation period of the effect. Note that the transfer gate n12 has the signal CM output from the CPU 2 applied to its gate via the inverter 15.

Further, the transfer gate group 13 is gate-controlled by directly applying the signal CH to its gates.

Next, the configuration of the reproducing section 9 will be explained with reference to FIG. The up/down counter 17 is an 8-bit counter, and when the CPU 2 starts recording or playback, especially after being cleared by outputting the clear signal CLR,
A counting operation is performed to count clocks based on the signal output by the tempo oscillator 18.

The frequency of the oscillation output of the tempo oscillator 18 is variable by a tempo volume 19, and the output of the tempo oscillator 18 is input to an analog game 20. The output of the tempo stop switch ESW is manually connected to the other end of the AND gate 20 for gate control, and the output of the AND gate 20 is connected to a T-type flip-flop 21.
And the transfer gate 23 is manually operated. Further, the set output of the flip-flop 21 is input to a T-type flip-flop 22 and a transfer gate 24. Furthermore, the set output of the flip-flop 22 is input to the transfer gate 25.

The outputs of a tempo acceleration switch CSW, a normal switch FSW, and a slow tempo switch DSW are applied to each of the transfer gates 23, 24, and 25, each of which is a double lock type switch in which only one is in the on state. and gated. Each output of each transfer gate 23, 24, 25 is counted by the up/down counter 17 as the clock.

Thus, the flip-flops 21 and 22 form a frequency dividing circuit, and the flip-flop 2
Each output of 1.22 has a frequency of l/2. l/4
It becomes.

The up-count operation and down-count operation of the up-down counter 17 are controlled by the flip-flop 2.
This is done by the set output signal UPDOWN of 6.

That is, the set input terminal S and reset input terminal R of the flip-flop 26 are respectively input with the outputs of a forward switch BSW and a reverse switch ASW (same as the reverse switch IB in FIG. 1), which are two locking type switches. are doing. Then, each bit output of the jlp/dOWn counter 17 is sent to the corresponding exclusive OR gate 277-27.
In addition to being manually inputted to each end of the data o, the data is sent to the recording section 8 as data TD7 to TDO. Also exclusive or game) 277
Each other end of ~27o has an 18-bit NE latch 2.
8 corresponding bit outputs are input. and exclusive or gates 277 to 27 (each output of l is the nor gate 2
9, and the output of the NOR gate 29 is further supplied to the CPU 2 as a -negative signal. That is, exclusive or gate 2
7r to 27o and NOR gate 29 form a matching circuit.

The NE latch 28 connects the S output terminals S7 to SO of the full adder 30 when the CPU 2 outputs a latch clock.
The result data of addition or subtraction from is latched. Further, the NE latch 28 is cleared by applying a clear signal CLR output from the CPU 2 at the start of a recording operation and a reproduction operation. The latched data of the NE latch 28 is returned to the input terminals A7 to AO of the full adder 30 via the transfer gate group 31 and input thereto. In addition, exclusive OR gates 32 are connected to the B input terminals B7 to BO.
Outputs 7 to 320 are input, and carry input terminal 7-
The output of the AND gate 33 is connected to the inverter 34 at CI N.
．． It is input via the transfer gate 35. Therefore, exclusive or gates 321-32. After the time data from the PR latch 11 in the recording section 8 is rewound during playback, it is input to each end of the recorder 8 in response to a key operation when performing a new recording ff operation for correction iE. Further, the output of the AND gate 33 is applied to each other end via an inverter 34 and a transfer gate 35.

The set output of the flip 70 knob 26 and the signal R output from the CPU are input to the AND gate 33. This signal R is normally output as "t", and is temporarily output as "0" when the previous recording agency is corrected. The output of the AND gate 33 is then sent to the CPU 2. Further, the transfer gate group 31 and the transfer gate 35 are gate-controlled by the signal CHH output from the CPU 2, but this signal CHR is a signal output from the CPU 2 as a temporary value of 0 when making corrections during recording. be. Furthermore, the transfer gate group 31
The latch data of the NE latch 28 output from the NE latch 28 is sent to the PR latch 11 when data is corrected during reproduction.

Next, the specific configuration of the mixdown section 10 will be explained with reference to FIG. The counter (also abbreviated as CNT) 41 is cleared by a clear signal CLR output from the CPU 2 at the start of the mixdown process, and then inputs a +1 signal output from the CPU 2 to execute a counting operation. The capacity is 8 bits, and the counting output is sent as time data to the A input terminal of the matching circuit section 42, the A input terminals A7 to AO of the subtracter 43, and the latch (LA).
(also abbreviated as STT) 44 LI input terminals LI7 to LI
Input each to O. The latch data of the latch 44 is applied to the B input terminals B7 to BO of the subtracter 43 via the L output terminals L7 to LO. The subtracter 43 subtracts the input data to the B input terminal from the input data to the A input terminal, and outputs the time data of the difference to the 0 output terminals 07 to 0.
It is output from O and written to the specified channel in the RAM 5 as one of the composite data.

Time data from two channels to be mixed down in the RAM 5 are read out and applied to the A input terminal of the adder 45. Further, a latch (also abbreviated as NEXTI) for one of the two channels is provided at the B input terminal or the C input terminal of the adder 45, respectively.
The time data latched by 46 or the time data latched by latch (also abbreviated as NEXT2) 47 for the other channel are input, respectively. and adding section 4
5 adds the manual data to the A input terminal and the input data to the B input terminal or the input data to the C input terminal, and outputs the resulting data as new time data from the D output terminal or the E output terminal, respectively. output and latch the latch 46 or latch 47. Note that the latches 46 and 47 perform the latch operation when the CPU 2 outputs the signals LAI and LA2, respectively. Furthermore, at the start of the mixdown process, the latches 46 and 47 are also cleared together with the counter 41 by the clear signal CLR output by the CPU 2.

Each latch data of the latches 46 and 47 is stored in the matching circuit section 42.
to the B input terminal or C input terminal respectively.

applied. Then, the coincidence circuit section 42 detects coincidence or mismatch between the input data to the A input terminal and the input data to the B input terminal in response to this, outputs a coincidence signal E1, and outputs the coincidence signal E1 to the CP.
In addition to sending it to U2, it also detects whether the input data to the A input terminal and the manual data to the C input terminal match or do not match, and outputs a match signal E2 and sends it to the CPU 2.

Next, two of the melody progressions shown in Figures 8 (A) and (B), respectively.
The operation of recording and playing back one song to the RAM 5 will be explained. First, the case of recording will be explained. In this case 1, for example, the melody information of the song shown in FIG. 8(A) is first recorded by key operations on the keyboard switch section 1, and FIG. 3 is a flowchart illustrating the recording operation of this melody information. Note that the numbers θ to 17 in FIG. 8 correspond to the counter 4.
1 count output is shown.

To start recording, a recording start switch (not shown) of any channel (for example, the first channel (CHI)) is turned on. The output is then input to the CPU 2 via the pass line B2.

In response, the CPU 2 performs step RMI in the flowchart of FIG. 3, that is, sends the clear signal CLR to the pass line B7. B9 and PR latch 11.
NE latch 28. The up/down counters 17 are cleared to 0. Then, the CPU 2 clears the address counters for the first channel (CHI) in the RAM 5 in which the melody information of the song shown in FIG. 8(A) in the address register section 7 is to be written. 7 address control information for setting the start address is output to the path line B5 and set (step RM2).Next, the CPU 2 outputs data NOP to the path line B6 to
The storage state is schematically shown in FIG. 4. Then this data NOP (NO0PE
RATION) is a data similar to a rest that does not perform work H'T 1"f. 1 or more is the processing of step RM3. Then, the CPU 2 registers the 7 address counter C of the address register section 7. The following is simply an address register) is incremented by 1 in step RM4 to set address 1, and then the reset switch I
A process for determining whether or not A is turned on is performed in step RM5. The reset switch IA is a switch that is turned on when performing recording correction, and when turned on, the reset switch IA is set to the initial state, contrary to the process of step RMI. On the other hand, when it is not turned on, step R
Proceeding to M6, it is determined whether the end key ID has been turned on. This end key 1'D is a switch for writing an end code at the end of the melody information inputted to R'A'M5 by pushing the melody information input end 'T verse. When the end key ID is turned on (YrYESJ), the process proceeds to step RM7] and two consecutive processes are executed. However, now the end key ID is not turned on (N rNOJ)
, proceeds to step RM8, and reverse switch IB (
A process for determining whether the reverse rotation switch (ASW) is turned on is executed. Then when it was turned on.

Processing for moving to a recording standby state in step RM9 is executed, and this processing will be explained in detail later.

Now, of course, the reverse switch IB is turned on, and the process proceeds to step RMIO, where it is determined whether or not the key has been operated. Then, until the two keys of the two first tones (each tone of note ic3゜03-) of the melody in Figure 8 ('A) are turned on at the same time as the recording start switch and the playing of the chord melody begins. is step RMIO1RM5, R
M6, RM8. RM, IOl... are repeated.

When the keys C3 and C31 are turned on at the same time, the process proceeds to step RMII, where a process for determining whether the key is depressed or released is executed.Since the keys are depressed, the process proceeds to step RM12,
PU2 first inputs the MSB of the key code to indicate that it is the key code and key press data for pitch 03 on the bass side.
Musical tone information is calculated by adding data "0" to the most significant bit. And pass it to B3
is given to the Raku lip creation section 3 to start emitting sound from the speakers 6R'' and 6L (step RM13), then step R.
Proceeding to M16', the CPU 2 sets the signal CH to "0" to keep the transfer gate group 12 always open and the transfer gate group 13 always closed during normal times after the start. As a result, the playback unit 9 inputs the above-mentioned step RMI clearing process and clock at the set tempo, and performs a counting operation (note that the forward switch BSW is currently turned on and the flip-flop 26 is set, count operation is in progress) is already in progress
The count output (time data) of the p/dow n counter 17 is sent to the pass line B as data TD7 to TDO.
11. ) through the transfer gate group 12 to the A input terminal of the PI'19 latch 11 and the subtracter 14; The input data from the PR latch 11 is subtracted and the result is output to the CPU 2 as time data.Then, the process of step RM17 is executed.
The PU 2 applies a signal LAT to the PR latch 11, causing the PR latch 11 to latch the data being manually input, and subsequently causes the latched data to be held and applied to the B input terminal of the subtracter 14.

Next, the process proceeds to step RM1B, where the time data (the input data to the input terminals of the subtractor 14 is the same (a), so the resulting data ■7 to IO at that time are "O").
) is written to the address 1 of the RAM 5. Next, the address register is incremented by 1 and address 2 is set (step RM
19), and the already calculated key press code, that is, the key code (C3) and the key press data (rONJ) are written in the 21R area of this RAM 5 (step RM20).
. Then, the address register is incremented by 1 to set address 3 (step RM2), and the process returns to step RM5.

Next, steps RM5, RM6. RM8, RMlO~R
M13. By each process of RM16 to RM21, time II+j
The process for the key of pitch C31 that was turned on is executed in the same way, and the time data rQJ is stored at 3JI of CHI in RAM5.
is written, and a key code (C31) and key press data (rONJ) are written at address 4. The address register is then set to address 5, and the process returns to step RM5. Thus, two musical tones with pitches C3 and C3g are emitted simultaneously as a chord.

Next step RM5. RM6. Step R via RM8
When the MIO determines that the key has been released for pitch C3-, the process proceeds to step RM14, where the key code is changed to indicate that it is the key code and key release data for pitch C3-. A process of adding data rlJ to MSH is executed to create a key release code. Then, it is sent to the musical tone creation section 3, whereby the musical tone of the pitch C3M is muted (step RM15).Next, when the process proceeds to step RM17 via the step RM16, the PR latch 11
The time data of the up/down counter 17 at the time of the key release operation is newly latched, held thereafter, and applied to the B input terminal of the subtracter 14. and subtractor 14
subtracts the clock data when the key of pitch C3g, which was being input to the B input terminal, is pressed from the clock data input to the A input terminal when the key is released, and obtains the resulting data. Write time data to address 5 of RAM 5 (step R
M18), in this case, as shown in FIG. 4, Suzuma data at this time is "5", and step RM19.
As shown in FIG. 4, each process of RM20 causes RAM5 to
The key release code is stored at address 6 of . Then, in step RM21, the 7# ground is designated, and the process returns to step RM5.

Next, when the key of pitch B3 of the second musical tone is pressed.

This is determined in step RMI,0, and step R
Proceed to step RM12 via MII.

The key press code is calculated in the same manner as for each key operation poem of pitches C3 and C3-. Then, through the process of step RM13, creation and sound emission of the musical tone n jib B3 is started. Then, step RM16. By each process of RM17°RMlg, the PR latch 11 is set.

+1'J? i! , 'u The time data when the pitch B3 key is pressed is latched, and the subtracter 14 calculates the separation of the pitch C3g from the time data when the pitch E3 key is pressed to the A input terminal to the B input terminal. Data is obtained as a result of subtracting the clock data of the key time, and is stored in address 7 of the RAM 5. In this case, as shown in FIG. 4, the time data based on the result data is rlJ. Also.

After the processing in step RM20, the next 9th address of RAM5 is specified in step RM21, and step RM5
Return to

Thereafter, when the melody is played at time intervals according to FIG. 8(A), the same processing as described above is performed.

Below 9fIi of CHI in RAM5, melody information for the third tone and below is written.When the last performance input is completed, turn on the end key ID and write the end code to RAM5 as the last data of melody information. Write it as .

Next, the process of step RM9 when the reverse switch IB is turned on will be explained. This reverse switch I
B (reversing switch ASW) is turned on when a key is pressed incorrectly when inputting the melody information, returns the address register section 7 to the desired address, and sets the correct melody information to a standby state where it can be recorded. In that case, when the reverse switch IB is turned on, the latch data of the PR latch 1.1 at that time is C.
It is latched by the NE latch 28 of the IIf generating section 9 via the PU2.

After writing the melody information in FIG. 8(A) to CHI of RAM 5 as described above, while playing back and listening to the melody information in FIG. 8(A), The melody information of the song is transferred to the second channel of RAM5 [hereinafter CH2
In this case, the recording process (
That is, the processing in the flowchart of FIG. 3) is the same as that described above, and as a result, the
In the state shown in the figure, the melody information of the song shown in FIG. 8(B) is written.

Therefore, first, the melody ILT raw processing operation will be described with reference to the flowcharts of FIGS. 6(A) and 6(B).

First, when the ILT raw switch for CHI in RAM 5 is turned on, a clear signal is output through the processing of step SMI, and the NE latch 28 and up/do in FIG.
When both the w and n counters 17 are cleared, the leading address for the melody information shown in FIG. Processing data rNOPJ (see FIG. 4) is then read out from the RAM 5, and C
The data r
The process of determining whether the MSB of NOPJ is "0" or "l" is performed in Stella 7"5M5, but in this case, since the data is rNOIJ, which is similar to a rest, the process proceeds to step SM7 and the message is sent to the musical tone creation section 3. outputs a control signal equivalent to a key-off signal and prohibits execution of musical tone creation, and
Proceeding to step SM8, the time data "0" is read from address 1 of the RAM 5, and address register 7 is incremented by 1 to set address 2 (step 5M9). The resulting data is then latched into the NE latch 28 (step SMIO1SMI 1). In this case, the forward switch BSW is currently turned on, and as a result, the flip-flop 26 is turned on. In the set state, the AND gate 33 is opened, and up/do
The wn count 17 is given an up-count command. The signal R is normally output as "l", so the output of the AND gate 33 is normally "1".
When the signal is supplied to the CPU 2, the output of the 4-inverter 34 normally becomes "O" and is sent to one end of each of the exclusive OR gates 32+ to 32o and the carry input terminal CIN of the full adder 30, respectively, to the transfer gate 3.
5. Note that the signal CHR is normally “l”.
Therefore, the transfer gate 35 and the transfer gate group 31 are normally open.

Therefore, in the step SMIO1SMII, the time data "0" is input to the B input terminal of the full adder 30 as it is without being inverted by the exclusive OR gates 321 to 32o. - On the other hand, the output data (8-bit all "θ" data) of the NE latch 28 is input to the A input terminal via the transfer gate group 31, so the full adder result data at that time is "0".
It will be latched to ME latch 2B.

Next, in the judgment process of step 5M12, the Noah gate 29
It is determined whether or not the coincidence signal from is output at "L" level. In this case, exclusive or gate 277-2
The 8-bit all "θ" data of the up/down counter 17 and the 8-bit all "0" latch data of the NE latch 28 are input to 7o, respectively.
1'' level coincidence signal is supplied to the CPU 2, the process proceeds to step 5M13, and it is determined that the up-counting operation is in progress, and the process proceeds to step SM3.

Next, in step SM3, the key code "C3" and the key press data "0" are obtained from the 2nd address of CHI in the RAM 5, that is, the 4th
Data rC3 and ONJ shown in the figure are read out and input to the CPU 2, and address 3 of CHI in the RAM 5 is set in step SM4.

Then, in step SM5, the key press data "0" is determined, and the process proceeds to step SM6, where a key code "C3" and a key-on signal are given to the musical tone creation section 3. As a result, as shown in FIG. Pitch C of the first musical note of the melody shown in
The musical tone No. 3 is first played back, and the speakers 6R and 6L start emitting the sound. In the next step SM8, time data "0" is read from address 3 of CHI in the RAM 5, and in step SM9, address 4 in the RAM 5 is set. And the time data rQJ is as it is,
It is applied to the B input terminal of the full adder 30. On the other hand, the time data rOJ being latched by the NE latch 28 is being input to the input terminal f of the full adder 30, and therefore the addition result data of the full adder 30 at that time is the time data "
0'', and in addition to being newly latched into the NE latch 28, it is also applied to the exclusive OR gates 277-27o (step SMI 1), and step 5M
The process proceeds to step 12, where it is determined whether or not the coincidence signal is output at the "L" level.The process then proceeds to step SM3 via the step 5M13 in order to output the coincidence signal at the "1" level. Then, in step SM3, the data rc3g and ONJ shown in FIG. 4 are read from address 4 of CHI in RAM5.
The address is set, and the musical tone of pitch C31 of the first musical tone is simultaneously started to be emitted as a chord together with the musical tone of pitch 03. In each process of steps SM8 to 5M1l, CHI of RAM5
The time data "5" is applied as is to the input terminal of the full adder 300B from which it was read from address 5, and at that time, the time data "0" is being input to the A input terminal.
Therefore, time data 5, which is the result data, is NE
It is newly latched into the latch 28. Further, CHI of RAM 5 is set to address 6. And step 5M
12, and then proceeds to step 5M14 until the match signal of l''' level is output, and the up/p/
It is determined whether or not the d o w n signal is inverted, that is, in this case, whether the reversing switch ASW is turned on.
Since it is not turned on and is rNOJ, step 5M18
The process proceeds to step 5M20, where it is determined whether or not the melody information is being corrected and recorded. Since the answer is "NO", the process further advances to step 5M20, where it is determined whether or not the reset switch IA has been turned on, which is also "NO". Therefore, each process returning to step 5M12 is repeatedly executed.

Then, when the length of the time data "5" has elapsed from the start of the simultaneous sound generation of the first tones of the key codes rC3 and C31J, and a coincidence signal of the "1" level is output, step 5M
13, the process proceeds to step SM3, and the RAM
Key code rc31J and key release data "l" from 6i of 5
", that is, data rc31, OFF" in FIG. 4 is read out. Further, in step SM4, address 7 of the RAM 5 is set. Then, in step SM5, the key release data "1" is determined, and the process proceeds to step SM7, where a key-off signal "key code rc31" is given to the musical tone creation section 3, and a key-off signal "key code rc31" of the first musical tone is given. At step SM8, the RAM is
The time data rlJ is read from address 7 of RAM 5, and address 8 of RAM 5 is set in step SM9. Then, by steps SMI O and SMI l, the time data rlJ is input directly to the B input terminal of the full adder 30, and at this time, the time data "5" of the previous result data is input to the input terminal. Therefore, the addition result data output from the full adder 30 is "6", which is N
In addition to being newly latched by E latch 28, it is also applied to exclusive OR gates 27-27o. Then, the process proceeds to step 5M12, and until the count value of the up/down counter 17 increases to time data [6] and a coincidence signal of "1" is output, the process proceeds to step 5M14.5M described above.
18.5M20, 5M12. . . . each process is repeated, and during this time, the pitch IC3 of the first musical tone is
The musical tone of 1J is muted, and only the musical tone of pitch "C3" is produced. When a match signal of "L" level is output, the process proceeds to step 5M13, and further proceeds to step SM3.

The reproduction processing for the two first musical tones of the chord is thus completed, and thereafter the reproduction processing for the second musical tone ff is started in the same manner as described above. Then, while the first musical tone is being reproduced as described above, it is played according to CB in FIG. 8, and the melody information of the tune is input to CH2 of the RAM 5.

On the other hand, it is possible to rewind by operating the reverse switch IB in the middle of fi and ff, and then to perform a key operation while the sound is being reproduced to immediately shift to the recording state. That is, in step 5M19, key-on is determined, and the process advances to step 5M21, where processing for transitioning to the urT state is performed. In other words, the full adder 30 temporarily executes a subtraction operation, subtracts the current time data in the RAM 5 from the cumulative time data latched in the NE latch 28, and causes the NE latch 28 to latch the result.
The latch data of this NE latch 28 is transferred to the PR latch 11. Then, after returning the full adder to the addition operation, the subtraction result is stored in the RAM 5 of the subtracter 14, the key press code of the currently keyed-on key is written at the next address, and the address is further incremented by one. Thereafter, the process proceeds to RM5 in FIG. Next, as described above, RAM5
Figures 8 (A) and (B) recorded on CHI and CH2, respectively.
) will be synthesized by the mixdown process of the mixdown unit 10, and the process will be described, for example, in which the two songs are recorded in the area of the third channel (hereinafter referred to as CH3) of the RAM 5. FIG. 1O shows a flowchart for this purpose.

First, when you turn on the switch for mixdown,
Step M1 of flowchart □ in FIG. M2, M
3 and M4 are respectively executed, and the counters 41 . Latch (NEXTI) 46, Ra-/+
(NEXT2) 47, Latch (LASTT)
44 are reset together (see FIG. 9).Next, by each process of steps M5 and M6, the address counter (ADRI and a
ll) The first address (address 0) is preset to the address counter (abbreviated as ADR2) for CH2.
Next, in step M7, the start address is also set in the address counter (abbreviated as ADRM) for the CH3.

In the next step M8, the matching circuit section 42 determines whether the data of the latch 46 and the count output of the counter 41 match, and now both data are "
0'', and the coincidence signal El of the ``l'' level is output and supplied to the CPU 2.Therefore, the CPU 2 starts the process of step M9 and collects the result data of the subtracter 43, that is, the counting output of the counter 41. The data "0" obtained by subtracting the data "0" of the latch 44 from "0" is written to the area at address 0 of CH3 (see Figure 11).
The count output "0" of 1 is set in the latch 44 and held as the data of the song (step MIO), and in step Mll, the ADRM is incremented by 1 to become address 1, and then the IIk of fcH3 is Data rNOPJ at address 0 according to the ADRI of CHI is read and written to the address (step M12), and ADRI is +
1 and the 1st address is set (step M13), and then the time data "O" at the 1st address of CHI is read out and added to F.
81! is applied to the A input terminal of 45 and added to the time data "0" of the latch 46 to the B input terminal, and the resulting time data "0" is latched again to the latch 46 (step M14). ADRI is incremented by +1 to set the 2# address (step M15), then ADRM is incremented by +1 to become the 2nd address (step M16), and step M8
Return to

Next, in step M8, it is determined that the negative signal El of "1" is still being output, and the process proceeds to step M9.
c7) 2 of CH3. The subtraction result data rOJ of the subtractor 43 is written at the % location. Then, the count output "0" of the counter 41 is latched again in the latch 44 (step MIO), ADRM is incremented by 1, and address 3 is set (step M11). Data [C3°ONJ] from location 2'#i of CHI is read and written to address 3, and ADRI
is increased by +1 and address 3 is set (step M13) 0
Next, in step M14, the adder 45 adds the latch data "0" of the latch 46 to the time data "0" at the 3rd address of CHI, resulting in time data "0", which is latched by the latch 46. 0 Next, in step M15, A
DRI becomes address 4, and in step M16, AD
RM will be number 4. Then, the process returns to step M8.

In this step M8, the output of the negative signal E1 of .degree.1'' is still determined, and the process proceeds to step M9 again.Then, in steps M9 and MIO, respectively.

The result data rOJ of the subtracter 43 is loaded into address 4 of CH3, and data "0" is latched into the latch 44 again. Next, in steps Mll and M12, address 5 is set, and then data r from address 4 of CHI is set at address 5.
c31, ONJ is read and written 0 then AD
RI is +1 and it is 51FtJ1! ! is set (step M13), and then in step M14 the latch 46 is set to CH
The time data "5" from address 5 of I is read out and added to the time data rQJ of the latch 46, and as a result, the data "5" is latched into the latch 46. Then, step M15. In M16, both ADRl and ADRM are set to address 6, and the process returns to step M8.

In this step M8, a negative signal E1 of "0°" is determined due to the mismatch between the data of the counter 41 and the latch 46, and the process proceeds to step M1-7. Then this step M
17 executes the same process as step M8 above on CH2 of the RAM 5. That is, the coincidence circuit section 42 detects a coincidence between the count output rQJ of the counter 41 and the latch data r(N of the latch 47). It makes a judgment and outputs a negative signal E2 of “l” and gives it to the CPU 2. As a result, the CPU
At U2, an instruction is given to proceed to step M18. At the stamen,
Following steps M18, Ml9. M2O, M21. M2
2, M23, M24, and M'25 are the steps M9, MIO, and Ml for the serious offender CHI.1. Ml2. M
l3, Ml4. They correspond to Ml5 and Ml6, respectively.
Processing similar to CH1 is executed for CH2.

That is, in step M18, the subtracter 43 is placed at address 6 of CH3.
As a result, data "0" is written, and in step M19, data rQJ is latched into the latch 44. And step M20. M21 sends data rNOP from address 0 of CH2 shown in FIG. 7 to address 7 of CH3.
is read and written to the 0th order, ADR2 is incremented by 1 and set to address 1 (step M22), and step M2
3, the time data "4" at address 1 of CH2 is read out and added to the data rQJ of the latch 47 in the adder 45, and as a result, the data "4" is latched in the latch 47. Then, in step M24°M2S, ADR2
is set to address 2, ADRM is set to address 8, and the process returns to step M17.

In step M17, due to the mismatch between the data "0" of the counter 41 and the latch data "4" of the latch 47, "θ"
" - negative signal E2 is determined, and the process proceeds to step M26, where it is determined whether or not it is the data end of CHI and CH2, based on the presence or absence of the end code of each channel. Therefore, it is not the data end, and the process proceeds to step M27. CPU
2 outputs a +1 signal to the counter 41 to make its count output rlJ, and returns to step M8.

In this step M8, it is determined that the count output "l" of the counter 41 and the latch data "0" of the latch 46 do not match, and the process proceeds to step M17.
However, it is determined that there is a mismatch, and the process proceeds to step M26, and further, in step M27, the counter 41 is incremented by 1 and becomes "2".
Then, the process returns to step M8.

Hereinafter, until the value of the counter 41 matches the data "4" of the latch 47, steps M8 and M17 of l1ii are performed.
．． M26 and M27 are each executed twice.

Then, (Iff of the counter 41 becomes "4". Through step M8, a match is detected in step 2 M17, and in step M18, the counter 41 is set at address 8 of CH3.
Data f4.'' is subtracted from data ``O'' of tsuchi 44, and the result ``4'' is written. Further, in step M19, the current value "4" of the counter 41 is set in the latch 44-.In steps M20 and M21, data rG3. from address 2 of CH2 is transferred to address 9 of CH3. ONJ is written, and the 3rd address where ADR2 is added by 1 is set (step M22), and in step M23, the time data "2" at the 3rd address of ADR2 is changed to the data "4" in the latch 47. As a result, data "6" is set in the latch 47. And step M24. M25, Ml7. M26. After each process in M27, the process returns to step M8.

The following operation is a repetition of what has been described above, and is shown in Fig. 8 (A
) and (B) are written in CH3 of the RAM 5, and the result is as shown in FIG. 11. Further, when the data ends of CHI and CH2 are determined in step M26.

Proceeding to step M2g, an end mark is written at the end of the data of CH3, and the mixdown process ends.

Furthermore, in Figure 8 (A) and (B), the number 0.1,...
. . . indicates the count value of the counter 41.

In the example described in @, the number of channels of the memory for storing melody information etc. was set to 3, but it may be 4 or more.Also, instead of using one memory as a plurality of channels, the number of channels of the memory is 3. Furthermore, when the contents of each memory area are mixed down and musical tone information is stored in one memory area, the MJ tones of other memory areas can be stored in the memory area that stores the original musical tone information. Information may be stored by adjusting timing information.

[Effect of the Invention 1] As explained above, the present invention makes it possible to emit music RF in reverse by reading the musical tone information stored in the memory in the reverse direction, thereby reducing the time required to search for the corrected part. In addition, once you have found the corrected part in this way, you can simply cancel this reverse sound output and switch to the normal musical sound output state, and in this normal musical sound output state, create a new By making it possible to correct musical tone information simply by inputting musical B'f information, musical tone information can be corrected more quickly and smoothly compared to conventional automatic performance devices. .

[Brief explanation of the drawing]

FIG. 1 is an overall circuit diagram of an electronic musical instrument according to an embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of a recording section 8. Fig. 3 is a flowchart of the melody information recording process, and Fig. 4 is Fig. 8 (A) in RAM 50CHI.
The storage state diagram of the melody information shown in FIG. FIG. 5 is an 11-minute circuit diagram of the playback section 9, and FIGS. 6(A) and (B)
) are diagrams showing a flowchart of the reproduction process of the melody information, FIG. 7 is a storage state diagram of the melody information shown in FIG. 8(B) in CH2 of the RAM 5, and FIG. 8(A)
, (B) are diagrams showing musical scores of the two types of melody information, FIG. 9 is a detailed circuit diagram of the mixdown section 10, FIG. 1θ is a flowchart explaining the operation of mixdown processing, and FIG. Figure 11 shows R after mixdown processing.
It is a figure which shows the memory state diagram in CH3 of AM5. l...SaS switch section, IA (BSW)...
... Reset switch, IB ... Reverse switch (reverse switch), IC ... Record switch, 10 ... End switch, 2 ...
... CPU, 3 ... Musical composition 1&, ff1l,
4... Localization control section, 5... RAM, 6
R16L...Speaker, 7...Address register section, 8...Recording section, 9...
Playback section, 10...Mixdown section, 11...
...PR latch, 14°43...subtractor,
17...up/down counter, 18...tempo oscillator, 19...tempo volume, 21.22.26...flip-flop, 28...NE latch, 30...
...Full adder, 41...Counter, 42.
... Matching circuit section, 44°46.47...
Latch, 45... Adder, BSW...
Forward switch, CSW...tempo acceleration switch, DSW...slow tempo switch, ESW...
...tempo stop switch, FSW...
・Normal switch, CHI, CH2, CH3...
...Each channel of RAM5. Patent Applicant Casio Keiki Co., Ltd. No. 1- Fig. 4 Fig. 6 Fig. 7 (B) Fig. 7 Fig. 11

Claims (1)

[Scope of Claims] Musical tone information inputted from musical tone information input means, consisting of pitch information and on/off information indicating the start or stop of pronunciation;
a storage means for storing timing information indicating the timing at which a musical tone is generated based on the musical tone information; a reading means for reading out the musical tone information and the timing information from the storage means; and an address retraction for reversing the address of the storage means. and the reading means for sequentially reading out the musical tone information and timing information while the address of the storage means is being retracted by the address retraction means and after the address retraction of the address of the storage means by the address retraction means is canceled. and input of new musical tone information from the musical tone information input means when the reading means is reading out the musical tone information and timing information from the storage means under the control of the reading control means. a detection means for detecting the presence or absence of the musical tone information; and a storage control means for controlling the storage means to immediately store the new musical tone information and timing information when the input of the new musical tone information is detected by the detection means. An automatic performance device characterized by comprising: and.