JPS59125788A - Automatic performer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention provides predetermined musical tone information k stored in a memory.
The present invention relates to an automatic performance device that performs automatic performance.

[Prior art]

2. Description of the Related Art Electronic musical instruments that perform automatic performance by reading and reproducing musical tone information in a memory have been developed, but some have not yet been put into practical use.

Musical tone information is stored in the memory in the order of musical scores in accordance with the progression order of automatically performed pieces.

[Problems with conventional technology]

If the rest information is missing at the beginning of the song, that is, if the song can start from a rest, especially if the song is played alone for 111 imms without rhythm accompaniment, the rest information will be There is an undesirable point in VC that a silent state continues for a long time at the start of playback.

[Purpose of the invention]

To provide an automatic performance device f which skips the rest and starts playing the music immediately when the entire automatic performance of a music piece starting from a rest is performed.

[Key points of the invention]

When rest information is read from the beginning of the song in memory, for example, fast forwarding is performed until the musical tone information of the first musical tone that is written next to this rest information and to be sounded starts to be read out. This is a store that has the means to do this.

〔Example〕

Embodiments of the present invention will be described below with reference to all the drawings. FIG. 1 is a circuit diagram showing the overall configuration of an electronic musical instrument equipped with an automatic performance function. Keyboard switch section IV? Multiple keys, various switches for obtaining various effects such as tone, vibrato, sustain, stereo sound localization, normal rhythm, full-in rhythm, automatic accompaniment, etc., as well as R A IVi (random access memory) channels described later. A designated switch, etc. is provided. For example, a reset switch LA.

Reverse switch IB, record switch IC or end key ID? These functions will be described later. Then, two CPUs (central processing units) periodically output a key scan signal via the pass line Bik to scan the entire keyboard switch section 1, and in response to this, the keyboard switch section 1 selects six keys and switches. The output signal of CPU2. VC is given.

For the CPU2, for example, for the musical tone creation section 3.
Each line B3 is operated and a musical tone generation command is given to generate musical tone signals for melody and automatic accompaniment, and these are supplied to the total localization control section 4. Naive, the CPU 2 outputs the control 1'1 tube axis according to the sound image localization part preset to the RA8 to the pass line B4, and gives it to the sound image localization control section 4, and Left and right speakers 6R with all sound image localization settings for musical sound signals.

The corresponding signal tone is output to 6L, and all musical tones are emitted.

Rfi, ”, VJ, 5 &j, CPU 2 crosses the hash line B5 and supplies the address to the address register 7, and thus reads data.
All operations during the evening are fully controlled. And CPU2 and RA
Data is exchanged between M5 via path line B6. In this case, RAM 5 stores the height and note length of the song.

rest? musical tone information (hereinafter referred to as melody information for convenience), tone, vibrato, sustain, sound image localization,
Performance information for all kinds of effects, such as fill-in rhythm on/off, etc., is recorded in different areas. The address counter 7 is provided with one independent address counter for each of the melody information and performance information.
Sakuchoki melody information and @ticket information are read out in parallel and at the same time (/?l) according to the progress of the melody, making it possible to perform the [] period.

The recording section 8 receives time information (data D?-Do') given from the CPU 2 via the pass line B7, and the time information given from the playback section 9 via the pass line B111/i''L (data T D 7). ~TI) Time information (data 7-Io) representing the note length is created from 0), is supplied to the CPU 2 via the pass line B8Th, and is stored in the RAM 5 as performance information for the melody information -f.

Playback department 9ke, RA? V when playing from v'15? - Information according to the melody information and performance information to be read'
! It is given from rcPU2 via pass line B9' to create data for playback processing, and that? Pass line B
1. Ok via CPU2[, also as mentioned above 4
y. Gives time information to the recording section 8 during recording. The CPU 2 is a processor that completely controls all operations of the electronic musical instrument, and a detailed explanation thereof will be omitted. For the same reason as the provision of all two address counters, both the recording section 8 and the reproducing section 9 have multiple stages of the same circuit, so that they each operate independently.

Next, other switches on the keyboard switch section 1 will be explained with reference to Fig. 2. The start switch IE is a switch for inputting all recording start commands.

In addition, the first channel designation switch IF1 and the second channel designation switch IF2 respectively
This is a switch for specifying the channel and the second channel, and is swept at the same time as the record switch IC when recording melody musical sound information. In this case, switches IFI and I
If you operate C at the same time, the first channel will be specified,
After operating the start switch IE', when a key tone is operated, musical tone information of a predetermined melody is stored in the RAM 5.

On the other hand, when switches IF2 and 1C are operated simultaneously,
When the second channel is designated and the start switch IE is operated, the musical tone information of the pond melody is written into the RAM 5 when the key is operated. So, for example, if you first write melody 7;L in the first channel A, when you add another melody to the second channel,
After turning on only the switch IFI, the switch 1F2
By operating the IC and gold at the same time, and operating the start switch 1E=i at θ(, the melody of the first channel will be played, and since you are listening to it, you can listen to the other melody in the second channel. In addition,
The play switch IG simultaneously plays two melodies that are incorporated into the first channel and the second channel of the RAM 5 in a double series, respectively.
This is a switch for automatically playing the C readout and playback section.

Next, the configuration of the recording section 8 will be explained with reference to FIG. P
R launch 1.1 K, usually in the reproducing section 9 as described below.
[The count output of the J p /down counter is input as data TD7 to T Do through the transfer date group 12, and when the CPU 2 outputs the signal LATffi, it is launched. In addition, when the VC-C main playback operation is stopped during playback and rewinding is performed by operating the reverse switch IB, and a new recording is started, the latch data of PR launch I'l is sent to the CPU 2 via the rewinding operation. Then, the data for the full adder at that time is sent to the full adder in the reproducing section 8, which will be described later, and conversely, the data for the full adder at that time is sent to the entire transfer gate group 13 as data D7 to Do. The PR clutch 1 is launched.Then, the data released by the PR clutch 1 is sent to the B input terminals (87 to 30) of the reducer 14.
is applied to. In addition, the A input terminal of the subtracter 14 (A7 to
The data TD7...TDo are input to AU). Therefore, 14 subtracters are used to convert the input data of the A input terminal to B.
Subtract the input data of the input terminal, and the resulting data ■7~
IO'! It is sent to RAM 5 and stored via rcPUZ. This data 7 to IO indicates time data that gives the key-on time and key-off time in the case of melody information, and on the other hand, in the case of the other musical tone information of the effect, VC is the time data that indicates the generation period of the effect. be. It should be noted that the transfer dart group 12 receives the signal C output by the CPU 2.
applied to the gate via the Hk inverter 15,
Further, in the transfer arc 3 group 13, the signal CH is directly applied to the darts thereof, and the darts are controlled together.

Next, the configuration of the reproducing section 9 will be explained with reference to FIG. 6. '[JP/dow n counter 17, 8
This is a bit-configured counter, and after the CPU 2 outputs a clear signal CLR at the start of recording or playback and is cleared, the tempo oscillator 18 outputs a signal from its output terminal P to the counter. Do the following.

The frequency of the oscillation output of the tempo oscillator 18 is variable by a tempo volume 19, and the output of the tempo oscillator 18 is input to an AND gate 20. The output of the tempo stop switch ESW is input to the other end of the AND gate 20 for date control, and the output of the AND gate 20 is input to a T-type flip-flop 21 and a transfer gate 23. Further, the set output of the flip-flop 21 is inputted to the H1T type flip-flop 22 and the transfer dart 24. Furthermore, the flimp float 220 cent output is input to the transfer gate 25. Each of the transfer gates 23, 24, and 25 has a tempo power low speed switch CSW, a normal switch FSW, and a slow tempo switch DSW, each consisting of a double lock type switch in which only one of them is in the on state. Each output is applied and dart controlled. and each transfer gate 23.24
．． Each output of 25 is UP/CROWN as the clock.
The OR gate 37 is applied to the counter 17 and counted.Thus, the flip-flops 21 and 22 form a branch circuit, and for the output of the tempo oscillator 18, the outputs of the 7-resonance deflops 21 and 22 are respectively Its frequency is 1/2
．． It is 1/4.

Further, as shown in the figure, the tempo oscillator 18 outputs from its output terminal H1 a signal higher in speed (higher frequency) than the signal output from the output terminal P, and the transfer digit 36 and the or digit 37 ? through said up/do
The wn counter 17 is marked as a clock. This is H
If rest information is included as the first musical tone information of the melody in at least one channel of the RAM 5, the CPU 2 detects the rest information and then sounds the melody in real time. Until the musical tone information of the first musical tone is read out, a one-level gate control signal FLLr which opens the transfer gate 36 is outputted to the high speed clock kup/down counter 17. This causes fast-forward read processing for R, AM5? This is to prevent the occurrence of silent periods due to rest information.

The amplifier count operation and down count operation of the up/down counter 17 are controlled by the following steps.
This is done by the set output signal UPDWK of the clip-flop 26. That is, the set input terminals S, , I) and cent input terminals RE of the flip-frog 26 are respectively forward swing fBSW and reverse swing switch ASW consisting of a double lock type switch (same as IJ / -s switch IB in figure m1). Each output is an input. And U P/D
Each bit output of the OWN counter 7 is input to one end of each of the corresponding exclusive registers 277 to 27o, and is also sent to the recording section 8 as data TD, to TDo. Further, each corresponding bit output of the NE clutch 8 having an 8-bit capacity is input to each other end of the exclusive OR gates 277 to 27o. And exclusive oak 277
-27o are input to the NOR gate 29, and the output of the NOR gate 29 is further supplied to the CPU 2 as a coincidence signal. That is, exclusive OR gates 277-27o and NOR gate 29 form a matching circuit.

The NE latch 28 connects the S output terminals S7 to So of the full adder 30 when the CPU 2 outputs the lunch clock.
The result data of addition x or subtraction from is latched. Also, when NE clutch 8 is used, at the start of recording operation and playback operation! 4. Clear signal CLR output by CPU2
(r is applied and cleared. A of the full adder 30
Input terminal A, ~Ao VCIrfl, N'E latch 28
The latch data is fed back through the transfer gate group 31 and input. In addition, the B input terminals B7 to BOi are
The outputs of the exclusive OR gates 32 to 320 are inputted, and the output of the AND gate 33 is inputted to the carry input terminal CIN via an inverter 34 and a transfer gate 35. Therefore, exclusive 0p million addresses 32. ~32
At each end of the PR lunch 11) in the recording section 8, the time data of the PR lunch 11) is used for rewinding during playback and then for correction. : Human input according to key operations when performing recording operations.゛In addition, at each other end, the ant gate 3
The output of 3 is in-134,) 7spf dart 3
5'.

ing. This signal R is normally outputted as "1#" and "7", and is temporarily outputted as "0#" during the recording correction. It is then sent to the output ucPU2 of the AND gate 33. Additionally, the transfer gate group 31 and the transfer dart 35 are connected to the signal CH output by the CPU 2.
Dirt control is performed by R, and this signal CHR is temporarily outputted from the CPU 2 as 0# when correction 2 is performed during recording. Furthermore, the latch data of the NE latch output from the transfer gate group 31 is sent to the PR latch 11 when data is corrected during reproduction.

Further, the A input terminal and the B input terminal of the subtracter 38 have the following signals, respectively.
NE clutch 8 latch data, up/do w
Count value data of n counter 17 is inputted respectively,
The subtracter 38 then performs the fast forwarding process of the RAM 5.
The entire count value data is subtracted from the latch data, and the resultant data '(zNE is given to the latch 28 and latched.

Next, the sheet music in Figure 9 shows the two pieces (circular form pieces).
The operation of recording on the first channel and second channel of &RAM 5 and reproducing them all will be explained. Operation in case of loss of recording〃) et al. 70-Char-h'f!
: Refer to and explain. Is this the first song to be played for 141 years?
, it is assumed that the first song is recorded on the first channel, and all subsequent songs are recorded on the second channel. Further, the melody of the song is written into the RAM 5 by normal performance by operating the keyboard switch 1jS1.

Before starting recording 3, press the record switch IC and the 1st channel designation switch 11゛1 at the same time and set the RA.
Input the nail/sound command for the first channel of M and 5. Next, turn on the start switch IE' (i7), and after inputting the recording start command, start playing the first song.Then, the output of the clear signal is input to the CPU2 via the pass line B2, and the CPU2 Accordingly, the fourth
Step i (M) of the flowchart shown in the figure is performed. That is, the clear count-IQcLRk pass line B7, B
9, respectively, and output to PR latch 11. NE clutch 8, U
Clear the P/dow n counters 17' (i=each).Then, the CPU 2 clears the address counters for the melody information in the address list from the RAM 5.
The address control information for setting all the starting addresses for the melody information 'i]<is output and set to line B5 (step RM2).

Next, the CPU 2 outputs data NOP to the pass line B6 and stores it in the first address (0 address) of the RAM 5. Fifth
The figure schematically shows the entire storage state. This data N0P (NO0PERATION) is data indicating a rest. The above is the process of step RM3.

Then, the CPU 2 performs an increment process of step RM4 in which the address counter of the address register 7 (hereinafter simply referred to as address renostaff) is incremented by 1, thereby setting a value of 1. Next, a process of determining whether or not the reset switch 1 has been turned on is performed in step S5. The reset switch IA is a switch that is turned on when performing recording correction. When turned on, the process returns to step RM and is set to the initial state. On the other hand, when it is not turned on [id, step RM6
The VC progresses and it is determined whether the end key ID is turned on or not. This end-t'-ID is a switch that is turned on when the input of melody information is completed to write an end code at the end of the melody information inputted by RAM 5 VC. IDi,
ttonshi*, :1(yryEs J)ica, stets7
The process proceeds to QRM, , and the above-described processing is executed.

However, the end key ID is turned on, so (N
rNOJ), Sufu 77' RR48VC forward h L, reverse switch xB (reverse ffi switch A S W)
Processing to determine whether or not the player has been turned on is executed. When the switch is turned on, a process is executed to move the Stellan' RM 9 to a recording standby state, and this process will be explained in detail later. Then, of course, the reverse switch IB is turned on, and the process proceeds to step RM, +o, where it is determined whether or not the key has been operated. Then, when the key of the first tone (tone of pitch 03) of the melody of the first song in FIG. 9 is turned on and the melody performance is about to start, step RM+ is executed. , RMs , RMa , RM3
, RM+. ,... are repeated. When the C3 key is turned on after a half-rest interval after the start of the performance, the process proceeds to step RM++, where a process to determine whether the key is pressed or released is executed, and since it is a pressed key, step RMI2 Then, in order to indicate that the key code and key press data are CPUZU pitch 03, the musical sound information is added by adding all data "0" to the MSB (highest focus) of the key code. calculate. Then, it is applied to the musical tone generating section 3 through the entire pass line B3', and the sound is emitted from the speakers 6R and 6L (step RM13). Next, STETSU fRM l
Proceeding to step a, the CPU 2 sets the signal CH to 0#, and thereafter, in normal times, the transfer gate group 12 is always open and the transfer gate group 13 is always closed. This [state 7' described above in the reproduction section 9]
After clearing RM, input the counter of the set tempo and perform counting operation (Currently, forward switch BSW is turned on, flip-flop 26 is set, and up-counting operation is in progress) Execute on whole milk Inside UP/
The count output of the down counter 17 (time data for converting to a half-minute rest) is sent to the A input terminal of the PR clutch 1 and the subtracter 14 via the nomadic line Bll and transfer key 12 group as data T D 7 to T D o. It will be input. Next, the process of step RMI7 is executed, and the CPU 2 applies the I word LAT to the PR launch 11, and all the time data being input at that time PR launch 11.
After that, the launch data is held and applied to the input terminal of the subtracter 140B. -force,
In parallel with this, step RM.

, is executed. That is, the tank calculator 14 executes operation 371-w to subtract the input data to the B input terminal from the input data to the input terminal -\, and the input data to the 1 input terminal is t, 2 minutes. The time data of the rest and the latch data of the PR clutch 1 that was cleared at the beginning is "Oj," so the result data at that time I7 to IoFi are the time data of the half rest, and the head is stored in the address 1 of RAM 5. In FIG. 5, this result data is indicated as "T8" meaning time data of the length of a second official rest. ? The address register 7 is incremented by +1 to set address 2 (step RM, +o), and the already calculated key press code, that is, the - code (C3) to address 2 of RAM 5, is set to address 2 (step RM, +o). and key press data (rOJ) are written (step RM2 o ). and address register 7 is 1
-1 and 3@ground is set (step RM2.), and the process returns to step RMs.

Next step RM, RM6, RM8 all 8 steps R
↑~'140 When it is determined that the key has been released, the process proceeds to step RM14, where the M of the key code is entered to indicate that it is the key code of Onhiri C3 and the key release data.
Data “1” in SB? Execute the process to add and create all key release codes. Then, it is sent to the musical tone creation section 3, whereby the musical tone of the pitch C5 is muted (step R
M+ a). When proceeding to step RMI7 via the step R] V1+e k, the PR latch IIK-
For example, when the key is released,
The time data of the counter 17 is newly launched, held thereafter, and applied to the subtracter 140B input terminal.

Then, the subtracter 14 writes the address to the input terminal at the time of the key release operation (step RM+8). In this case, as shown in FIG. 5, the time data at this time is "T3J," which represents the key-on time of a quarter note of the pitch C5 key.
Each process of M2 o'L, l:S, as shown in Figure 5,
The key release code is stored at address 4 in RAM5. Then, address 5 is specified in step RM2+, and the process returns to step RM.

Next, when the R of pitch E3 of the second musical tone is falsified, this causes step RM+. and step RIvL+
The process proceeds to step RNL2, where the key press code 1c is calculated in the same manner as the key operation code for the previous iH pitch 03. Then, through the process of step RM+, creation and sound emission of a musical tone of pitch E3 is started. and step RIV1+ a , R
M,? , RM+8, the PR latch 11
Vc is the timing data when the key is pressed at the pitch E3, and the subtracter 14 outputs the supplementary pitch E to the input terminal.
The above-mentioned sound day C is sent from the clock data at the time of key press 3 to the B input terminal.
Data is obtained as a result of subtracting the 1 hour data at the time of key release in step 3, and is written to location 5 in the RAM 5. In this case, as shown in FIG.
1", this represents the key-off time of the key of pitch C3. Thus, the key-on time of the quarter note is set to 1, and the key-off time is set to S1, which is open at "T4". After the processing of step RM20, step RM21
As a result, the next 6th address of RAM 50 is specified, and the process returns to step RM.

Hereinafter, the process when the pitch E3 is released is the same as when the key is released from the pitch 03, and
The same applies to each process subsequent to musical tones. When the processing of the last note is completed, the end key ID'i is turned on and the second code 'tRAM5 is written as the last data of the melody information.

In the above manner, the 9th channel is added to the 1st channel of RA and M5.
After recording the first song in the diagram, the second channel VC
Record the song after Figure 9 1, which is the first song. In this case, the result is almost the same as in the above case, but
Switch operations before starting a performance are a little difficult. That is, first turn on only the first channel designation switch "Th1F".Next, turn on the record switch JC and the second channel designation switch IF2 all at the same time←7, then turn on the start switch 1E. and start playing.

In this case, n shown in FIGS. 7(A) and (B), which will be described later,
According to the flowchart of the raw processing, the melody of the song that has already been entered into the first channel is extracted and transmitted to the musical tone generator HH3VC, so that it can be reproduced and emitted. Then, according to the song that is being played, the men perform the following mengane 7 and make the second chiangeolu VrC nail sound.
- Figure 8 shows the contents of the melody information that is included in the second channel, but since the ending of the song is a whole rest, the time data rT16J at address 1 is twice as long as the half rest. Data on addresses such as oshi, sai, and other addresses are listed in the first page.
The content is the same as that of the channel.

Next, the process of step RM9 when the reverse switch IB is turned on will be explained. This rebus switch I
B (reversing switch ASW) is turned on when the key operation is wrong when inputting the melody information, and returns the address register 7 to the desired address 1, so that the correct melody information can be recorded. In the evening, when the reverse switch IB is turned on, the latch data of PR launch 1 is set to CPU2'? Then, the correction recording operation is started.

After writing the melody information to the RAM 5 as described above, information on various effects, that is, if there are effects other than the melody information, it is all R, AM, and other channels f of 5! It's crowded. Therefore, detailed explanation of this operation will be omitted.

Next, referring to FIGS. 7(A) and 7(B), the songs recorded in the first channel and the second channel of the RAM 5 as described above are respectively 1. I will explain the operation when making VA Germany emit 1-mo live sound.

For example, 1 game, 1, only the blood of the 1st channel survives.
Turn on li, then turn on start switch 1E (L on-・
ru.

Step 8~1. Processing of 9 clear signal 7) (υA
6th Ray (NE latch 28 and -LJ P/
d o w n counter 17 is both (l clear cave Z,
. Next, by the process of step 0Shi2], % A!
The first channel ν of ＼・15 is 1￥ 1+ 'τ and the first channel is set to ``Resreno Stuff''.
O, P J (see figure 1'XIL5) is read out, C
Sent to PU2;, @ed (step 'S fs4,)
. Then, the address register 7 is opened and address 1 is set (step SM<). - Therefore, CPU2 is 6
TJ"T27" l r N OP J ノMS
If B is '0' or 1#, the furnace part processing is carried out in step 5iAs, but in this case, since the data is "rNOP" indicating a rest, the process proceeds to step SM7 and is sent to the musical tone generator 3 as a key-off signal. All corresponding control signals are output, and execution of musical tone creation is prohibited.

Also, when proceeding to step SMi, address 1 of RAM5 is rT.
8J is input to the full adder 3oOB input terminal, and the resulting data (rNE latch 28 is latched (steps SM, ., SM+r).In this case, the forward switch BSW is currently turned on. As a result, the f70 f70 knob 26 is in the set state, the gate 33 is opened, and the UP/DOWN
An amplifier count command is given to the counter 17. The signal R is normally output as u 1 n, so the output of the AND quote 33 is normally “l#
When the signal is supplied to the CPU 2, the upper blade of the inverter 34 normally becomes "0#" and is sent to one end of each of the exclusive gates 32 to 320 and the carry input terminal CIN of the full adder 30, respectively. transfer case)
35'. Note that the signal CHR is normally “
Therefore, the transfer gate 35 and the transfer case 1 group 31 are normally open.

Therefore, the step SM+o, SM,+.

Then, the time data l-T 8 J is input to the B input terminal of the full adder 30 without being completely inverted by the exclusive OR gates 327 to 32o.

On the other hand, the output data of the NE clutch 8 (8-bit all-par 0" data) is input to the A input terminal via the transfer dart group 31, and therefore the full adder result data at that time is "T8". NE latch 28 will be latched.

Next, in the judgment process of step SM,2, it is judged whether or not the coincidence signal from the norate 29 is output at the "1# level".In this case, the exclusive oregate 2
77 to 27o, respectively, 8 bits all "0# data of UP/DOWN counter 17 and NE clutch 8
The latch data "T8" is input, and the "O# level matching signal indicating all mismatches is supplied to the CPU 2, so step SM I 4 VC progresses, and the reverse switch is activated. ” B was manipulated up/'
It is determined whether or not the d o wn @ number has been reversed, and since it is rNOJ, the process further proceeds to step SM, 8, where it is determined whether or not recording is in progress.
Proceeding to M20, it is determined whether the reset switch IA has been turned on or not.Furthermore, rN'OJ is determined, and the process proceeds to step SM. Then, 1\iJ until the match signal of ``1# level is output, that is, up/down.
While the count value data of the counter 17 reaches the time data "T8", the step 5M12.5MI4.5M
l8.5M20.8MI2,... is repeated,
A musical note is sounded: i, followed by 9 rests. And 1”
When the level match signal is output, the rest time of the half rest ends and the program advances to Stella fsM, 3. This step SM
, +s, it is determined whether the amplifier is counting or down-counting, and it is determined that the amplifier is counting, and the process proceeds to step 5R13.

Next, in step 'SM3', press key code 'C3' from address 2 of RAM 5, faly'-ta '0', pij
If the data in Figure 5 is "C5, on" or the
Input to U2 7, and at step Sa+, RAM
Address 503 is set. And Slump S? vi 5
Out, the above-mentioned push piece) data "0" is judged, and slump 5
Proceed with M6VC and enter the key code “C” for tone creation section) 3.
3'' is given as a key-on signal, and as a result, the first tone of the melody is reproduced and the sound emission starts from the speaker 6R16L. And next step SM 8
Now, read the time data "T3" from address 3 of RAM 5.
is read out, and in step SM9, RAM 5 4
The street address is set. The time data "T3" is then applied to the B input terminal of the Cru Adder 30. On the other hand, the HN'E latch 28 is connected to the A input terminal of the full adder 30.
The time data "T8" which is being latched is being input, so the addition result data at that time of Full Age-30 is also the interval data r-T i I J, and so-! Shiga IJ
When it is newly latched in the E position 928, the HJ force is transferred to the exclusive million ports 277 to 27a (step SMII) 0, and the stellar address 0SΔl■12V
C progresses, and it is determined whether or not the coincidence signal is output at the "1# level", and while the coincidence signal is output at the "1" level, the step 5M14, SM+8.5M20%, and step SM , and returning to step 2 are repeatedly executed.

And the on time of the first musical tone of the key code “C3” (
When the time data T3] has elapsed and a match signal of "1" level is output, the process proceeds to step SI'1413, and then in step SM3rfc progress L, the key code "C8" and key release data are output from address 4 of RAM M5. "1", i.e.
"C3, OFF" in FIG. 5 is read out. It's Kade.
In step SM4, the 5@ field in the RAM 5 is set. Then, in step S M5, the key release data "1" is determined, and in step S5M7VC, a key code "C5" and a key-off signal are given to the musical tone creation section 3,
The sound emission of the first musical note is stopped. Next step SM
, [From address 5 of RAM 5, the time data "T1" is read from Yomihata, step SM, and Nodoke RA IV! 1.
5 and 6 are also set to earth. Then step SM...

SM, , Vc, the time data "T1" is directly input to the B input terminal of Full Age-30, and at that time, the i4i data rT11J is input to the A input terminal VCh and the previous result data. Therefore, the addition result data output from the full adder 30 becomes "rT12", and in addition to being newly latched in the NE latch 28, it also has an exclusive OR function.
G27. ~27o. And step SM+
2, the count value of the Up/'dow n counter 17 is increased by the time counter r T l 2 j switch, and a coincidence signal of 'l' is outputted. S Ml 4 , SM+ s , 5M2o,
The processes of "SM+2, -" are repeated, and during this time,
Previously, the Ki1 tone had been muted, and now the key is on.

In addition, when a coincidence signal of "1 level" is output, step S
Proceed to M+s, and then proceed to Stella':'SM3.

The reproduction processing for the first musical tone is thus completed, and the reproduction operation for the second musical tone and subsequent musical tones is performed in the same manner.

(In '7, former Me Suy-Two fsM,, VC Oi-C
"1".

When the coincidence signal has been determined, the reverse switch IBi is operated for correction work and the amplifier count is switched to the full down count. The entire operation will be explained below. As a result of this switching operation, the flip 70 ring 26 is reset.
Therefore, the AND gate 33 is subsequently closed, and its output is given to the CPU 2 and the inverter 34 as "0"'. Further, a town count command is manually inputted to the up/down 11 counter 17, and accordingly, a down-count operation is started and a rewinding state is entered. When this is determined at step SM, 3VrC, the process of step 5M22 in FIG. 7(B) is started.

That is, the processing data of the area specified by the address of the address register 7 at that time is read from the RAM 5. For example, data "G3, ON" (FIG. 5, key press code for the third musical tone) is read from the 10@ field. and step 5
iVI2°rC engineering υ, address register 7 is incremented by -1 and address 9 is set.

Next, in steps SM24, 8M2°, the key press code is determined, and the appropriate note command for the third tone is determined. ) Time 7” from address 9 of VC'RAM 5
In the evening, the TIJ was read and compared, and the address register 775.
Knee 1 #t is set to address 8 (Step SM2□
, 5M28). Next, the time data ``T1'' is marked on the full adder 30, but in the current meeting, the output code ``i'' of the inverter 34 is ``1'', so the output ``i'' of the inverter 34 is The output signal is applied to the carry input terminal CIN of the differential OR gates 327 to 32o1 and the input signal 30. As a result, full 7 goo 30ba,
1 data for the launch of the NE launch 28 to the A input terminal rT16J to the B input terminal]
Data rTx J years subtracted, resulting data r 'f
15 J is applied to the NE latch 28 to latch it (Step 5M5oJ. Therefore, the time gutter (+-T l 5 J) which is wound at Tftl 1 address is latched in the TeNE latch 28 because the reverse rotation has started. VC
hru. Then, the process proceeds to step SM2, and as described above, until the match signal of Vc and then l# is output, step 'SMI 2.8Ml4, SM+s, 5IVi2o,
8Ml2. -- is repeated. Then, before operating the reverse switch lB' and returning to the amp count, ["
1' (matching the time data "T15") is output, steps SM+ 2 and SM+ are performed again.
From s, the process proceeds to the process shown in the separate flowchart of FIG. 7(B), and the rewind process is subsequently executed. And for example,
The data up to address 6 of RAM 5 is rewound, and the reverse switch 1B' is operated while the second musical tone E3 is muted. Then,
It is determined in steps SM+4 and SM+5 that the down count has been reversed to the alarm count, and the step SM+e β progresses, and the address reno staph is +1.
This makes it possible to perform playback processing in the forward direction from step 718M8 onwards. Therefore, the sound emission starts from the second musical tone E3.

Here, when the record switch IC is turned on and all recording conditions are set, the status fS Ml 2 , SM! When step SM+sVc is reached via Step 4, the recording state is determined, and Step SM! Proceed to 9. Then the correction key is turned on next time, step 5M20, 5MI
2,5MI4.8M+8, SM+o, SM4
o-...-... is repeated. Then, in step 1, it is determined that this is the case, and the process to move to the recording state in step 05M2+ is executed.
2. Now, if the address register 7 is -1, then the case 6
．． Address 9 is set. The signal R is then temporarily set to O'', thereby forcing the full adder 30 to continue to act as a subtracter as described above.The full adder 30 then receives the time data rT16J from the NE branch 8 to the From there, the time data "T1" from address 9 of the RAM 5 input to the B input terminal is fully subtracted, and the subtraction result data rT, zsJkN'E is latched by the latch 28.

Therefore, the signal R is returned to "1#" again, and the signal CH is temporarily set to "1", and the time data from the NE latch 28 is transferred through the transfer gate group 13, which is temporarily closed. rT15J is latched to PR clutch 1.Then, the signal CH is turned on, and the iM normal “O”K is returned.
Subtractor 14 outputs up/d to the A input terminal.

The counted value data of the wn counter 17, that is, the corrected third
A subtraction operation is executed to subtract the time data rT15J input to the B input terminal from the key-on count value data of musical tone F3, thereby obtaining a new key-off time of the second musical tone and signing it into RAM address 509. I can bend it. Then, the process returns to step RM in FIG. 4, and the above-described corrective recording operation for the third musical tone and subsequent tones becomes possible.

Note that step 5M26 in FIG. 7(B) is performed during rewinding.
This process is performed when the key release code is read out from the RAM 5, and the musical tone of the key corresponding to the key release code can be reproduced and emitted for the time data of the previous address.

In step SM, 2 of FIG. 7(A), when the coincidence signal 'l' is not input, reverse switch IB (
When the r operation reverses the state from a 7:7' count to a down count in seconds 14, this is determined at step 5IVI+4 and SM+5VC, respectively, and then the process proceeds to step SM7. Then, the address rewinding process is performed at the -J angle, and the process then proceeds to the above-mentioned stage y'SM27, and the above-mentioned rewinding operation becomes possible. On the other hand, when reversing from down counting to up counting, step 5MI4, SM+
5, the rewind operation is determined, and the process proceeds to step 5Ml6, where the address register 7 is incremented by 1, and playback processing in the forward direction starting from step 0s M8 becomes possible.

The process of individually emitting only the melody information (Fig. 8) in the second channel of RAM, 5 is the same as the first one described above.
This is the same as in the case of the channel, and in the case of this second channel, since the time data rT16J of the whole rest is read out first, the rest state is maintained for twice the time of the first channel from the beginning of the first generation. will continue.

Next, referring to the flowchart of FIG. 7(C), the first
The entire operation of the process of starting the reproduction of two melodies of the channel and the second channel at the same time will be explained. In this case, play switch IGk is turned on.

At this time, the process of step S1 is executed, and the first address t of the address register 7 and the /rc1 address plus one address are set. Next, in step S2, time data "
T8'' and rT16J are read respectively, and each full adder 30
Through the entire process, each NE clutch 8 is launched (step S3). Then, the CPtJ&-j signal FF is 'l#
Then, the transfer gate 36 is fully opened, and the highest speed signal output from the output terminal Hi of the tempo oscillator 18 is outputted at the highest speed (step S4), and a process of determining whether a coincidence signal of 1" is output (step S4). Then, when the count data of each counter 17 reaches the time data "T8" from the start of playback, a coincidence signal of "1#" is first output in the first channel, and this is determined. Then, the process proceeds to step s6, where the signal FF is set to "o", and the counting operation of both the valley channel counters 17 is temporarily stopped.Then, the process proceeds to step 87,
In each subtracter 38 of each channel, each NE launch 28 has a lunch (time data "T8", "T16" set with -).
” to the current up/down counter 17
The count value data "T8" is subtracted extensively, and each result data r
'ro' and 'T8' are respectively launched to the corresponding NE launch 28 (step S).

Then, address 2 is set for each channel for each address (step So),
Is the clock based on the tempo output from either of the 17 counters, 23, 24, or 25 of the transfer gates 23, 24, or 25? Counting starts, and the process proceeds to step 5M12, where the normal regeneration processing operation is started.
When you start playing the channels at the same time, VCl-tl In this example, the first time data of the first channel is "T8".
In other words, the half rest in the first channel of the musical score shown in FIG. is started. The musical score in Figure 10 explains this state in its entirety, and on the musical score, the melody of the first channel,
There is no half rest, and in the melody of the second channel, the whole rest is changed to a half rest. Therefore, if there is a song that starts from a rest, the rest in that song will be invalid and silence will occur.
It becomes difficult to hear.

In the above embodiment, two channels V of the RAM 5
For each C song, first record the melody information of the song that has a rest, and then only when playing both channels at the same time will the rest be ignored and playback of one of the songs immediately start. However, in each channel, when the entire channel is played back, if the song starts from a rest, the VCl may be set so that the rest is skipped and the sound is immediately played back. In this case, if the first address of the memory is rest information, it is sufficient to read from address 21.Furthermore, in the above embodiment, the fast forward function of the counter is used to read the rest information at the beginning of the song. I skipped it, but you can skip it by comparing the time characteristics of the rests in both channels and playing the shorter rest time differently from the inter-part information. .Furthermore, the number of memory channels may be 3 or 4 or more, and of course,
The number of memories is not limited to one, but may be multiple.

〔Effect of the invention〕

As explained above, when automatically playing a piece of music that begins with a rest, the present invention provides an automatic performance device and apparatus that skips all of the rests 77' and immediately starts playing and emitting the song. '
Since Th is provided, in the case of a song that starts with a rest, that rest is ignored and there is no silence, which has the advantage of making it less difficult to listen to.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is an overall circuit configuration diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a specific configuration diagram of some switches of the keyboard switch section 1, and FIG. The detailed circuit of the recording section 8 is shown in FIG.
4 is a storage state diagram of the melody information shown in FIG. 7 in the RAM 5, FIG. 5 is a storage state of the melody information in the first channel of the RAM 5, and FIG.
Detailed M circuit diagram of E 7 iRi (A), (B), (
C) i- respectively, Mi7 Re Me. Flow chart of data reproduction processing Venus Figure 1, No. 8
The figure is a memory state diagram of the melody in the second channel of the RAM 5, and Figure 9 is a diagram of the musical scores recorded in the first channel and the second channel respectively, 'A 10
The figure shows the condition of a famous piece that appears when each side of the sheet music in Figure 9 is made horny at the same time. FIG. ...End switch, IE...Start switch, IF, ...1st channel designation switch, IF2...'2nd channel designation switch, IG... ...Play switch, 2...SCP
U, 3... Raku, Minasaku FN, Part, 4...
Localization control section, 5...B, AM, 6R, 6L...
・・・・・・Speaker, 7・・・・Attachment, 8・・・・・・Recording section, 9・・・・・・
Playback section, 11...PR lunch, 14...
・Subtractor, J7...up/dow
n counter, 18...tempo oscillator, 19...
...Tempo oscillator-4, 21, 22, 26...
...Flip-flop, 28...NE latch,
30. River...Full adder, 3G...Transfer gate, 38...Subtractor, BSW...
... +111' switch, C8W ... Tempo acceleration switch, DSW ... Slow tempo switch, ESW ... Denboston bus inch, ES
W・・・・・・Normal switch. Figure 1 R 530- Figure 2 E Figure 5 Figure 8 Figure 7 Figure 7 CB) Figure 7 (C) Procedural amendment (voluntary) February 14, 1981 Kazuo Wakasugi, Commissioner of the Patent Office 1, Display of the case 1982 Patent Application No. 232565 2 Name of the invention Automatic musical performance device 3 Person making the amendment Relationship to the case Patent applicant Address 2-6 Nishi-Shinjuku, Shinjuku-ku, Tokyo $1 Name (
14-4) Kashio, representative of Casio Bg Co., Ltd.
Toshio 4, Agent address: 6-7-16-5, Ginza, Chuo-ku, Tokyo Subject of amendment (1) "Detailed description of the invention" column of the specification. 6. Contents of the amendment (1) In the specification attached to the application, on page 19, line 8, after "becomes.", it is written: "Then, the subtracter 14 inputs the data from the manual data to the A input terminal to the B input terminal. "The input data from the PR latch 11 is subtracted and the result is output to 0PU2 as time data." is inserted. (2) Delete "Time" in the 10th item on the same page of the same book. (3) r ff1 from line 14 to line 16 on the same page of the same book
J, the subtractor 14 is input from the manual data to the A input terminal]3
Performs an operation that subtracts the input data to the input terminal, and deletes ". . (4) In the 16th line of the same page at the beginning, the word ``now'' is corrected to ``-subtractor 14''.

Claims (2)

[Claims] (1) In an automatic performance device that reads musical tone information stored in a memory and plays it back for automatic performance, if rest information is included at the beginning of the musical tone information, this rest information is skipped at the start of fully automatic performance. 1. An automatic performance device comprising: control means for starting sound generation from tone information following the rest information. (2) The memory stores a plurality of sets of musical tone information to be sounded simultaneously, and the control means controls the timing of the shortest rest when rest information is included at the beginning of at least two sets of musical tone information. Control pronunciation by skipping each rest information by the length (
2. An automatic performance device according to claim 1, characterized in that: