JPS59125621A - Device for manufacturing semiconductor - Google Patents
Device for manufacturing semiconductorInfo
- Publication number
- JPS59125621A JPS59125621A JP22868782A JP22868782A JPS59125621A JP S59125621 A JPS59125621 A JP S59125621A JP 22868782 A JP22868782 A JP 22868782A JP 22868782 A JP22868782 A JP 22868782A JP S59125621 A JPS59125621 A JP S59125621A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- wafer
- oscillation
- chamber
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は半導体製造装置に係り、特に、インライン型ス
パック装置またはケミカル・ベーパ・デポジション(C
VD)装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to semiconductor manufacturing equipment, and particularly relates to in-line sppack equipment or chemical vapor deposition (C
VD) Regarding improvement of equipment.
(2)技術の背景
近時、半導体の製造工程において、スパッタまたはCV
D等により、例えばウェハ上に形成した各デバイスにコ
ンタクトをとるためのコンタクト窓を第1図の半導体の
断面図に示すように形成し、配線用の金属導電性物質、
例えばアルミニウム(A文)をスパッタリング法により
形成する。(2) Background of technology Recently, in the semiconductor manufacturing process, sputtering or CV
For example, a contact window for making contact with each device formed on the wafer is formed as shown in the cross-sectional view of the semiconductor in FIG.
For example, aluminum (text A) is formed by sputtering.
このような配線層のデポジットにおいては、第1図fa
lに示すようにデバイスが形成されたウェハ1上にリン
シリカガラス(P S G)等の絶縁層2を形成してコ
ンタクト窓3を該絶縁膜層2上に形成し、A文等の配線
パターン4を形成するときにPSGjiの厚みが1μm
程度あり、コンタクト窓3の幅Wが極めて小さいときに
は、A文の配線パターン4のコンタクト窓3内への何着
状態は凸状に形成されpscl’iのエツジ部2aの近
傍のΔ文配線層厚は極めて薄くなる。In depositing such a wiring layer, as shown in FIG.
As shown in FIG. 1, an insulating layer 2 made of phosphor silica glass (PSG) or the like is formed on the wafer 1 on which devices are formed, and a contact window 3 is formed on the insulating film layer 2. When forming pattern 4, the thickness of PSGji is 1 μm.
When the width W of the contact window 3 is extremely small, the wiring pattern 4 of the A pattern is formed in a convex shape in the contact window 3, and the Δ pattern wiring layer near the edge portion 2a of the pscl'i. The thickness becomes extremely thin.
一般に理想的には、第1図(b)に示すようにpsc層
及びコンタクト窓上のへ父層4の厚さDI、D2.D3
は厚みが等しくなるように膜形成されるべきである。Generally, ideally, the thicknesses DI, D2 . D3
should be formed to have equal thickness.
第1図(alの如くA文理パッド4の付着された場合に
は3aで示す部分が薄いため電流を流したとき抵抗が高
いという弊害の他にパターン切れ等を発η二するため信
頼性を著しく低下させることが多い。When the A literary pad 4 is attached as shown in Figure 1 (al), the part indicated by 3a is thin and has the disadvantage of high resistance when current is applied, as well as pattern breakage, etc., which reduces reliability. Often significantly reduced.
人文配線パターン層を第1図(blに示す理想的パター
ン形状とするためにはウェハを200〜450°Cまで
上昇させる必要があり、インライン式のスパッタ装置で
はスパック室にウェハが送り込まれてスパッタリングが
なされるときのウェハ基板温度が200〜450’Cに
保持されている必要があった。In order to form the humanities wiring pattern layer into the ideal pattern shape shown in Figure 1 (bl), it is necessary to heat the wafer to 200 to 450°C. It was necessary that the wafer substrate temperature be maintained at 200 to 450'C during the process.
これはA文の原子の運動速度を上げてやるために必要な
ウェハ基板温度である。This is the wafer substrate temperature necessary to increase the moving speed of the atoms in sentence A.
(3)従来技術と問題点
従来の上記したインライン式のスパッタ装置の略図的な
構成を第2図に示す1.第2図において、5はセンダー
でウェハ基板の出し入れが行われ、弁6を介してロード
ロック7にウェハが挿入されスパッタ室10と連なる弁
9と該弁6を閉じ弁8を開いてロードロック7内を真空
状態とし、スパッタ室10内はメインl\ルブ11を介
して真空状態となされているが、弁9を開いてロードロ
ック7内のウェハをスパッタ室10に挿入するとともに
弁9を閉じる。このときロートロック13とスパック室
]0を結ぶ弁12は閉じられている。(3) Prior art and problems The schematic configuration of the conventional in-line sputtering apparatus described above is shown in FIG. In FIG. 2, reference numeral 5 denotes a sender where wafer substrates are taken in and taken out, and the wafer is inserted into a load lock 7 through a valve 6, and a valve 9 connected to the sputtering chamber 10 is closed and the valve 8 is opened to lock the wafer. The inside of the load lock 7 is in a vacuum state, and the inside of the sputtering chamber 10 is made into a vacuum state via the main l\\lube 11, but the valve 9 is opened and the wafer in the load lock 7 is inserted into the sputtering chamber 10, and the valve 9 is closed. close. At this time, the valve 12 connecting the funnel lock 13 and the spackle chamber]0 is closed.
スパッタ室10内でスパッタリングが終って配線層等が
形成されたうエバはロードロック13に送り込まれる。After sputtering is completed in the sputtering chamber 10, the evaporator on which wiring layers and the like have been formed is sent to a load lock 13.
この場合、ロードロック13とスパッタ室を結ぶ弁12
並びにレシーバ16とを結ぶ弁15は閉しられて、弁1
4が開かれて10−Fロック13の排気がなされ真空状
態とした後に弁12が開かれてスパッタリングされたウ
ェハがロードロック13内に送り込まれる。In this case, the valve 12 connecting the load lock 13 and the sputtering chamber
Also, the valve 15 connected to the receiver 16 is closed, and the valve 1
4 is opened and the 10-F lock 13 is evacuated to create a vacuum state, and then the valve 12 is opened and the sputtered wafer is sent into the load lock 13.
次に弁12を閉し、ロードロック13をN2等の不活性
ガスを用いて大気圧にした後且つ弁15を開いてロード
ロック13内のウェハをレシーバ16内に1M人して取
り出す。Next, the valve 12 is closed, the load lock 13 is brought to atmospheric pressure using an inert gas such as N2, and then the valve 15 is opened to take out 1M wafers in the load lock 13 into the receiver 16.
このようなインライン式スパック装置では、ロードロッ
ク7においては大気をスバ・ツタ室に入れないための機
能とともにウェハを200〜450″Cまで昇温させる
機能を有している。In such an in-line spacing apparatus, the load lock 7 has a function of not allowing atmospheric air to enter the sprinkling chamber and a function of raising the temperature of the wafer to 200 to 450''C.
このロードロック内の加熱は処理時間に見合うように加
熱時間を設定してウエノ\加熱を行ってし)るが、これ
が圧密に動作しているときは特に問題がないが、これの
ライン内でのトラブル、或いは排気速度の変動等の異常
が生じたときにウエノ・・は所定の基板温度に達しない
ままスパック室内に送入されて膜形成されて不良品を発
生する欠点があった。The heating inside this load lock is performed by setting the heating time to match the processing time, and there is no particular problem when it is operating compactly, but within this line When problems such as problems or fluctuations in the pumping speed occur, the urethane is fed into the spuck chamber before reaching a predetermined substrate temperature and a film is formed, resulting in defective products.
(5)発明の目的
本発明は上記欠点に鑑み、ロードロ・ツクすなわち予備
加熱室内の温度を非接触状態でモニタできるようにして
、安定な処理の行える半導体製造装置を提供することを
目的とするものである。(5) Purpose of the Invention In view of the above-mentioned drawbacks, it is an object of the present invention to provide a semiconductor manufacturing apparatus that enables stable processing by monitoring the temperature inside the loading chamber, that is, the preheating chamber, in a non-contact manner. It is something.
(5)発明の構成
そして、この目的は本発明によれば、膜形成装置の予備
室または膜形成室内に搬入されたウエノ1等の試料をマ
イクロ波で加熱するマイクロ波加熱手段と、該試料表面
の温度を検出するための検出手段とを有し、該検出手段
の検出出力を上記マイクロ波加熱手段に帰還させて予備
室または膜形成室内のウェハ基板温度を一定に調整する
ようにしてなることを特徴とする半導体製造装置を提供
することで達成される。(5) Structure of the Invention According to the present invention, the object is to provide a microwave heating means for heating a sample such as Ueno 1 carried into a preliminary chamber or a film forming chamber of a film forming apparatus using microwaves, and and a detection means for detecting the temperature of the surface, and the detection output of the detection means is fed back to the microwave heating means to adjust the temperature of the wafer substrate in the preliminary chamber or the film forming chamber to a constant value. This is achieved by providing a semiconductor manufacturing apparatus characterized by the following.
(6)発明の実施例 以下、本発明の一実施例を図面について説明する。(6) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.
第3図は本発明の第2図に示すロードロ・ツク7すなわ
ち、予備室の要部の断面を示すものであり、17は断面
がほぼ直方形状で紙面の方向に延設され手前側にセンダ
ー5が、奥にスバ・ツタ室10が第2図のように配置さ
れ、弁6,9並びに8の開閉によってロードロック内を
真空に保ったり大気に連通させたりしている真空槽であ
り、該真空槽内には同じくセンダー5側からスバ・ツタ
室10に向かって2本のレール18が敷設されてウエノ
\等の試料1が該レール上に連続的に1殻送される。FIG. 3 shows a cross section of the main part of the load drawer 7 shown in FIG. 2 of the present invention, that is, the main part of the preliminary chamber, and 17 has a substantially rectangular cross section, extends in the direction of the paper, and has a sender on the front side. 5 is a vacuum chamber in which a suba ivy chamber 10 is arranged as shown in FIG. Two rails 18 are also laid in the vacuum chamber from the sender 5 side toward the suba ivy chamber 10, and one shell of the sample 1, such as Ueno\, is continuously sent onto the rails.
真空槽17の上部には窓19が形成され、該窓の上部に
は石英ガラス20が覆はれ、ガラス抑え金具21とO−
リングシール材22によって真空槽内を高(、>真空度
に保持している。A window 19 is formed in the upper part of the vacuum chamber 17, the upper part of the window is covered with quartz glass 20, and a glass holding fitting 21 and an O-
The inside of the vacuum chamber is maintained at a high degree of vacuum by the ring sealing material 22.
ガラス抑え金具21の上部にはフランジ部23を有する
導波管24を載置する。A waveguide 24 having a flange portion 23 is placed on the top of the glass holding fitting 21 .
該導波管側部にはマイクロ波発振管25を設け、導波管
壁に穿った透孔を通してアンテナ26を突き出させマイ
クロ波出力端27よりマイクロ波を発振させて石英ガラ
ス20を通してウェハ1を加熱させる。A microwave oscillation tube 25 is provided on the side of the waveguide, and an antenna 26 is protruded through a hole bored in the waveguide wall to oscillate microwaves from a microwave output end 27 to cause the wafer 1 to pass through the quartz glass 20. Let it heat up.
マイクロ波発振管25から発振された電磁場は誘電体で
あるウェハのみを加熱し、他の真空槽を形成している金
属部分や石英ガラスを加熱しない。The electromagnetic field oscillated from the microwave oscillation tube 25 heats only the dielectric wafer and does not heat the other metal parts or quartz glass forming the vacuum chamber.
導波管は大気にさらせるため、加熱装置を真空槽内に設
ける必要がないので加熱装置の設計の自由度を大きぐと
れる。さらに金属部に当ってマイクロ波は接地電位に落
ちるためにランプヒータ加熱のように金属部の蓄熱によ
る影響をウェハが受けないという特徴がある。Since the waveguide is exposed to the atmosphere, there is no need to provide a heating device in a vacuum chamber, allowing greater flexibility in designing the heating device. Furthermore, since the microwave falls to the ground potential when it hits the metal part, the wafer is not affected by heat accumulation in the metal part, unlike heating by a lamp heater.
本発明ではガラス抑え金具21及び導波管24のフラン
ジ23に透孔21.a 、 23aに挿通して石英ガラ
ス20の表面にオプティカルファイバー28の一端を対
接させ、その4h端を赤外線センサの如き温度検出器2
9に結合させ、ウェハ1から生じる赤外線31を検出し
、温度検出器の出力を温度−電気変換回路30を通して
マイクロ波発振管の電力供給源に帰還させて電磁波のパ
ワー或いは照射時間をコントロールさせるよようにする
。In the present invention, the glass holding fitting 21 and the flange 23 of the waveguide 24 have through holes 21. a, one end of the optical fiber 28 is brought into contact with the surface of the quartz glass 20 by passing it through 23a, and the 4h end is connected to a temperature detector 2 such as an infrared sensor.
9 to detect the infrared rays 31 generated from the wafer 1, and return the output of the temperature detector to the power supply source of the microwave oscillation tube through the temperature-electrical conversion circuit 30 to control the power or irradiation time of the electromagnetic waves. Do it like this.
上記構成によれば、例えばマイクロ波波の発振時間を設
定し、ウェハ温度が200〜450’C範囲になるよう
に時間制御することが可能となる。According to the above configuration, for example, it is possible to set the oscillation time of the microwave and control the time so that the wafer temperature is in the range of 200 to 450'C.
すなわち、ウェハ温度が所定の温度より低ければ発振を
継続させ、所定温度より高げれば発振を停止させるよう
にする。That is, if the wafer temperature is lower than a predetermined temperature, the oscillation is continued, and if the wafer temperature is higher than the predetermined temperature, the oscillation is stopped.
なお、上記実施例ではインライン式膜形成装置としてス
パック装置によりA交配線パターンを形成する場合につ
いて予備室内部での実施例について述べたが、膜形成室
においても同様の構成によりウェハ温度の制御は可能で
ある。さらに本発明はこれに限定されることなく、例え
ばCVD装置によって各種薄膜を形成する場合に適用し
得ることは勿論である。In the above embodiment, an in-line film forming apparatus in which the A cross line pattern is formed using a spuck apparatus was described in the preliminary chamber, but the wafer temperature can also be controlled using the same configuration in the film forming chamber. It is possible. Furthermore, the present invention is not limited thereto, and can of course be applied to the case where various thin films are formed by, for example, a CVD apparatus.
(7)発明の効果
以上、詳細に説明したように本発明の半導体製造装置に
よれば、インライン式薄膜形成装置内のトラブル或いは
排気速度変動等の異常に対して、従来のように時間だけ
で温度制御をしている場合に比べて試料の表面温度を非
接触状態で計測できること、並びに加熱手段にフィード
ハックを掛けて時間または出力をコントロールできるの
で安定な処理を行い得る特徴を有するものである。(7) Effects of the Invention As explained above in detail, according to the semiconductor manufacturing apparatus of the present invention, troubles in the in-line thin film forming apparatus or abnormalities such as fluctuations in pumping speed can be resolved in a timely manner, unlike conventional methods. Compared to temperature control, this method has the characteristics of being able to measure the surface temperature of the sample in a non-contact state, as well as being able to control the time or output by applying a feed hack to the heating means, allowing for stable processing. .
第1図(al、 (blは従来の半導体装置の人文配線
パターン状態を説明するための側断面図、第2図は従来
のインライン式スパック装置の概略的構成を示す排気系
統図、第3図は第2図の予備室を本発明に適用した場合
の側断面図である。
1・・・Si基板(ウェハ)、 2・・・絶縁膜、
3・・・コンタクト窓、 4・・・配線Jfi(
A又等)、 5・・・センダー、6、 8. 9.1
1.12.14.15・・・弁、 7゜13・・・ロ
ードロック、 IO・・・スパック室、16・・・
レソーハ、 17・・・X空$L t8・・・レ
ール、19・・・窓、20・・・石英ガラス、 21
・・・ガラス抑え金具、 22・・・0−リングシー
ル、 23・・・フランジ部、 24・・・導波管
、 25・・・マイクロ発振管、 26・・・アン
テナ、 27・・・マイクロ波出力端、 28・・・
オプティカルファイバー、 29・・・温度検出器、
30・・・温度−空気変換回路、 31・・・赤
外線。Figure 1 (al, (bl) is a side sectional view for explaining the human wiring pattern state of a conventional semiconductor device, Figure 2 is an exhaust system diagram showing the schematic configuration of a conventional in-line spacing device, and Figure 3 2 is a side sectional view when the preliminary chamber of FIG. 2 is applied to the present invention. 1... Si substrate (wafer), 2... Insulating film,
3... Contact window, 4... Wiring Jfi (
A, etc.), 5... Sender, 6, 8. 9.1
1.12.14.15...Valve, 7゜13...Load lock, IO...Spack chamber, 16...
Lesoha, 17...X empty $L t8...rail, 19...window, 20...quartz glass, 21
... Glass holding fitting, 22 ... O-ring seal, 23 ... Flange section, 24 ... Waveguide, 25 ... Micro oscillation tube, 26 ... Antenna, 27 ... Micro Wave output end, 28...
Optical fiber, 29...Temperature detector,
30...Temperature-air conversion circuit, 31...Infrared rays.
Claims (1)
ハ等の試料をマイクロ波で加熱するマイクロ波加熱手段
と、該試料表面の温度を検出するための検出手段とを有
し、該検出手段の検出出力を上記マイクロ波加熱手段に
帰還させて予備室または膜形成室内のウェハ基板温度を
一定に調整するようにしてなることを特徴とする半導体
製造装置。A microwave heating means for heating a sample such as a wafer carried into a preliminary chamber or a film forming chamber of a film forming apparatus using microwaves, and a detection means for detecting the temperature of the surface of the sample, the detection means A semiconductor manufacturing apparatus characterized in that the detection output of is fed back to the microwave heating means to adjust the temperature of the wafer substrate in the preliminary chamber or the film forming chamber to a constant value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22868782A JPS59125621A (en) | 1982-12-28 | 1982-12-28 | Device for manufacturing semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22868782A JPS59125621A (en) | 1982-12-28 | 1982-12-28 | Device for manufacturing semiconductor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59125621A true JPS59125621A (en) | 1984-07-20 |
JPH0377659B2 JPH0377659B2 (en) | 1991-12-11 |
Family
ID=16880226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22868782A Granted JPS59125621A (en) | 1982-12-28 | 1982-12-28 | Device for manufacturing semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59125621A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62283643A (en) * | 1986-05-02 | 1987-12-09 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Metallic contact system |
JPH0325977A (en) * | 1989-06-23 | 1991-02-04 | Fuji Electric Co Ltd | Schottky barrier diode |
FR2671628A1 (en) * | 1991-01-10 | 1992-07-17 | Doryokuro Kakunenryo | Apparatus for measuring the heating temperature in an intense microwave electric field |
US5491112A (en) * | 1989-06-30 | 1996-02-13 | Im Institutet For Mikroelektronik | Method and arrangement for treating silicon plates |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5691436A (en) * | 1979-12-26 | 1981-07-24 | Fujitsu Ltd | Method for heating semiconductor substrate |
JPS5754315A (en) * | 1980-09-19 | 1982-03-31 | Matsushita Electric Ind Co Ltd | Preparation of semiconductor device |
JPS57178316A (en) * | 1981-04-27 | 1982-11-02 | Hitachi Ltd | Manufacture of semiconductor element and device therefor |
-
1982
- 1982-12-28 JP JP22868782A patent/JPS59125621A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5691436A (en) * | 1979-12-26 | 1981-07-24 | Fujitsu Ltd | Method for heating semiconductor substrate |
JPS5754315A (en) * | 1980-09-19 | 1982-03-31 | Matsushita Electric Ind Co Ltd | Preparation of semiconductor device |
JPS57178316A (en) * | 1981-04-27 | 1982-11-02 | Hitachi Ltd | Manufacture of semiconductor element and device therefor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62283643A (en) * | 1986-05-02 | 1987-12-09 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Metallic contact system |
JPH0325977A (en) * | 1989-06-23 | 1991-02-04 | Fuji Electric Co Ltd | Schottky barrier diode |
US5491112A (en) * | 1989-06-30 | 1996-02-13 | Im Institutet For Mikroelektronik | Method and arrangement for treating silicon plates |
FR2671628A1 (en) * | 1991-01-10 | 1992-07-17 | Doryokuro Kakunenryo | Apparatus for measuring the heating temperature in an intense microwave electric field |
Also Published As
Publication number | Publication date |
---|---|
JPH0377659B2 (en) | 1991-12-11 |
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