JPS59124712A - Semiconductor device manufacturing apparatus - Google Patents

Semiconductor device manufacturing apparatus

Info

Publication number
JPS59124712A
JPS59124712A JP23379282A JP23379282A JPS59124712A JP S59124712 A JPS59124712 A JP S59124712A JP 23379282 A JP23379282 A JP 23379282A JP 23379282 A JP23379282 A JP 23379282A JP S59124712 A JPS59124712 A JP S59124712A
Authority
JP
Japan
Prior art keywords
film forming
processed
forming apparatus
manufacturing apparatus
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23379282A
Other languages
Japanese (ja)
Inventor
Minoru Inoue
実 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23379282A priority Critical patent/JPS59124712A/en
Publication of JPS59124712A publication Critical patent/JPS59124712A/en
Pending legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52Controlling or regulating the coating process

Abstract

PURPOSE:To realize fine control and management for individual material to be processed and enhance working efficiency of an apparatus as a whole by providing a plurality of pairs of thin film forming apparatus and also providing a transfer mechanism which is capable of freely setting the transfer path of material to be processed. CONSTITUTION:In case a material to be processed is required to form a multi- layer film and to continuously form different kinds of metals by the growth method, the material to be processed is sent to a second film forming apparatus 20b. When the second layer film is formed, thickness in the load lock connected to the second film forming apparatus 20b is inspected, thickness of the second layer is inspected by the measuring means 22b, 23b and the surface condition is also inspected. If any fault is detected, wafer can be extracted from the output OUT2. When any fault is not detected, the material to be processed is sent to the third film forming apparatus 20c. Sputtering is carried out to the third layer as described above and it is then outputted from the OUT3, for example, after the inspection. Each process including measuring is conducted under the vacuum condition and the film forming apparatus 20a, 20b, 20c are provided with the heating chamber for heating material to be heated such as wafer and such heating chamber is adjusted to adequate temperature.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は半導体製造装置に係り、特に半導体基板上に多
層または単層の薄膜を形成するインライン型薄膜形成装
置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to semiconductor manufacturing equipment, and particularly to improvements in in-line thin film forming equipment for forming multilayer or single-layer thin films on semiconductor substrates.

(2)技術の背景 半導体または集積回路等の製造工程において、配線用の
アルミニウム(A文)系合金膜や眉間絶縁膜等を成上さ
せるためにケミカル・ヘーパ・デポジション(CVD)
またはスパッタ装置等が広く用いられている。
(2) Background of the technology In the manufacturing process of semiconductors or integrated circuits, chemical vapor deposition (CVD) is used to form aluminum alloy films for wiring, glabellar insulating films, etc.
Alternatively, sputtering equipment and the like are widely used.

これら薄膜形成装置は生産工程において、効率を上げる
ためにインライン式となされている。しかし、半導体の
ウェハ上に単層の膜を形成する場合は1組のインライン
式の例えばスパック装置等に被処理物たるウェハを1u
l1人し、スパッタ室内で膜形成された被処理物を取り
出せばよいが、多層膜形成時には別の1組の膜形成装置
に再び搬入させなければならないために複数の膜形成装
置で処理を行っているのが現状である。
These thin film forming apparatuses are of an in-line type in order to increase efficiency in the production process. However, when forming a single-layer film on a semiconductor wafer, the wafer to be processed is placed in a set of in-line spuck equipment, etc.
It is sufficient to use one person to take out the workpiece on which a film has been formed in the sputtering chamber, but when forming a multilayer film, the workpiece must be transported again to another set of film forming apparatuses, so processing is performed using multiple film forming apparatuses. The current situation is that

(3)従来技術と問題点 従来の上記したインライン式のスパッタ装置の概略的な
系統図を第1図に示す。第2図は2組のインライン式の
スパッタ装置を直列的に配設した場合の路線的な系統図
を示すものである。
(3) Prior Art and Problems A schematic system diagram of the above-described conventional in-line sputtering apparatus is shown in FIG. FIG. 2 shows a line system diagram when two sets of in-line sputtering devices are arranged in series.

第1図において、1はセンダーでウェハ等の被処理物の
出し入れが行われ、弁2を介してロードロック3にウェ
ハが挿入され、スパッタ室5と連なる弁6と該弁2を閉
し弁4を開いてロードロック3内を真空状態となす。ス
パッタ室5内はメインバルブ7を介して真空状態となさ
れているが弁6を開いてロードロック3内のウェハをス
パッタ室5内に挿入するとともに弁6を閉じる。このと
きロードロック8とスパッタ室5を結ぷ弁9は閉じられ
ている。
In FIG. 1, reference numeral 1 denotes a sender for loading and unloading workpieces such as wafers, the wafer is inserted into a load lock 3 via a valve 2, a valve 6 connected to a sputtering chamber 5, and the valve 2 are closed. 4 to create a vacuum inside the load lock 3. The interior of the sputtering chamber 5 is kept in a vacuum state via the main valve 7, but the valve 6 is opened and the wafer in the load lock 3 is inserted into the sputtering chamber 5, and the valve 6 is closed. At this time, the valve 9 connecting the load lock 8 and the sputtering chamber 5 is closed.

スパッタ室5内でスパッタリングが終ッて所定の膜厚の
薄膜が形成されたウェハはロートロック8に送り込まれ
る。
After sputtering is completed in the sputtering chamber 5 and a thin film of a predetermined thickness is formed on the wafer, the wafer is sent to the rotor lock 8 .

この場合ロート”ロック8とスパッタ室5を結ぶ弁9並
びにレシーバ10と結ふ弁11は閉しられて弁12が開
かれて排気がなされ真空状態とした後に弁9が開かれて
スパッタリングされたウェハ4がロート′ロック8内に
送り込まれる。
In this case, the valve 9 that connects the funnel lock 8 and the sputtering chamber 5 and the valve 11 that connects the receiver 10 are closed and the valve 12 is opened to evacuate and create a vacuum state, and then the valve 9 is opened to perform sputtering. The wafer 4 is fed into the funnel'lock 8.

次に弁9を閉じ、且つ弁11を開いてロードロック8内
のウェハをレシーバ゛10内にIB人して取り出す。
Next, the valve 9 is closed and the valve 11 is opened to take out the wafer in the load lock 8 into the receiver 10.

このような1組のインライン型のスパック装置、すなわ
ち膜形成装置を複数用いて被処理物に例えば多層膜を形
成する場合の従来構成を第2図に示す。
FIG. 2 shows a conventional configuration for forming, for example, a multilayer film on an object to be processed by using a plurality of such in-line spuck apparatuses, that is, a plurality of film forming apparatuses.

なお、第1図と同一部分には同一符号を付して重複説明
を省略する。予備室を構成するロードロック8と第2の
スパッタ室13との間に弁11を介在させ、該第2のス
パッタ室13の真空度は導入するガス流量を制御するマ
スフロー(図示−1ず)とメインバルブ14で制御され
、さらに第2のスパッタ室とロードロック16に弁15
を設け、ロードロック3.8と同様に排気用弁17をロ
ードロック16に設けるとともに1シーパ10との間に
弁18を介在させる。
Note that the same parts as in FIG. 1 are given the same reference numerals, and redundant explanation will be omitted. A valve 11 is interposed between the load lock 8 constituting the preliminary chamber and the second sputtering chamber 13, and the degree of vacuum in the second sputtering chamber 13 is controlled by a mass flow (not shown in the figure) which controls the flow rate of gas introduced. and a main valve 14, and a valve 15 in the second sputtering chamber and load lock 16.
Similarly to the load lock 3.8, an exhaust valve 17 is provided on the load lock 16, and a valve 18 is interposed between the load lock 16 and the 1-seaper 10.

このように構成された膜形成装置ではスパッタ室5で、
第1層目の膜が被処理物上に形成され、第1図と同様に
ロードロック3.8の排気操作によって第2のスパッタ
室13に111人された被処理物は第1層膜上に第2層
膜をスパッタリングして多層膜構造が形成され、被処理
物は弁15.16.17の操作によりレシーバ10に搬
出される。
In the film forming apparatus configured in this way, in the sputtering chamber 5,
The first layer film is formed on the workpiece, and the workpiece is placed in the second sputtering chamber 13 by the exhaust operation of the load lock 3.8 in the same manner as in FIG. A multilayer film structure is formed by sputtering a second layer film, and the object to be treated is transferred to the receiver 10 by operating the valves 15, 16, and 17.

従来構成及び動作によれば、センダー1及びレシーバ1
0は一つで且つ複数のスパッタ室は直列的に連結されて
いるために処理過程でトラブルが発生した場合には取り
出し時間が長くかかるだけでなく、第1のスパッタ室で
スパッタリングを行っている間、第2のスパッタ室は独
立の機能をもっては利用されない場合が多く、処理能率
は極めて5− 悪い欠点を有する。
According to the conventional configuration and operation, sender 1 and receiver 1
Since there is only one 0 and multiple sputtering chambers are connected in series, if a problem occurs during the processing process, it not only takes a long time to take out the sputtering chamber, but also sputtering is performed in the first sputtering chamber. However, the second sputtering chamber is often not used as an independent function, and has the disadvantage of extremely low processing efficiency.

(4)発明の目的 本発明は上記欠点に鑑みなされたものであり、複数組の
インライン型膜形成装置を連設する場合に各々の膜形成
装置に被処理物を独立的に搬入。
(4) Purpose of the Invention The present invention has been made in view of the above-mentioned drawbacks, and when a plurality of in-line film forming apparatuses are installed in series, the object to be processed is carried into each film forming apparatus independently.

1般出できるようにして能率的な膜形成処理のできる半
導体製造装置を提供することを目的とするものである。
It is an object of the present invention to provide a semiconductor manufacturing apparatus that can be made available to the general public and that can perform efficient film formation processing.

(5)発明の構成 そして、上記目的は本発明によれば、賎形成室の入出力
端に予備室を有する薄膜形成装置を複数組連設し、上記
複数の各予備室に被処理物を独立的に搬入または)絞出
可能な搬入、 1All出機構と、被処理物の1般送径
路を任意に設定可能な搬送機構とを具備してなることを
特徴とする半導体製造装置を提供することによって達成
される。
(5) Structure of the Invention According to the present invention, the above object is to provide a plurality of sets of thin film forming apparatuses each having a preparatory chamber at the input/output end of a film forming chamber, and to store a workpiece in each of the plurality of preparatory chambers. To provide a semiconductor manufacturing apparatus characterized in that it is equipped with a loading/unloading mechanism that can carry in or squeeze out items independently, and a conveyance mechanism that can arbitrarily set a single general conveyance path for a workpiece. This is achieved by

(6)発明の実施例 以下、本発明の一実施例を第3図乃至第6図について説
明する。
(6) Embodiment of the Invention An embodiment of the present invention will be described below with reference to FIGS. 3 to 6.

第3図は本発明の原理的な構成を示す系統図で6− あり、第4図乃至第6図は本発明の他の配列方法を示す
系統図である。
FIG. 3 is a system diagram showing the basic configuration of the present invention, and FIGS. 4 to 6 are system diagrams showing other arrangement methods of the present invention.

第3図において、INl及びI N 2は被処理物のウ
ェハ等が搬入される経路を示し、第1乃至第3の膜形成
装置20a 、 20b 、 20cは基本的には第1
図で述べたと同様の2組のロードロック(予備室)並び
にスパッタ室より構成され、スパッタ室前後のロートロ
ック部内にウェハ等の被処理物」二に形成された膜厚を
計測する膜厚計測手段22a。
In FIG. 3, INl and IN2 indicate paths through which wafers and the like to be processed are carried in, and the first to third film forming apparatuses 20a, 20b, 20c are basically
It consists of two sets of load locks (preliminary chambers) and a sputtering chamber similar to those shown in the figure, and film thickness measurement is used to measure the thickness of a film formed on a workpiece such as a wafer within the rotorlock section before and after the sputtering chamber. Means 22a.

22b 、 22Cを設けるとともにウェハの表面状態
を計測するため表面の反射率等を計測する表面計測手段
23a 、 23b 、 23cが配設されている。表
面計測手段23a 、 23b 、 23cからは第2
の膜形成装置20b、第3の膜形成装置20c、・・・
等のロードロック部に連通されてウェハを直列的に第1
の膜形成装置20a乃至第3の膜形成装置20Cと順次
必要な膜の積層数だけ1M人して多層膜形成を行うよう
になされ、さらに表面計測手段23a 、 23b 。
22b, 22C are provided, and surface measuring means 23a, 23b, 23c for measuring surface reflectance, etc. in order to measure the surface condition of the wafer are provided. From the surface measuring means 23a, 23b, 23c, the second
film forming apparatus 20b, third film forming apparatus 20c,...
The wafers are connected in series to the first
The film forming apparatus 20a to the third film forming apparatus 20C are used to form a multilayer film by 1M people for the required number of films to be laminated in sequence, and surface measuring means 23a, 23b are also provided.

23cには次のフォト工程等にウェハを進めるような出
力口0UT1.  OUT 2 、 OUT 3が設け
られている。勿論、図示しないが弁により第1図乃至第
2の膜形成装置に影響を与えないように排出がなされる
23c has an output port 0UT1 for advancing the wafer to the next photo process, etc. OUT 2 and OUT 3 are provided. Of course, although not shown, the gas is discharged by a valve so as not to affect the film forming apparatuses shown in FIGS. 1 and 2.

さらに人出口I N 2よりドライ前処理のような前処
理部21を通して各々の膜形成装置20a 、 20b
、2Qcの被処理物を並列的に搬入できるようにする。
Furthermore, each film forming device 20a, 20b passes through a pretreatment section 21 such as a dry pretreatment from the person exit IN2.
, 2Qc of workpieces can be carried in in parallel.

上記構成における被処理物の膜形成工程を説明すると、
例えば第1の膜形成装置20aにUtt人されたウェハ
が単層構造であれば、膜厚をロードロック内の膜厚計測
手段22aで計測し、さらに表面の反射率が被計測手段
23aで計測されて出力口0UT1より次のフォト工程
に送出される。
To explain the process of forming a film on the object to be treated in the above configuration,
For example, if the wafer placed in the first film forming apparatus 20a has a single layer structure, the film thickness is measured by the film thickness measuring means 22a in the load lock, and the reflectance of the surface is measured by the measuring means 23a. Then, it is sent out to the next photo process from the output port 0UT1.

被処理物が多層膜を形成する必要があり、且つ異種の金
属を連続的に成長させる場合には被処理物は第2の膜形
成装置20bに送り込まれ、第2N目の膜形成が終了し
た時点で再び第2の膜形成装置20bに連なるロードロ
ック内の膜厚並びに被計測手段22b、 23bで第2
層目の膜厚と、表面状態が検査され、例えば膜厚または
表面に異常を認めれば出力口OU T 2よりウェハ等
を取り出すことができ、良好であれば第3の膜形成装置
20Cに送られ、上記と同様に第3Nのスパッタリング
等を行い検査後に例えば出力口0UT2より出力させる
ことができる。
When the object to be processed needs to form a multilayer film and different types of metals are to be continuously grown, the object to be processed is sent to the second film forming device 20b, and the formation of the 2Nth film is completed. At this point, the film thickness in the load lock connected to the second film forming apparatus 20b and the second measuring means 22b and 23b are measured again.
The film thickness and surface condition of each layer are inspected. If an abnormality is found in the film thickness or surface, for example, the wafer etc. can be taken out from the output port OUT 2, and if it is in good condition, it is sent to the third film forming apparatus 20C. After performing the 3N sputtering or the like in the same manner as described above and performing the inspection, it can be output from the output port 0UT2, for example.

また、エソチング工程を経たために一度大気状態にさら
した被処理物に、さらに薄膜を成長させて多層構造とす
る場合には、途中のブランチ(第3図の点線24部分)
からドライ前処理部21に被処理物を与えて第1層目の
変質された表面を若干削りとり第2の膜形成装置20b
にて第2層目の膜形成を行うようにする。
In addition, when growing a thin film to form a multilayer structure on a workpiece that has been exposed to the atmosphere due to an ethoching process, intermediate branches (dotted line 24 in Figure 3)
The object to be treated is fed to the dry pre-treatment section 21, and the altered surface of the first layer is slightly scraped off to the second film forming device 20b.
Then, the second layer film is formed.

上記の各工程は、すなわち計測等も真空中で行われ、且
つ膜形成装置20a 、 20b 、 2Oc内にはウ
ェハ等の被処理物を加熱するための加熱室を有し所定の
温度になるよう調整されている。
Each of the above steps, including measurements, etc., is performed in a vacuum, and the film forming apparatuses 20a, 20b, and 2Oc have heating chambers for heating objects to be processed such as wafers, and are heated to a predetermined temperature. It has been adjusted.

上記構成及び動作は本発明の原理的な構成であり、いま
、膜厚計測手段22aと表面計測手段23a並びに膜形
成装置20aを含む1組の構成を20a′として表し、
同様に20b 、 22b 、 23bを含めて9− 20b′とし、20c 、 22c 、 23cを含む
めで20c′と表した半導体処理部、すなわち第4図の
構成によれば第1乃至第3の半導体処理部は直列的に構
成とされ、入出力口IN1〜I N 5 、 0UTI
〜OU T 4から別種の被処理物を容易に搬入、 1
lli出できる。
The above configuration and operation are the basic configuration of the present invention, and a set of configurations including the film thickness measuring means 22a, the surface measuring means 23a, and the film forming apparatus 20a is represented as 20a'.
Similarly, according to the structure of FIG. 4, the semiconductor processing section is designated as 9-20b' including 20b, 22b, and 23b, and 20c' includes 20c, 22c, and 23c, that is, the first to third semiconductor processing sections. The sections are configured in series, with input/output ports IN1 to IN5, 0UTI.
~ Easily transport different types of workpieces from OUT 4, 1
I can get it out.

第5図に示すものはロードロック内に1本の通路25a
を設け、該通路に対し半導体処理部20a ’ 。
The one shown in FIG. 5 has one passage 25a in the load lock.
A semiconductor processing section 20a' is provided for the passage.

2Qb ′、 20C’を並列的に配設するとともに各
処理部の能力のバランスをとるためにハソファステーシ
ョン26a 、 26bを通路25bに対し並列的に配
設した場合である。
2Qb' and 20C' are arranged in parallel, and in order to balance the capabilities of each processing section, the haphastations 26a and 26b are arranged in parallel to the passage 25b.

さらに、第6図の場合は半導体処理部20a’。Furthermore, in the case of FIG. 6, there is a semiconductor processing section 20a'.

20b ’ 、 20C′の入出力口に1ffl路25
a 、 25bを設は通路間をシャントするように処理
室を配設した場合であり、上記各実施例に示された通路
は勿論ロードロック内に配置され真空状態を保持できる
よう構成されている。
1ffl path 25 at the input/output port of 20b' and 20C'
25a and 25b are the cases in which the processing chamber is arranged so as to shunt between the passages, and the passages shown in each of the above embodiments are, of course, placed in a load lock and configured to maintain a vacuum state. .

(7)発明の効果 以上、詳細に説明したように本発明の半導体製−10− 造装置によれば、制御系統を各処理部及びIlll糸送
分けることができるために被処理物毎のきめ細かい制御
、管理が可能であり、さらに各処理室が各々独立してい
るので処理工程中に発生したトラブルが別の処理室に影
響を与えることがなく、各々の処理物の機能を充分に発
揮させることができるため全体の稼働効率を高めること
ができる特徴を有する。
(7) Effects of the Invention As explained in detail above, according to the semiconductor manufacturing apparatus of the present invention, the control system can be divided into each processing section and Illll thread feeding, so that fine-grained control can be achieved for each workpiece. Control and management are possible, and since each processing chamber is independent, troubles that occur during the processing process will not affect other processing chambers, allowing each processing item to perform its functions to its fullest. It has the feature of increasing overall operating efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のインライン式のスパッタ装置の路線的な
系統図、第2図は従来の2組のインライン式のスパッタ
装置を直列的に配設した場合の路線的な系統図、第3図
は本発明の半導体製造装置の原理的系統図、第4図乃至
第6図は本発明の他の配列方法を説明するための系統図
である。 1・・・センダー、  2. 4. 6. 9.11゜
12、15.18.19・・・弁、  7,14・・・
メインパルプ、   3.8・・・ロードロック、5.
13・・・スパッタ室、10・・・レシーバ、20a、
 20b、 20c −−・膜形成装置、 21・・・
前処理部、 22a 、 22b 、 22c・・・膜
厚計測手段、  23a、 23b、 23c −−・
表面計測手段。 特許出願人  富士通株式会社 13 回 IN2 笛4 図 )85図 箋6(2) 20a゛ (半 為イ本       −メ f  処1  汽 2シ               25b牛轟抹 ↑f  よう  −Xl 半傳林) 処渠   Δ 53− 11           11
Figure 1 is a line system diagram of a conventional in-line sputtering device, Figure 2 is a line system diagram when two sets of conventional in-line sputter units are arranged in series, and Figure 3 is a line diagram of a conventional in-line sputtering apparatus. 1 is a principle system diagram of the semiconductor manufacturing apparatus of the present invention, and FIGS. 4 to 6 are system diagrams for explaining other arrangement methods of the present invention. 1...Sender, 2. 4. 6. 9.11゜12, 15.18.19... valve, 7,14...
Main pulp, 3.8... Load lock, 5.
13... Sputtering chamber, 10... Receiver, 20a,
20b, 20c --- Film forming device, 21...
Pre-processing section, 22a, 22b, 22c... Film thickness measuring means, 23a, 23b, 23c ---
Surface measurement means. Patent Applicant: Fujitsu Limited 13 times IN2 Flute 4 Figure) 85 Notebook 6 (2) 20a Δ 53- 11 11

Claims (1)

【特許請求の範囲】 (1)膜形成室の入出力端に予備室を有する薄膜形成装
置を複数組連設し、上記複数の各予備室に被処理物を独
立的に搬入または搬出可能な搬入。 搬出機構と、被処理物の搬送径路を任意に設定可能な搬
送機構とを具備してなることを特徴とする特許請求の範
囲第1項記載の半導体製造装置。 (2)上記薄膜形成装置の一つ以上において、金属薄膜
を形成することを特徴とする半導体製造装置。 (3)上記予備室は真空に保持され被処理物の金属表面
の変質を防止するようにしてなることを特徴とする特許
請求の範囲第1項記載の半導体製造装置。 (3)上記予備室に被処理物の物理量を計測するための
計測手段を配設してなることを特徴とする特許請求の範
囲第1項記載の半導体製造装置。 (5)物理量計測手段によって被処理物の膜厚を計測す
ることを特徴とする特許請求の範囲第3項記載の半導体
製造装置。 (6)物理量の計測手段によって被処理物の表面反射率
を計測することを特徴とする特許請求の範囲第3項記載
の半導体製造装置。
[Claims] (1) A plurality of sets of thin film forming apparatuses having preparatory chambers at the input and output ends of the film forming chamber are arranged in series, and objects to be processed can be independently carried in or taken out from each of the plurality of preparatory chambers. Import. 2. A semiconductor manufacturing apparatus according to claim 1, comprising: a carry-out mechanism; and a conveyance mechanism capable of arbitrarily setting a conveyance path for the workpiece. (2) A semiconductor manufacturing apparatus, characterized in that one or more of the above thin film forming apparatuses forms a metal thin film. (3) The semiconductor manufacturing apparatus according to claim 1, wherein the preliminary chamber is maintained in a vacuum to prevent deterioration of the metal surface of the object to be processed. (3) The semiconductor manufacturing apparatus according to claim 1, wherein the preliminary chamber is provided with a measuring means for measuring the physical quantity of the object to be processed. (5) The semiconductor manufacturing apparatus according to claim 3, wherein the film thickness of the object to be processed is measured by a physical quantity measuring means. (6) The semiconductor manufacturing apparatus according to claim 3, wherein the surface reflectance of the object to be processed is measured by a physical quantity measuring means.
JP23379282A 1982-12-29 1982-12-29 Semiconductor device manufacturing apparatus Pending JPS59124712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23379282A JPS59124712A (en) 1982-12-29 1982-12-29 Semiconductor device manufacturing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23379282A JPS59124712A (en) 1982-12-29 1982-12-29 Semiconductor device manufacturing apparatus

Publications (1)

Publication Number Publication Date
JPS59124712A true JPS59124712A (en) 1984-07-18

Family

ID=16960636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23379282A Pending JPS59124712A (en) 1982-12-29 1982-12-29 Semiconductor device manufacturing apparatus

Country Status (1)

Country Link
JP (1) JPS59124712A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321827A (en) * 1986-07-15 1988-01-29 Mitsubishi Electric Corp Semiconductor manufacturing equipment
JPH02294018A (en) * 1989-05-09 1990-12-05 Hitachi Ltd Film formation device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979783A (en) * 1972-12-08 1974-08-01
JPS52139378A (en) * 1976-05-17 1977-11-21 Hitachi Ltd Integrated treatment apparatus for semiconductor wafers
JPS5787120A (en) * 1980-11-20 1982-05-31 Matsushita Electric Ind Co Ltd Method and device for plasma cvd

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979783A (en) * 1972-12-08 1974-08-01
JPS52139378A (en) * 1976-05-17 1977-11-21 Hitachi Ltd Integrated treatment apparatus for semiconductor wafers
JPS5787120A (en) * 1980-11-20 1982-05-31 Matsushita Electric Ind Co Ltd Method and device for plasma cvd

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321827A (en) * 1986-07-15 1988-01-29 Mitsubishi Electric Corp Semiconductor manufacturing equipment
JPH02294018A (en) * 1989-05-09 1990-12-05 Hitachi Ltd Film formation device

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