JPH053174A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH053174A
JPH053174A JP15357291A JP15357291A JPH053174A JP H053174 A JPH053174 A JP H053174A JP 15357291 A JP15357291 A JP 15357291A JP 15357291 A JP15357291 A JP 15357291A JP H053174 A JPH053174 A JP H053174A
Authority
JP
Japan
Prior art keywords
wafer
chamber
chambers
processing
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15357291A
Other languages
Japanese (ja)
Inventor
Minoru Inoue
實 井上
Yasutaka Ozaki
康孝 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15357291A priority Critical patent/JPH053174A/en
Publication of JPH053174A publication Critical patent/JPH053174A/en
Withdrawn legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To provide a wafer processing method where wafers are set uniform in processing condition from first, where the wafer processing method is that chambers which carry out wafer processing separately are employed, and wafers are successively transferred to the chambers from loaders through a common wafer transfer means and finally housed in unloaders. CONSTITUTION:Provided that a time required for transferring a wafer is represented by t, the number of chambers is N, and the wafer processing time of each chamber is represented by Ti, the residence time T of each wafer in the chamber is set to a certain value to satisfy formulas, T>tXN, T > maximum Ti, and a time, T-Ti, of each chamber is defined as a waiting time of a wafer, and a processing procedure is so constituted that a following wafer is transferred to a first chamber when a first wafer is transferred to a following chamber from a first chamber. In a figure, 1-5 denote the processes of a first to a fifth wafer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に、個別にウエーハ処理を行う複数のチャン
バを用いて順次に行う一連のウエーハ処理を、複数のウ
エーハに対し逐次に施す際の方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a plurality of wafers which are sequentially subjected to a series of wafer treatments which are sequentially performed using a plurality of chambers for individually performing wafer treatments. Regarding the method of the occasion.

【0002】[0002]

【従来の技術】近年、半導体装置製造のウエーハプロセ
スでは、集積の高密度化に伴い配線がAlまたはAl合金の
単層からTiN上にAl合金を積み重ねた積層配線になりつ
つある。それに伴い配線膜の形成に使用するスパッタ装
置も個別にウエーハ処理を行う複数のチャンバを備えた
マルチチャンバ装置となりつつある。
2. Description of the Related Art In recent years, in a wafer process for manufacturing a semiconductor device, the wiring is becoming a laminated wiring in which an Al or Al alloy single layer is stacked on top of TiN and an Al alloy is stacked with the increase in integration density. Along with this, a sputtering apparatus used for forming a wiring film is becoming a multi-chamber apparatus including a plurality of chambers for individually performing wafer processing.

【0003】図2は上記マルチチャンバ装置の一例の構
成図である。同図において、1a〜1dはチャンバ、2はロ
ード、3はアンロード、4はウエーハ搬送手段、であ
る。
FIG. 2 is a block diagram of an example of the above multi-chamber apparatus. In the figure, 1a to 1d are chambers, 2 is load, 3 is unload, and 4 is wafer transfer means.

【0004】4個のチャンバ1a〜1dはそれぞれが個別に
ウエーハ処理(スパッタ)を行うチャンバであり、ウエ
ーハの搬入・搬出がウエーハ搬送手段4によってなされ
る。ロード2は、未処理のウエーハを供給する箇所であ
り、複数の未処理ウエーハを収納したウエーハキャリア
がセットされて、ウエーハの搬出がウエーハ搬送手段4
よってなされる。
Each of the four chambers 1a to 1d is a chamber for carrying out wafer processing (sputtering) individually, and wafers are loaded and unloaded by the wafer transfer means 4. The load 2 is a portion for supplying unprocessed wafers, a wafer carrier storing a plurality of unprocessed wafers is set, and the wafer is unloaded to the wafer transfer means 4.
Done by

【0005】アンロード3は、チャンバ1a〜1dによる処
理を終えたウエーハを収める箇所であり、ウエーハの搬
入がウエーハ搬送手段4よってなされる。ウエーハ搬送
手段4は、例えば一個のロボットアームであり、ロード
2,チャンバ1a〜1d,アンロード3に対し共通に使用し
てウエーハの上記搬出・搬入を含む相互間の搬送を行
う。
The unload 3 is a part for accommodating the wafers which have been processed by the chambers 1a to 1d, and the wafer transfer means 4 carries the wafers in. The wafer transfer means 4 is, for example, one robot arm, and is commonly used for the load 2, the chambers 1a to 1d, and the unload 3 to transfer the wafers to and from each other.

【0006】そして1枚のウエーハに着目すれば、ロー
ド2からチャンバ1aに搬送 → チャンバ1aによる処理
→ チャンバ1aからチャンバ1bに搬送 → チャンバ
1bによる処理 → チャンバ1bからチャンバ1cに搬送
→ チャンバ1cによる処理→ チャンバ1cからチャンバ
1dに搬送 → チャンバ1dによる処理 → チャンバ1d
からアンロード3に搬送、という経過となり、これで一
連のウエーハ処理を終了する。
If one wafer is focused on, it is transferred from the load 2 to the chamber 1a → processing by the chamber 1a → transfer from the chamber 1a to the chamber 1b → chamber
Processing by 1b → Transfer from chamber 1b to chamber 1c
→ Processing by chamber 1c → Chamber 1c to chamber
Transfer to 1d → Processing by chamber 1d → Chamber 1d
Then, the unloading 3 is carried, and a series of wafer processing is completed.

【0007】このことからこのマルチチャンバ装置は、
先行のウエーハをチャンバ1bに搬送した後、空きとなっ
たチャンバ1aに次のウエーハを搬送するといった手順の
操作を行うことにより、上記一連のウエーハ処理を複数
のウエーハに対し逐次に即ち時間ずれを持たせて並行処
理する様態で施すことができる。
From this, this multi-chamber apparatus is
After the preceding wafer is transferred to the chamber 1b, the next wafer is transferred to the vacant chamber 1a, so that the above-mentioned series of wafer processes are sequentially performed with respect to a plurality of wafers, that is, a time lag occurs. It can be given in the form of holding and performing parallel processing.

【0008】そして従来の上記操作は、チャンバ1a〜1d
の何れにおいてもウエーハ処理が終わったところでそこ
のウエーハを次の箇所へ搬送することを原則にしてい
た。しかしながら、ロード2からの1枚目のウエーハは
無条件にその原則を守ることができるが、例えばチャン
バ1bの処理時間がチャンバ1aのそれより長い場合には、
2枚目以降のウエーハは、チャンバ1aによる処理が終わ
った時点にチャンバ1bが塞がっているため、チャンバ1b
への搬送にチャンバ1bが空くまでの待ち時間が生じてい
た。
The above-mentioned conventional operation is performed in the chambers 1a to 1d.
In any of the above, the principle was to transport the wafer there to the next location when the wafer processing was completed. However, the first wafer from load 2 can obey the principle unconditionally, for example, if the processing time of chamber 1b is longer than that of chamber 1a,
For the second and subsequent wafers, since the chamber 1b is closed when the processing by the chamber 1a is completed, the chamber 1b is closed.
There was a waiting time until the chamber 1b was emptied for the transfer to.

【0009】そしてウエーハ処理がスパッタであるため
ウエーハがこの待ち時間に応じた温度低下を起こして、
1枚目と2枚目のウエーハの間では、チャンバ1bによる
処理開始時のウエーハ温度に差が生じていた。処理開始
時ウエーハ温度の上記待ち時間による変化様相は図3に
示される。なお、処理開始までの温度低下には搬送中の
温度低下も含まれるが、搬送の時間は1枚目も2枚目も
同じである。
Since the wafer processing is sputtering, the temperature of the wafer is lowered according to this waiting time,
There was a difference in wafer temperature between the first and second wafers at the start of processing by the chamber 1b. The mode of change of the wafer temperature at the start of processing due to the waiting time is shown in FIG. It should be noted that the temperature decrease until the start of processing includes the temperature decrease during conveyance, but the conveyance time is the same for the first and second sheets.

【0010】このことにより1枚目のウエーハは2枚目
以降のウエーハと処理条件に差が生ずることになるの
で、従来は、未処理のウエーハをウエーハキャリアに収
納する際に1枚目となるウエーハをダミーウエーハにし
て、処理条件が揃う2枚目以降を製品用のウエーハにし
ていた。
As a result, the processing condition of the first wafer is different from that of the second and subsequent wafers. Therefore, conventionally, the first wafer is used when the unprocessed wafer is stored in the wafer carrier. The wafer was used as a dummy wafer, and the second and subsequent wafers under the same processing conditions were used as product wafers.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、ダミー
ウエーハを介在させることは、コストや作業効率の面か
ら望ましいものではない。然も上述の原則を基にすれ
ば、チャンバ1a〜1dの処理時間の相互関係によっては、
ダミーウエーハを4枚にしなければならない場合もでて
くる。
However, interposing a dummy wafer is not desirable in terms of cost and work efficiency. However, based on the above principle, depending on the interrelationship of the processing times of the chambers 1a to 1d,
In some cases, you will have to use four dummy wafers.

【0012】そこで本発明は、半導体装置の製造方法に
おいて、上述のようなマルチチャンバ装置を使用して一
連のウエーハ処理を複数のウエーハに対し逐次に処理す
る際に、当初にダミーウエーハを使用することなく、最
初のウエーハから処理条件が揃うようにさせる方法の提
供を目的とする。
Therefore, according to the present invention, in the method of manufacturing a semiconductor device, when a series of wafers are sequentially processed for a plurality of wafers by using the above-described multi-chamber apparatus, a dummy wafer is initially used. The purpose of the present invention is to provide a method for ensuring that the processing conditions are met from the first wafer without being processed.

【0013】[0013]

【課題を解決するための手段】上記目的を達成するため
に、本発明の方法においては、個別にウエーハ処理を行
う複数のチャンバを用い、共通のウエーハ搬送手段によ
りウエーハをローダから該チャンバの各々に順次に搬送
し最後にアンローダに収めて行う一連のウエーハ処理
を、複数のウエーハに対し逐次に施すに際して、個々の
ウエーハ搬送に要する時間をt、チャンバの数をN、個
々のチャンバのウエーハ処理時間をTi として、個々の
チャンバ内にウエーハを滞留させる時間Tをt×Nより
大きく且つTi の最大より大きな一定値に設定し、個々
のチャンバにおける時間T−Ti を待ち時間としてウエ
ーハを該チャンバ内に待機させ、最初のウエーハが最初
のチャンバから次のチャンバに搬送されたところで次の
ウエーハを最初のチャンバに搬送するといった手順で、
上記一連のウエーハ処理を複数のウエーハに対し逐次に
施すことを特徴としている。
In order to achieve the above object, in the method of the present invention, a plurality of chambers for individually performing wafer processing are used, and the wafers are transferred from the loader to each of the chambers by a common wafer transfer means. When sequentially performing a series of wafer processing in which a plurality of wafers are sequentially transferred and finally stored in an unloader, the time required to transfer each wafer is t, the number of chambers is N, and the wafer processing of each chamber is With the time T i , the time T for keeping the wafer in each chamber is set to a constant value larger than t × N and larger than the maximum of T i , and the time T−T i in each chamber is used as the waiting time. In the chamber, and when the first wafer is transferred from the first chamber to the next chamber, the next wafer is transferred to the first chamber. In the procedure, such as to convey to the server,
It is characterized in that the above-mentioned series of wafer processing is sequentially performed on a plurality of wafers.

【0014】[0014]

【作用】上記滞留時間Tを上述のように設定することに
より、個々のチャンバはそれぞれの処理時間Ti が確保
され、然も、上記ウエーハ搬送手段によるウエーハ搬送
を常に滞留時間Tが終わったところで行うことができる
ようになり、個々のチャンバにおける待ち時間T−Ti
は、複数のウエーハに対し最初のウエーハから揃うよう
になる。
By setting the dwell time T as described above, the processing time T i of each chamber is secured, and the wafer transport by the wafer transport means is always performed at the end of the dwell time T i. The waiting time T-T i in the individual chamber
Will be aligned to the first wafer for multiple wafers.

【0015】従って、個々のチャンバにおける処理開始
時のウエーハ温度がすべてのウエーハで揃うようにな
り、当初にダミーウエーハを使用することなく、最初の
ウエーハから処理条件が揃うようにさせることができ
る。
Therefore, the wafer temperature at the start of processing in each chamber can be made uniform for all the wafers, and the processing conditions can be made to be the same from the first wafer without using a dummy wafer at the beginning.

【0016】[0016]

【実施例】以下本発明による方法の実施例について図1
のタイムチャートを用いて説明する。この実施例は、先
に図2を用いて説明したマルチチャンバ装置を使用する
場合のものである。
FIG. 1 shows an embodiment of the method according to the present invention.
The time chart will be described. This embodiment is a case where the multi-chamber apparatus described above with reference to FIG. 2 is used.

【0017】従って先に述べたように、1枚のウエーハ
に着目すれば、ロード2からチャンバ1aに搬送 → チ
ャンバ1aによる処理 → チャンバ1aからチャンバ1bに
搬送→ チャンバ1bによる処理 → チャンバ1bからチ
ャンバ1cに搬送 → チャンバ1cによる処理 → チャ
ンバ1cからチャンバ1dに搬送 → チャンバ1dによる処
理 → チャンバ1dからアンロード3に搬送、という経
過で一連のウエーハ処理を終了させる。いうまでもなく
この間の搬送はすべてを共通のウエーハ搬送手段4によ
って行う。
Therefore, as described above, if attention is paid to one wafer, it is transferred from the load 2 to the chamber 1a → process by the chamber 1a → transfer from the chamber 1a to the chamber 1b → process by the chamber 1b → chamber 1b to the chamber Transfer to 1c → Process by chamber 1c → Transfer from chamber 1c to chamber 1d → Process by chamber 1d → Transfer from chamber 1d to unload 3 A series of wafer processing is completed. Needless to say, all the wafers are conveyed by the common wafer conveying means 4 during this period.

【0018】図1において、〜は1枚目〜5枚目の
ウエーハそれぞれの経過で搬送及び各チャンバ1a〜1dに
おける滞留の時点を示し、ロード2からの搬送で始まり
アンロード3への搬送で終わる。そして、tは個々のウ
エーハ搬送に要する時間、Tは個々のチャンバ1a〜1d内
にウエーハを滞留させる時間、Ti は個々のチャンバ1a
〜1dのウエーハ処理時間、T−Ti は個々のチャンバ1a
〜1dにおいてウエーハ処理後にウエーハを待機させる待
ち時間、である。
In FIG. 1, symbols (1) to (5) show the time points of transfer and retention in the chambers 1a to 1d after the first to fifth wafers, respectively, starting from transfer from the load 2 to transfer to the unload 3. Over. Further, t is a time required for transporting each wafer, T is a time for keeping the wafer in each of the chambers 1a to 1d, and T i is each chamber 1a.
Wafer processing time ~1d, T-T i is the individual chambers 1a
In 1d, the waiting time for waiting the wafer after the wafer processing.

【0019】この実施例は、先に述べたように、先行の
ウエーハをチャンバ1bに搬送した後に次のウエーハをチ
ャンバ1aに搬送するといった手順の操作を行うことによ
り、上記一連のウエーハ処理を複数のウエーハに対し逐
次に即ち時間ずれを持たせて並行処理する様態で施して
いるが、従来の場合と異なる点は、上記操作において、
チャンバ1a〜1dの何れにおいても滞留時間Tが終わった
ところでそこのウエーハを次の箇所へ搬送していること
である。
In this embodiment, as described above, by carrying out the procedure of carrying the preceding wafer to the chamber 1b and then carrying the next wafer to the chamber 1a, the above-mentioned series of wafer treatments are performed. The wafers are sequentially processed, that is, in parallel with a time lag, but the difference from the conventional case is that in the above operation,
In any of the chambers 1a to 1d, the wafer there is transported to the next location when the residence time T ends.

【0020】そして滞留時間Tは、搬送時間t×4(チ
ャンバ数)より大きく且つ処理時間Ti の最大より大き
な一定値に設定して、全チャンバ1a〜1dに対し同じに揃
えてある。このことにより、すべてのチャンバ1a〜1dは
それぞれの処理時間Ti が確保されており、然も、ウエ
ーハ搬送はどの場合も個々のチャンバ1a〜1dの待ち時間
T−Ti を変更することなく行うことができる。
The residence time T is set to a constant value that is greater than the transfer time t × 4 (the number of chambers) and greater than the maximum of the processing time T i , and is set to be the same for all the chambers 1a to 1d. As a result, all the chambers 1a to 1d have their respective processing times T i secured, and in any case, the wafer transfer does not change the waiting time T-T i of the individual chambers 1a to 1d. It can be carried out.

【0021】従って、個々のチャンバ1a〜1dにおける処
理開始時のウエーハ温度がすべてのウエーハで揃うよう
になり、当初にダミーウエーハを使用することなく、最
初のウエーハから処理条件が揃うようにさせることがで
きる。そしてこのことは、チャンバ1a〜1dの処理時間T
i の相互関係が如何様になっても成立する。
Therefore, the wafer temperature at the start of processing in each of the chambers 1a to 1d can be made uniform for all the wafers, and the processing conditions can be adjusted from the first wafer without using a dummy wafer at the beginning. You can And this means that the processing time T of the chambers 1a to 1d
It holds regardless of the mutual relationship of i .

【0022】なお、上述の実施例はチャンバ数が4の場
合であるが、本発明が任意のチャンバ数に対して有効で
あることは上述の説明から明らかである。
Although the number of chambers is four in the above embodiment, it is apparent from the above description that the present invention is effective for any number of chambers.

【0023】[0023]

【発明の効果】以上説明したように本発明によれば、半
導体装置の製造方法に係り、特に、個別にウエーハ処理
を行う複数のチャンバを用いて順次に行う一連のウエー
ハ処理を、複数のウエーハに対し逐次に施す際の方法に
関し、当初にダミーウエーハを使用することなく、最初
のウエーハから処理条件が揃うようにさせる方法が提供
されて、製品用ウエーハの処理条件を揃えるためにダミ
ーウエーハを介在させた従来方法によるコストや作業効
率の面の不具合を解消させる効果がある。
As described above, according to the present invention, a method for manufacturing a semiconductor device, and in particular, a series of wafer processes sequentially performed by using a plurality of chambers for individually performing a wafer process, is performed. Regarding the method for sequentially applying the above, a method is provided in which the processing conditions are adjusted from the first wafer without using the dummy wafer at the beginning, and the dummy wafer is used to adjust the processing conditions of the product wafer. This has the effect of eliminating defects in terms of cost and work efficiency due to the intervening conventional method.

【図面の簡単な説明】[Brief description of drawings]

【図1】 実施例のタイムチャートFIG. 1 is a time chart of an embodiment.

【図2】 マルチチャンバ装置の一例の構成図FIG. 2 is a block diagram of an example of a multi-chamber device.

【図3】 処理開始時のウエーハ温度の待ち時間による
変化を示す図
FIG. 3 is a diagram showing changes in wafer temperature due to waiting time at the start of processing.

【符号の説明】[Explanation of symbols]

1a〜1d チャンバ 2 ローダ 3 アンローダ 4 ウエーハ搬送手段 〜 1枚目〜5枚目のウエーハそれぞれの経過 t 個々のウエーハ搬送に要する時間 T 個々のチャンバ内にウエーハを滞留させる時間 Ti 個々のチャンバのウエーハ処理時間 T−Ti 個々のチャンバのウエーハを待機させる待ち
時間
1a to 1d Chamber 2 Loader 3 Unloader 4 Wafer transfer means 1st to 5th wafers elapsed t t Time required to transfer individual wafers T Time to retain wafers in individual chambers Ti i Individual chambers Wafer processing time T-T i Waiting time for waiting wafers in individual chambers

Claims (1)

【特許請求の範囲】 【請求項1】 個別にウエーハ処理を行う複数のチャン
バを用い、共通のウエーハ搬送手段によりウエーハをロ
ーダから該チャンバの各々に順次に搬送し最後にアンロ
ーダに収めて行う一連のウエーハ処理を、複数のウエー
ハに対し逐次に施すに際して、個々のウエーハ搬送に要
する時間をt、チャンバの数をN、個々のチャンバのウ
エーハ処理時間をTi として、個々のチャンバ内にウエ
ーハを滞留させる時間Tをt×Nより大きく且つTi
最大より大きな一定値に設定し、個々のチャンバにおけ
る時間T−Ti を待ち時間としてウエーハを該チャンバ
内に待機させ、最初のウエーハが最初のチャンバから次
のチャンバに搬送されたところで次のウエーハを最初の
チャンバに搬送するといった手順で、上記一連のウエー
ハ処理を複数のウエーハに対し逐次に施すことを特徴と
する半導体装置の製造方法。
Claim: What is claimed is: 1. A plurality of chambers for individually processing wafers are used, a wafer is sequentially transferred from a loader to each of the chambers by a common wafer transfer means, and finally stored in an unloader. When sequentially performing the wafer processing of a plurality of wafers, the time required for transporting each wafer is t, the number of chambers is N, and the wafer processing time of each chamber is T i. time is the residence T set with a fixed value than the maximum larger and T i from t × N, the wafer is waiting in the chamber a time T-T i in individual chambers as latency, the first wafer is first When the next wafer is transferred from one chamber to the next chamber, the next wafer is transferred to the first chamber. A method of manufacturing a semiconductor device, wherein a plurality of wafers are sequentially processed.
JP15357291A 1991-06-26 1991-06-26 Manufacture of semiconductor device Withdrawn JPH053174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15357291A JPH053174A (en) 1991-06-26 1991-06-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15357291A JPH053174A (en) 1991-06-26 1991-06-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH053174A true JPH053174A (en) 1993-01-08

Family

ID=15565427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15357291A Withdrawn JPH053174A (en) 1991-06-26 1991-06-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH053174A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285126A (en) * 2004-03-29 2005-10-13 Palo Alto Research Center Inc Method and system for self-synchronization of modular production system
JP2007214551A (en) * 1999-06-23 2007-08-23 Asml Us Inc Robot pre-arrangement in wafer processing system
US7630785B2 (en) 2005-01-07 2009-12-08 Tokyo Electron Limited Substrate processing system for setting uniform module cycle length and access control time lag in two pipeline processing systems
US9845531B2 (en) 2013-08-09 2017-12-19 Tokyo Electron Limited Substrate processing system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214551A (en) * 1999-06-23 2007-08-23 Asml Us Inc Robot pre-arrangement in wafer processing system
JP2005285126A (en) * 2004-03-29 2005-10-13 Palo Alto Research Center Inc Method and system for self-synchronization of modular production system
US7630785B2 (en) 2005-01-07 2009-12-08 Tokyo Electron Limited Substrate processing system for setting uniform module cycle length and access control time lag in two pipeline processing systems
US9845531B2 (en) 2013-08-09 2017-12-19 Tokyo Electron Limited Substrate processing system

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