JPS59124149A - Manufacture of ceramic circuit substrate - Google Patents

Manufacture of ceramic circuit substrate

Info

Publication number
JPS59124149A
JPS59124149A JP23370582A JP23370582A JPS59124149A JP S59124149 A JPS59124149 A JP S59124149A JP 23370582 A JP23370582 A JP 23370582A JP 23370582 A JP23370582 A JP 23370582A JP S59124149 A JPS59124149 A JP S59124149A
Authority
JP
Japan
Prior art keywords
ceramic circuit
green sheet
binder
copper paste
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23370582A
Other languages
Japanese (ja)
Other versions
JPH035075B2 (en
Inventor
Hirozo Yokoyama
横山 博三
Koichi Niwa
丹羽 紘一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23370582A priority Critical patent/JPS59124149A/en
Publication of JPS59124149A publication Critical patent/JPS59124149A/en
Publication of JPH035075B2 publication Critical patent/JPH035075B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867Applying pastes or inks, e.g. screen printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To facilitate burning of a green sheet and a copper paste in N2 as a unitary body, by providing the same organic binder in the green sheet for a ceramic circuit substrate and for the copper paste for forming a conductor circuit. CONSTITUTION:On a green sheet for ceramic circuit substrate, which includes a 10% acrylic resin as a binder, a conductor circuit is formed by using a copper paste, which includes 5.1% of the same acrylic resin as a binder. After the lamination, heating and compression are performed. Then, the laminated body is burned in N2 at the maximum temperature of 950 deg.C for 10min. In this constitution, the binder is perfectly flown away, residual carbon is not present around the conductor of the substrate, and the excellent ceramic circuit having no swelled parts and the like can be obtained.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明はセラミック回路基板用グリーンシートと導体形
成用銅ペーストのバインダー組成が同一であり、グリー
ンシートと銅ペーストの一体焼成によってセラミック回
路基板を製造する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention is characterized in that the binder composition of the green sheet for a ceramic circuit board and the copper paste for forming a conductor are the same, and that the ceramic circuit board is manufactured by integrally firing the green sheet and the copper paste. Relating to a method of manufacturing.

(2)技術の背景 1柱が羊純で、コストが安価なセラミック回路基板の製
法が要望されている。
(2) Background of the technology There is a need for a low-cost manufacturing method for ceramic circuit boards, one of which is pure sheep.

(3)従来技術と問題点 グリーンシートに市販銅ペースト全印刷し、これらシー
ト全槓贋した後、N2雰囲気焼成を行ないセラミック回
路基板全作製した場合、次のよう疫ことか起こる。
(3) Prior Art and Problems When all of the green sheets are printed with commercially available copper paste, all of these sheets are counterfeited, and the entire ceramic circuit board is manufactured by firing in an N2 atmosphere, the following problems occur.

市販銅ペーストはグリーンシートと異なるバインダー組
成であるため、グリーンシートと一体焼成ではバインダ
ーが完全に飛散せす、セラミック中にカーボンとして導
体周辺に残存する欠点がある。
Commercially available copper paste has a binder composition different from that of the green sheet, so when it is fired together with the green sheet, the binder is completely scattered, and it has the drawback that it remains as carbon in the ceramic around the conductor.

(4)発明の目8つ 本発明は上述の欠点に鑑みなされたもので、グリーンシ
ートと銅ペーストのIQ2雰囲気による一体焼成を行な
い、セラミック中にカーボンが残存ぜす、ふくれなどが
生じないセラミック回路基板の製造法を提供することに
ある。
(4) Eight points of the invention The present invention was made in view of the above-mentioned drawbacks.The present invention is made by integrally firing a green sheet and a copper paste in an IQ2 atmosphere, so that no carbon remains in the ceramic and no blistering occurs. An object of the present invention is to provide a method for manufacturing a circuit board.

(5)発明の構成 本発明はセラミック回路基板用グリーンシートと導体回
路形成用銅ペーストの有機バインダーを同−としたこと
を特徴とするセラミンク回路基板の製造方法によシ達成
さする0 本発明はセラミック回路基板用グリーンシートと導体回
路形ノ戎用銅ペーストの有機バインダーが同一である/
こめ、N2雰囲気によるグリーンシート銅ペーストの一
体焼成を容易にしたものである。
(5) Structure of the Invention The present invention is achieved by a method for manufacturing a ceramic circuit board characterized in that the green sheet for a ceramic circuit board and the organic binder of the copper paste for forming a conductor circuit are the same. The organic binder of the green sheet for ceramic circuit board and the copper paste for conductive circuit type are the same/
This facilitates the integral firing of the green sheet copper paste in an N2 atmosphere.

(6)発明の実施例 以下、本発明について実施例を参照して説明する。セラ
ミック回路基板の作製はグリーンシートと銅ペーストを
N2雰囲気によって一体焼成で行なう。そこでN、雰囲
気焼成で、完全に飛散し右下ボンの残存しない有機バイ
ンダーをグリー:/シートおよび銅ペーストのバインダ
ーとして、使用することが重要となる0各柚有機ノくイ
ンダーの中から上記条件を満足するアクリル樹脂を今回
の実施例に使用した。
(6) Examples of the Invention The present invention will be described below with reference to Examples. The ceramic circuit board is manufactured by integrally firing the green sheet and copper paste in an N2 atmosphere. Therefore, it is important to use N, the organic binder that is completely dispersed by firing in an atmosphere and does not leave any residue in the lower right bong as a binder for the sheet and copper paste. An acrylic resin that satisfies the following was used in this example.

回路基板の作製には、アクリルバインダーを10チ含ん
だ、厚さ0.4鴎、外形寸法150X150i11のグ
リーンシートを用いた。このグリーンシート上に、グリ
ーンシートと同一のアクリルパインダーツシュステンレ
ススクリーンを用いて印刷し、導体回路を形成した。
A green sheet containing 10 sheets of acrylic binder, having a thickness of 0.4 mm and an external dimension of 150×150×11 was used to manufacture the circuit board. A conductor circuit was formed on this green sheet by printing using the same acrylic pine dart stainless steel screen as the green sheet.

このようにして導体回路を形成したグリーンシート6層
分【、圧力10〜30Mpa、温1f90〜130゜加
圧時間4〜15分の種々の条件で積層した。これらの積
層グリーンシートをN2雰囲気において最高温度950
℃で10分間焼成し、セラミック回路基板を得た。これ
らの基板の導体周辺はカーボンの残存が認められず、完
全にバインダーが飛散している結果を得た。なお、この
回路基板の電気抵抗は線幅80μmで0.170/mと
低い値である。
Six layers of green sheets with conductor circuits formed in this way were laminated under various conditions: pressure 10-30 MPa, temperature 1f 90-130°, pressurization time 4-15 minutes. These laminated green sheets were heated to a maximum temperature of 950℃ in an N2 atmosphere.
C. for 10 minutes to obtain a ceramic circuit board. No residual carbon was observed around the conductors of these substrates, and the binder was completely scattered. Note that the electrical resistance of this circuit board is as low as 0.170/m at a line width of 80 μm.

アクリル樹脂バインダーを含んだガラス−セラミックペ
ーストと、表に示した銅ペーストを父互に繰り返しスク
リーン印刷法で形成して多層化を行なう方法でセラミッ
ク回路基板を得るとともできる。これは、焼成時にセラ
ミックの収縮が厚さ方間にのみ起こるため、寸法精夏に
優れる。この方法でもガラス−セラミックペーストと銅
ペーストのバインダー組成は同一であり、一体焼成が容
易であることを確認した。
A ceramic circuit board can be obtained by repeatedly forming a glass-ceramic paste containing an acrylic resin binder and a copper paste shown in the table by screen printing to form a multilayer structure. This is because the shrinkage of the ceramic occurs only in the thickness direction during firing, resulting in excellent dimensional precision. It was confirmed that even in this method, the binder composition of the glass-ceramic paste and the copper paste was the same, and that integral firing was easy.

(7)発明の効釆 睨欣後の纒体部にカーボンが残存しない信頼性の高いセ
ラミック回路基板を提供できる。クリーンシートと銅ペ
ーストの一体焼成が容易にでき、セラミンク回路簸板製
造工程を単純化できる。
(7) Effects of the Invention A highly reliable ceramic circuit board in which no carbon remains in the casing after being assembled can be provided. The clean sheet and copper paste can be easily fired together, simplifying the manufacturing process of ceramic circuit elutriation boards.

=22( )−=22( )−

Claims (2)

【特許請求の範囲】[Claims] (1)セラミック回路基板用グリーンシートと導体回路
形成用銅ペーストとの有機バインダーを同一としたこと
を特徴とするセラミック回路基板の製造方法。
(1) A method for manufacturing a ceramic circuit board, characterized in that the green sheet for a ceramic circuit board and the copper paste for forming a conductive circuit use the same organic binder.
(2)上記有機ノ・インダーが不活性ガス中で熱分解飛
散する樹脂であること全特徴とする特許請求の範囲U↓
1項記載のセラミック回路基板の製造方法。
(2) Claims U↓ characterized in that the organic inder is a resin that pyrolyzes and scatters in an inert gas.
A method for manufacturing a ceramic circuit board according to item 1.
JP23370582A 1982-12-29 1982-12-29 Manufacture of ceramic circuit substrate Granted JPS59124149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23370582A JPS59124149A (en) 1982-12-29 1982-12-29 Manufacture of ceramic circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23370582A JPS59124149A (en) 1982-12-29 1982-12-29 Manufacture of ceramic circuit substrate

Publications (2)

Publication Number Publication Date
JPS59124149A true JPS59124149A (en) 1984-07-18
JPH035075B2 JPH035075B2 (en) 1991-01-24

Family

ID=16959251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23370582A Granted JPS59124149A (en) 1982-12-29 1982-12-29 Manufacture of ceramic circuit substrate

Country Status (1)

Country Link
JP (1) JPS59124149A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60153193A (en) * 1984-01-23 1985-08-12 富士通株式会社 Conductive paste for ceramic circuit board
JPH01179407A (en) * 1988-01-07 1989-07-17 Murata Mfg Co Ltd Method of lamination for ceramic raw sheet
JPH01212419A (en) * 1988-02-19 1989-08-25 Murata Mfg Co Ltd Manufacture of ceramic laminate
JPH05213679A (en) * 1991-10-18 1993-08-24 Internatl Business Mach Corp <Ibm> Interface area between metal and ceramics in metal/ceramic substrate and formation method thereof
JPH05221760A (en) * 1992-02-04 1993-08-31 Shinko Electric Ind Co Ltd Production of metal paste for forming circuit and ceramic circuit board
WO2012105068A1 (en) * 2011-02-04 2012-08-09 三菱電機株式会社 Pattern-forming method and solar cell manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396692A (en) * 1977-02-03 1978-08-24 Dainippon Printing Co Ltd Method of making electrode plate
JPS55107295A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Method of fabricating ceramic circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396692A (en) * 1977-02-03 1978-08-24 Dainippon Printing Co Ltd Method of making electrode plate
JPS55107295A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Method of fabricating ceramic circuit board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60153193A (en) * 1984-01-23 1985-08-12 富士通株式会社 Conductive paste for ceramic circuit board
JPH0322717B2 (en) * 1984-01-23 1991-03-27 Fujitsu Ltd
JPH01179407A (en) * 1988-01-07 1989-07-17 Murata Mfg Co Ltd Method of lamination for ceramic raw sheet
JPH0611018B2 (en) * 1988-01-07 1994-02-09 株式会社村田製作所 How to stack ceramic green sheets
JPH01212419A (en) * 1988-02-19 1989-08-25 Murata Mfg Co Ltd Manufacture of ceramic laminate
JPH065656B2 (en) * 1988-02-19 1994-01-19 株式会社村田製作所 Method for manufacturing ceramic laminate
JPH05213679A (en) * 1991-10-18 1993-08-24 Internatl Business Mach Corp <Ibm> Interface area between metal and ceramics in metal/ceramic substrate and formation method thereof
JPH05221760A (en) * 1992-02-04 1993-08-31 Shinko Electric Ind Co Ltd Production of metal paste for forming circuit and ceramic circuit board
WO2012105068A1 (en) * 2011-02-04 2012-08-09 三菱電機株式会社 Pattern-forming method and solar cell manufacturing method

Also Published As

Publication number Publication date
JPH035075B2 (en) 1991-01-24

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