JPS5912368A - Evaluation of humidity resistance for hybrid integrated circuit package - Google Patents

Abstract

PURPOSE:To evaluate the humidity resistance of a package by measuring an DC amplification factor of a transistor chip housed in a hybrid integrated circuit package. CONSTITUTION:A transistor chip 2 is carried at an appropriate place on a pattern formed on a ceramic substrate 1 and a wiring 3 is done. Then, a packaging for evaluation is conducted with a molding resin 4. Thereafter, a module thus obtained is left alone in a constant humidity chamber of an appropriate atmosphere and taken out at an fixed time interval to measure hFE characteristic. Decision on the evaluation is done covering an actually used package and a package to be evaluated simultaneously by a relative comparison or on a different environmental condition. The acceptance or rejection is determined depending on the acceleration rate.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for evaluating the moisture resistance of a resin molded hybrid circuit, and particularly relates to a method for evaluating the moisture resistance of a resin molded hybrid circuit. This invention relates to a moisture resistance evaluation method θ that can be easily implemented using the present invention.

(2) Background of the technology Hybrid integrated circuits are made by forming passive elements such as resistors and capacitors on an alumina board, then mounting active elements such as transistor elements, and connecting these elements to create an excavated circuit,
It consists of all functional circuits such as digital/analog converters, and the surrounding area is generally molded with resin.

In such hybrid integrated circuit packages, external moisture enters the molded portion or the joints with the substrate and terminals at the speed of sound, and the moisture releases ions contained in the molding material, which can also cause It affects internal elements (especially active elements) and deteriorates their characteristics.

Therefore, in order to design the humidity resistance of a hybrid integrated circuit package, it is essential to measure the humidity inside the completed hybrid integrated circuit package from the outside.

(3) Conventional technology and problems Conventionally, as a method for evaluating the moisture resistance of hybrid integrated circuits, a moisture-sensitive element f
L: There are convenient methods and methods that use custom-made parameter variations of the hybrid product circuit itself, but in the former method, it is possible to eliminate moisture entering through the package and ions contained in the package material. It is inappropriate to evaluate the overall impact.

Furthermore, a measurement circuit using a humidity sensing element is generally a multi-layer circuit.

In later studies, normally, even if the characteristics of each element 11/j vary, it does not appear externally as a comprehensive custom order, and the circuit margin is designed to be large due to the compensation circuit gold film, etc. It is not possible to properly measure the moisture that has entered.

(4) Object of the Invention The object of the present invention is to overcome the above-mentioned drawbacks of the conventional method and to provide a relatively simple and sensitive method for evaluating the moisture resistance of a hybrid integrated circuit having a minute volume.

(5) @ Akira's configuration The purpose of the present invention is to house a transistor chip in a hybrid integrated circuit package, and measure the direct current amplification rate (hyz) of the trans/meta to improve the moisture resistance of the package. This is achieved by a method for evaluating the moisture resistance of a hybrid integrated circuit package, which is based on the concept of 11'1 IIT.

(6) Embodiments of the Invention The present invention utilizes the fact that the hFE of a transistor changes due to the influence of moisture and the release of ions contained in the package material due to moisture. It is something to do.

Figure 1 shows an example of the relationship between changes in hFK of transistors in a hybrid integrated circuit package and time under certain humidification conditions. It shows. 1st
As can be seen from the figure, in the case of package structure AXB, the hFI of the transistor changes depending on the influence of moisture.

Next, examples of the present invention will be described below.

1. As shown in FIG. 3, two transistor chips are mounted at appropriate locations on the pattern formed on the ceramic substrate 1, and wiring 3 is performed.

Next, as shown in FIG. 3, packaging to be evaluated is performed using mold resin 4.

In addition, the wiring 3e and the mozzie are placed at an appropriate position so that hFm measurement can be made from the lead wire 5 in the outdoor area.

2. Next, the resulting module is placed in a constant humidity tank with a suitable zero atmosphere, and is taken out at regular intervals to measure the custom-made hrx.

& Evaluation can be made by applying the test to a package with a proven track record and the packaging material to be evaluated, and making a relative comparison, or by conducting the test simultaneously under different favorable conditions, and determining pass/fail based on the acceleration rate. do.

ζ When conducting the evaluation, it is desirable to use all chips from the same manufacturing unit (manufacturer, type, manufacturing lot) in order to eliminate factors related to the moisture resistance of the chip itself.

Furthermore, in order to increase the measurement sensitivity of hFl change sensitivity, if two or more transistors are connected in series as shown in Figure 4, the change in hFPl can be calculated using the following formula. Cannot measure with good sensitivity.

However, LIB = base turtle style, IC = collector turtle style △hyB
:Decrease/removal of hyz n = If the number of stages of vertical connection is greater than 3 terminal leads should be pulled out for hFg measurement of the transistor chip, but if the number of terminals is small, connect as shown in Figure 5. It is also possible to take measurements by pulling it out to the outside using two terminals.

(7) As described in detail, the moisture resistance evaluation method of the present invention allows the evaluation of the moisture resistance of hybrid integrated circuits to be performed relatively easily and with high sensitivity. In general, the hyl of a transistor chip
! Since the decrease in water does not recover even after drying, humidification tests were conducted.
Is it due to the environmental conditions (emission temperature, time) before the measurement? In addition, transistor chips are relatively easy to obtain, are small in size, are inexpensive, and can be easily measured in small packages.

[Brief explanation of the drawing]

Figure 1 is an example graph showing changes in hFiffi of a transistor in a hybrid integrated circuit package under constant humidification conditions, Figures 2 and 3 are detailed illustrations of the present invention, and Figures 4 and 5 are measurements. Connection diagram 1 of the transistor for use is shown. In the figure, 1 is a substrate, 2 is a transistor chip, 3 is a bonding wire, 4 is a mold lead, and 5 is a lead wire. Figure 1-〉Time Figure 4 Figure 5

Claims (1)

[Claims] By housing a transistor chip in a hybrid integrated circuit packaging material and measuring the direct current strength θ1t, increase rate (hy expletive) of the transistor, the overall moisture resistance of the package can be evaluated as a % characteristic. Moisture resistance evaluation method for hybrid integrated circuit packages.