JPH025538Y2 - - Google Patents

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Publication number
JPH025538Y2
JPH025538Y2 JP1984118664U JP11866484U JPH025538Y2 JP H025538 Y2 JPH025538 Y2 JP H025538Y2 JP 1984118664 U JP1984118664 U JP 1984118664U JP 11866484 U JP11866484 U JP 11866484U JP H025538 Y2 JPH025538 Y2 JP H025538Y2
Authority
JP
Japan
Prior art keywords
circuit
bonding pad
elements
thin metal
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1984118664U
Other languages
Japanese (ja)
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JPS6134751U (en
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Priority to JP1984118664U priority Critical patent/JPS6134751U/en
Publication of JPS6134751U publication Critical patent/JPS6134751U/en
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Publication of JPH025538Y2 publication Critical patent/JPH025538Y2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 産業上の利用分野 本考案は基板内で複数の回路素子にて回路を構
成した半導体装置に関する。[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a semiconductor device in which a circuit is constructed of a plurality of circuit elements within a substrate.

従来の技術 モノリシツク半導体集積回路素子は半導体基板
内に半導体素子を含むコンデンサ、抵抗等の回路
素子を形成し、各回路素子を配線して回路を構成
すると共に回路の要部を基板上のボンデイングパ
ツドに接続したもので、この素子のボンデイング
パツドが外部電極に接続されて用いられる。Conventional technology A monolithic semiconductor integrated circuit device consists of forming circuit elements such as capacitors and resistors containing semiconductor elements in a semiconductor substrate, wiring each circuit element to form a circuit, and attaching the main parts of the circuit to bonding pads on the substrate. The bonding pad of this element is connected to an external electrode.

ところで半導体集積回路素子は回路素子数が多
く、特性のばらつきを最小に抑える考慮がなされ
ている。例えば抵抗素子やコンデンサ素子は複数
個並列接続しておいて、各素子間の電気的特性を
測定しつつトリミングして所定の特性に近似させ
るようにしている。 Incidentally, semiconductor integrated circuit devices have a large number of circuit elements, and consideration has been given to minimizing variations in characteristics. For example, a plurality of resistor elements and capacitor elements are connected in parallel, and the electrical characteristics between each element are measured and trimmed to approximate predetermined characteristics.

このトリミング作業の一例を第３図から説明す
る。１は半導体集積回路素子で、基板２上に半導
体素子（図示せず）を含む回路素子（図示例では
抵抗素子）３ａ，３ｂ，３ｃ，３ｄ，３ｅ，３ｆ
を形成し、回路の要部をボンデイングパツド４
ａ，４ｂ，４ｃ……に接続したものである。図示
例では抵抗素子３ａの一端はボンデイングパツド
４ａに、他端は並列接続された抵抗素子３ｂ，３
ｃ，３ｄの一端に接続され各抵抗素子３ｂ，３
ｃ，３ｄの他端はボンデイングパツド４ｂに接続
されている。 An example of this trimming work will be explained with reference to FIG. Reference numeral 1 denotes a semiconductor integrated circuit element, which includes circuit elements (resistance elements in the illustrated example) 3a, 3b, 3c, 3d, 3e, 3f that include a semiconductor element (not shown) on a substrate 2.
bonding pad 4 to form the main part of the circuit.
a, 4b, 4c... In the illustrated example, one end of the resistance element 3a is connected to the bonding pad 4a, and the other end is connected to the resistance elements 3b, 3 connected in parallel.
Each resistive element 3b, 3 is connected to one end of c, 3d.
The other ends of pads c and 3d are connected to bonding pad 4b.

ここで直並列接続された抵抗素子３ａ〜３ｄの
抵抗値が特性に影響を及ぼす場合にはボンデイン
グパツド４ａ，４ｂ間の抵抗値等を測定しつつレ
ーザ光等で並列接続された抵抗素子３ｃ，３ｄを
切断して所定の抵抗値に合せるトリミングが行わ
れる。 If the resistance values of the resistive elements 3a to 3d connected in series and parallel have an influence on the characteristics, the resistive elements 3c connected in parallel are measured using a laser beam or the like while measuring the resistance values between the bonding pads 4a and 4b. , 3d are trimmed to match a predetermined resistance value.

この場合、抵抗３ａ〜３ｄが他の回路素子から
独立していることはなく、例えば図示点線で示す
抵抗素子３ｅ，３ｆ等により閉回路が形成される
ことがある。このとき抵抗素子３ｅ，３ｆの抵抗
値が直並列回路３ａ〜３ｄの抵抗値より小さい場
合や非直線性の素子では測定の誤差が大きく、正
確なトリミングが困難であるという問題があつ
た。 In this case, the resistors 3a to 3d are not independent from other circuit elements, and a closed circuit may be formed, for example, by resistive elements 3e, 3f, etc. indicated by dotted lines in the figure. At this time, when the resistance values of the resistance elements 3e and 3f are smaller than the resistance values of the series-parallel circuits 3a to 3d, or when non-linear elements are used, there is a problem that measurement errors are large and accurate trimming is difficult.

そこで、このような場合には直並列回路３ａ〜
３ｄに対して大きな影響を及ぼす他の回路素子と
の接続部分で回路を切断し、他の回路素子を例え
ば第４図に示すようにボンデイングパツド４b′に
接続して、トリミング後、金属細線５ａ，５ｂ，
５ｃを介して外部電極（外部リード）６ａ，６
ｂ，……に接続する際に、ボンデイングパツド４
ｂ，４ｃをそれぞれ金属細線５ｂ，５ｃを介して
１つの外部電極６ｂに接続することが行われてい
る。 Therefore, in such a case, the series/parallel circuits 3a~
The circuit is cut at the connection point with another circuit element that has a large effect on the 3d, and the other circuit element is connected to the bonding pad 4b' as shown in FIG. 4, and after trimming, the thin metal wire is 5a, 5b,
External electrodes (external leads) 6a, 6 via 5c
When connecting to b,..., bonding pad 4
b, 4c are connected to one external electrode 6b via thin metal wires 5b, 5c, respectively.

考案が解決しようとする問題点 しかしながら、この方法では金属細線の使用量
が多いため、高価な金線を用いる場合には材料費
が多くかかるという問題があつた。Problems to be Solved by the Invention However, since this method uses a large amount of thin metal wire, there was a problem in that the material cost would be high if expensive gold wire was used.

またボンデイングの時間も長くなる欠点があつ
た。 Another drawback was that the bonding time was long.

さらにはトリミングを要する部分が多い半導体
素子ではボンデイングパツドの数も多くなり、ボ
ンデイングパツドの面積が制限されボンデイング
作業が困難となる欠点があつた。 Furthermore, semiconductor devices that require many parts to be trimmed also have a large number of bonding pads, which limits the area of the bonding pads and makes bonding work difficult.

問題点を解決するための手段 本考案は上記問題点に鑑み提案されたもので、
基板内で少くとも１つの閉回路を構成する複数の
回路素子の接続点にボンデイングパツドを設け、
このボンデイングパツドと外部電極とを金属細線
にて電気的に接続したものにおいて、上記ボンデ
イングパツドは各回路素子に電気的に接続され互
に分離された小パツドに分割され、金属細線の一
端部乃至中間部を各小パツドに接続して前記閉回
路を構成することにより、上記欠点や問題点を除
去した半導体集積回路装置を提供する。Means for solving the problems This invention was proposed in view of the above problems.
A bonding pad is provided at the connection point of a plurality of circuit elements constituting at least one closed circuit within the board,
In this bonding pad and an external electrode electrically connected by a thin metal wire, the bonding pad is divided into small pads that are electrically connected to each circuit element and separated from each other. The present invention provides a semiconductor integrated circuit device in which the above-described drawbacks and problems are eliminated by connecting the small pads to the intermediate portions to form the closed circuit.

作 用 本考案による半導体集積回路装置では、トリミ
ングを正確に行うために各回路素子を分離するよ
うに小パツドを用け、このパツドを金属細線の一
端部乃至中間部で接続している。Function: In the semiconductor integrated circuit device according to the present invention, small pads are used to separate each circuit element in order to perform accurate trimming, and the pads are connected at one end or the middle of a thin metal wire.

実施例 以下に、本考案の実施例を第１図から説明す
る。図において７は複数の回路素子８ａ〜８ｆを
半導体基板９内に形成した半導体素子で、基板９
表面の周縁部に沿つてボンデイングパツド１０
ａ，１０ｂ，１０ｃ……が形成されている。回路
素子８ａの一端はボンデイングパツド１０ａに接
続され、他端は並列接続された回路素子８ｂ，８
ｃ，８ｄの一端に接続されている。ボンデイング
パツド１０ｂは２分割されて、一方の小パツド１
０b′に並列回路素子８ｂ，８ｃ，８ｄの他端を接
続して、他の小パツド１０b″を本来並列回路素子
８ｂ，８ｃ，８ｄの他端に接続されるべき回路素
子（図示例では回路素子８ａと閉回路をなす回路
素子）８ｅに接続される。１１は半導体素子７を
マウントする素子マウント部、１２ａ，１２ｂ，
１２ｃ……は一端が素子マウント部１１に近接配
置された複数のリード、１３ａ，１３ｂ，１３ｃ
……は各ボンデイングパツド１０ａ，１０ｂ，…
…と各リード１２ａ，１２ｂ，……とを電気的に
接続する金線等の金属細線を示す。Embodiment An embodiment of the present invention will be described below with reference to FIG. In the figure, 7 is a semiconductor element in which a plurality of circuit elements 8a to 8f are formed in a semiconductor substrate 9.
Bonding pad 10 along the periphery of the surface
a, 10b, 10c... are formed. One end of the circuit element 8a is connected to the bonding pad 10a, and the other end is connected to the circuit elements 8b, 8 connected in parallel.
c, 8d. The bonding pad 10b is divided into two parts, one of which is the small pad 1.
0b' to connect the other ends of the parallel circuit elements 8b, 8c, 8d, and connect the other small pad 10b'' to the circuit element that should originally be connected to the other end of the parallel circuit elements 8b, 8c, 8d (in the illustrated example, the circuit It is connected to the circuit element (8e) forming a closed circuit with the element 8a. Reference numeral 11 denotes an element mount portion for mounting the semiconductor element 7, 12a, 12b,
12c... are a plurality of leads 13a, 13b, 13c with one end disposed close to the element mount section 11.
... are each bonding pad 10a, 10b,...
. . . and each lead 12a, 12b, . . . and a thin metal wire such as a gold wire is shown.

ここで、この半導体素子７はウエハ状態又は各
素子に分離された後に、トリミング作業が行われ
る。このときトリミングされる回路素子と閉回路
を構成する回路素子８ｅは小パツド１０b′，１０
b″によつて分離されているため、ボンデイングパ
ツド１０ａと小パツド１０b′間の電気的特性を測
定し正確なトリミングが可能となる。 Here, after the semiconductor element 7 is in a wafer state or separated into individual elements, a trimming operation is performed. The circuit elements to be trimmed at this time and the circuit elements 8e forming a closed circuit are connected to small pads 10b' and 10.
Since the bonding pad 10a and the small pad 10b' are separated by 10b', it is possible to measure the electrical characteristics between the bonding pad 10a and the small pad 10b' and perform accurate trimming.

このようにしてトリミングされた半導体素子７
は素子マウント部１１にマウントし、各ボンデイ
ングパツド１０ａ，１０ｂ，１０b′，１０b″，１
０ｃ，……とリード１２ａ，１２ｂ，１２ｃ，…
…が金属細線１３ａ，１３ｂ，１３ｃ，……によ
つて電気的に接続されるが、小パツド１０b′，１
０b″とリード１２ｂの接続は第２図に示すよう
に、先ず金属細線１３ｂの一端を小パツド１０
b′にボンデイングし、次に金属細線１３ｂの中間
部を小パツド１０b″にボンデイングして、さらに
他端部をリード１２ｂにボンデイングする。 Semiconductor element 7 trimmed in this way
is mounted on the element mounting part 11, and each bonding pad 10a, 10b, 10b', 10b'', 1
0c, ... and leads 12a, 12b, 12c, ...
... are electrically connected by thin metal wires 13a, 13b, 13c, ..., but small pads 10b', 1
0b'' and the lead 12b, as shown in FIG.
b', then the middle part of the thin metal wire 13b is bonded to the small pad 10b'', and the other end is bonded to the lead 12b.

考案の効果 以上のように本考案によれば、金属細線の使用
量を節約でき、特に高価な金線を用いる場合には
その効果が大である。Effects of the invention As described above, according to the invention, the amount of thin metal wire used can be reduced, and this effect is particularly great when expensive gold wire is used.

またボンデイングに要する時間も短縮でき、さ
らにはボンデイングパツドの数を小さくできるた
め、同一サイズのペレツトでは、ペレツト表面に
余裕ができパツドの面積を広くでき、ボンデイン
グ作業が容易となる。 Furthermore, the time required for bonding can be shortened, and the number of bonding pads can be reduced, so that with pellets of the same size, there is more space on the pellet surface and the area of the pads can be increased, making the bonding work easier.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案を示す要部平面図、第２図は第
１図部分拡大図、第３図は半導体集積回路素子の
平面図、第４図は従来の半導体装置の要部平面図
である。 ８ａ〜８ｆ……回路素子、９……基板、１０
ａ，１０ｂ，１０b′，１０b″，１０ｃ……ボンデ
イングパツド、１０b′，１０b″……小パツド、１
２ａ，１２ｂ，１２ｃ……リード（外部電極）、
１３ａ，１３ｂ，１３ｃ……金属細線。 Fig. 1 is a plan view of the main part showing the present invention, Fig. 2 is an enlarged view of the part of Fig. 1, Fig. 3 is a plan view of a semiconductor integrated circuit element, and Fig. 4 is a plan view of the main part of a conventional semiconductor device. be. 8a to 8f...Circuit element, 9...Substrate, 10
a, 10b, 10b', 10b'', 10c...Bonding pad, 10b', 10b''...Small pad, 1
2a, 12b, 12c...leads (external electrodes),
13a, 13b, 13c... thin metal wires.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板内で少くとも１つの閉回路を構成する複数
の回路素子の接続点にボンデイングパツドを設
け、このボンデイングパツドと外部電極とを金属
細線にて電気的に接続したものにおいて、上記ボ
ンデイングパツドは各回路素子に電気的に接続さ
れかつ互に分離された小パツドに分割され、金属
細線の一端部乃至中間部を各小パツドに接続して
前記閉回路を構成したことを特徴とする半導体集
積回路装置。 A bonding pad is provided at the connection point of a plurality of circuit elements constituting at least one closed circuit within the board, and the bonding pad and an external electrode are electrically connected by a thin metal wire, wherein the bonding pad is The closed circuit is characterized in that the wire is divided into small pads that are electrically connected to each circuit element and separated from each other, and one end or middle portion of the thin metal wire is connected to each of the small pads to form the closed circuit. Semiconductor integrated circuit device.
JP1984118664U 1984-07-31 1984-07-31 Semiconductor integrated circuit device Granted JPS6134751U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984118664U JPS6134751U (en) 1984-07-31 1984-07-31 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984118664U JPS6134751U (en) 1984-07-31 1984-07-31 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6134751U JPS6134751U (en) 1986-03-03
JPH025538Y2 true JPH025538Y2 (en) 1990-02-09

Family

ID=30677544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984118664U Granted JPS6134751U (en) 1984-07-31 1984-07-31 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6134751U (en)

Also Published As

Publication number Publication date
JPS6134751U (en) 1986-03-03

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