JPS60198850A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS60198850A
JPS60198850A JP5560684A JP5560684A JPS60198850A JP S60198850 A JPS60198850 A JP S60198850A JP 5560684 A JP5560684 A JP 5560684A JP 5560684 A JP5560684 A JP 5560684A JP S60198850 A JPS60198850 A JP S60198850A
Authority
JP
Japan
Prior art keywords
lead frame
lead
semiconductor device
leads
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5560684A
Other languages
Japanese (ja)
Inventor
Susumu Nakamori
中森　晋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5560684A priority Critical patent/JPS60198850A/en
Publication of JPS60198850A publication Critical patent/JPS60198850A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

PURPOSE:To check destruction of a semiconductor device to be generated by coming in contact of a material carrying static electricity with leads by a method wherein electric elements are provided on a tape carrier system lead frame. CONSTITUTION:Electric elements such as capacitor elements or resistor elements, etc. are provided between the parts 3c of leads 3 and a lead part 3d continuously connected to a lead on another side on a tape type insulating film 1. By using such a lead frame, even when a material carrying static electricity comes in contact with the lead frame in the manufacturing process to make the lead frame to be charged, because a current flows in the capacitors or the resistors having low impedances, no current flows in a semiconductor device. Accordingly, destruction of the semiconductor device can be checked.

Description

【発明の詳細な説明】 （技術分野） 本発明は、テープ・キャリア方式によって製造される半
導体回路に用いるリード・フレームに関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a lead frame used in a semiconductor circuit manufactured by a tape carrier method.

（従来の技術） 従来のテープ・キャリア方式用のり一ド轡フレームは第
１図のように均質のテープ状のボリイシＦ等の絶縁性フ
ィルム１の両側に等間隔のスズロケットホール２を開け
、中央部にデバイスホール４を開けてリード３を金属腐
蝕法および電気金贋金法によって連続的に形成する。リ
ード・フレームのり一ド３の半導体素子の搭載側は、デ
バイスホール４に突き出したものとなっておシ、リード
３の先端部３ａにおいて半導体素子５の電極に熱圧着さ
れリード３の他端３Ｃに探針を接触させて半導体素子の
電気的な特性を測定することができる。(Prior art) As shown in Fig. 1, the conventional glued frame for the tape carrier method has tin rocket holes 2 made at equal intervals on both sides of a homogeneous tape-shaped insulating film 1 such as Bolish F. A device hole 4 is opened in the center, and leads 3 are continuously formed by metal etching and electroplating. The side of the lead frame glue 3 on which the semiconductor element is mounted protrudes into the device hole 4, and the tip 3a of the lead 3 is thermocompressed to the electrode of the semiconductor element 5, and the other end 3C of the lead 3 is attached. The electrical characteristics of a semiconductor element can be measured by bringing a probe into contact with the semiconductor element.

（発明の目的） しかし、この形状のり一ド・フレームでは、製造工程に
おいて、静電気を帯びた物質が、リード３に接触するこ
とによって、このリード３を通して、容易に半導体装置
５に、電気が直接に加わシ半導体装置を破壊して、歩留
を極端に低下させていた。(Object of the Invention) However, in the glued frame of this shape, during the manufacturing process, a substance charged with static electricity comes into contact with the leads 3, and electricity can easily be directly applied to the semiconductor device 5 through the leads 3. In addition to this, semiconductor devices were destroyed and yields were extremely reduced.

（発明の目的および構成） 本発明は、従来のテープキャリア方式のリードフレーム
の上記の欠点を解消することを目的とし、リードフレー
ム上に容量、抵抗等の素子を具備し　。(Object and Structure of the Invention) The present invention aims to eliminate the above-mentioned drawbacks of the conventional tape carrier type lead frame, and includes elements such as capacitors and resistors on the lead frame.

たことを特徴とする。It is characterized by:

（作　用） この方式のり一ド・フレームを用いることによって、製
造工程において静電気を帯びた物質が、リードフレーム
に接触し、リードフレームが帯電したとしても宵、流は
、インピーダンスの低い容量ないしは抵抗を流れること
によって、半導体装量５に電流は流れず、半導体装置５
を破壊することなく歩留を一段と向上することができる
。ユ（実施例） 本発明の実施例によるテープ・キャリア方式のリード・
フレームは、第２図のようにテープ状のポリイミド等の
絶縁性フィルム１上に、リード３の３９と一方のリード
と連続的につながっているリード部３ｄとの間に容量素
子又は抵抗索子等の電気素子６を設けたものである。(Function) By using this type of glued frame, even if a substance charged with static electricity comes into contact with the lead frame during the manufacturing process and the lead frame is charged, the flow will be reduced to capacitance or resistance with low impedance. As a result, no current flows through the semiconductor device 5, and the semiconductor device 5
The yield can be further improved without destroying the material. (Embodiment) A tape carrier type lead/reader according to an embodiment of the present invention.
As shown in FIG. 2, the frame is made of a tape-shaped insulating film 1 made of polyimide or the like, and has a capacitive element or a resistive cable connected between 39 of the leads 3 and a lead part 3d that is continuously connected to one lead. It is equipped with an electric element 6 such as the following.

上記の実施例は、本発明の好適な膨様を示しているが、
穐々の変形もしくけ変更が可能である。Although the above examples illustrate preferred inflation patterns of the present invention,
It is possible to change the deformation of Aki.

たとえばリード部の３ｄの形状およびその接続個所、あ
るいは電気素子の種類およびその接続個所の変更が可能
である。For example, it is possible to change the shape of the lead portion 3d and its connection points, or the type of electric element and its connection points.

【図面の簡単な説明】 第１図は、従来のチップ・キャリア方式のリードフレー
ムの平面図であり、第２図は、本発明の実施例によるチ
ップ・キャリア方式のリード嚇フレームの平面図である
。 尚、図に、おいて、１・・・・・・テープ、２・川・・
スプロケットΦホール、３・・・・・・リード、４・・
・・・・デバイス・ホール、５・・・・・・半導体素子
、６・・・・・・本発明に関れる容量素子ないしは抵抗
素子である。 ！ 第１図 第　Ｚ　旧[Brief Description of the Drawings] Fig. 1 is a plan view of a conventional chip carrier type lead frame, and Fig. 2 is a plan view of a chip carrier type lead threat frame according to an embodiment of the present invention. be. In addition, in the figure, 1... tape, 2... river...
Sprocket Φ hole, 3...Lead, 4...
. . . Device hole, 5 . . . Semiconductor element, 6 . . . Capacitive element or resistive element related to the present invention. ! Figure 1 No. Z Old

Claims (1)

【特許請求の範囲】[Claims] 密層した電極用リードパターンを具備長尺状の絶縁性フ
ィルムにおいて、該フィルム上に電気素子が設けられて
いることを特徴とするり一ド・フレーム。1. A linear frame, characterized in that an elongated insulating film is provided with a densely layered electrode lead pattern, and an electric element is provided on the film.
JP5560684A 1984-03-23 1984-03-23 Lead frame Pending JPS60198850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5560684A JPS60198850A (en) 1984-03-23 1984-03-23 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5560684A JPS60198850A (en) 1984-03-23 1984-03-23 Lead frame

Publications (1)

Publication Number Publication Date
JPS60198850A true JPS60198850A (en) 1985-10-08

Family

ID=13003425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5560684A Pending JPS60198850A (en) 1984-03-23 1984-03-23 Lead frame

Country Status (1)

Country Link
JP (1) JPS60198850A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190345U (en) * 1986-05-26 1987-12-03
US4949155A (en) * 1987-07-14 1990-08-14 Sharp Kabushiki Kaisha Tape carrier for semiconductor chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190345U (en) * 1986-05-26 1987-12-03
US4949155A (en) * 1987-07-14 1990-08-14 Sharp Kabushiki Kaisha Tape carrier for semiconductor chips

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