JPH0414934Y2 - - Google Patents
Info
- Publication number
- JPH0414934Y2 JPH0414934Y2 JP6121687U JP6121687U JPH0414934Y2 JP H0414934 Y2 JPH0414934 Y2 JP H0414934Y2 JP 6121687 U JP6121687 U JP 6121687U JP 6121687 U JP6121687 U JP 6121687U JP H0414934 Y2 JPH0414934 Y2 JP H0414934Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit board
- metal plate
- resin
- metallized pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007789 sealing Methods 0.000 claims description 15
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 9
- 239000000523 sample Substances 0.000 description 4
- 238000011990 functional testing Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は回路基板に集積回路素子を搭載し、集
積回路素子を封止枠で囲い、枠の内側を樹脂で封
止する集積回路装置の構造に関する。[Detailed description of the invention] [Field of industrial application] The present invention is an integrated circuit device in which an integrated circuit element is mounted on a circuit board, the integrated circuit element is surrounded by a sealing frame, and the inside of the frame is sealed with resin. Regarding structure.
従来、この種の集積回路装置は、集積回路素子
上で生産工程上の機能試験でのみ使用する端子
（以降テスト端子と記す）とそれ以外の実使用上
必要な端子（以降ノーマル端子と記す）の両方共
回路基板にボンデイングし、回路基板上にメタラ
イズパターンを設けていた。
Conventionally, this type of integrated circuit device has two terminals on the integrated circuit element that are used only for functional tests during the production process (hereinafter referred to as test terminals) and other terminals that are necessary for actual use (hereinafter referred to as normal terminals). Both were bonded to a circuit board, and a metallized pattern was provided on the circuit board.
機能試験時は、メタライズパターンに測定治具
のプローブを接触させる。 During a functional test, the probe of the measurement jig is brought into contact with the metallized pattern.
上述した従来の集積回路装置では、回路基板上
に設けるテスト端子用メタライズパターンが高密
度実装の防げとなつていた。
In the conventional integrated circuit device described above, the metallized pattern for test terminals provided on the circuit board prevents high-density mounting.
本考案の集積回路装置は、回路基板に集積回路
素子を搭載し、集積回路素子を封止枠で囲い、枠
の内側を樹脂で封止する集積回路装置において、
金属板が封止枠の上面の一部分を覆うように固定
されており、金属板に集積回路素子上のテスト端
子をボンデイングする構造を有している。
The integrated circuit device of the present invention is an integrated circuit device in which an integrated circuit element is mounted on a circuit board, the integrated circuit element is surrounded by a sealing frame, and the inside of the frame is sealed with resin.
A metal plate is fixed so as to cover a portion of the upper surface of the sealing frame, and has a structure in which test terminals on an integrated circuit element are bonded to the metal plate.
次に本考案について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図及び第２図は本考案の実施例の樹脂で封
止を行う前の斜視図及び断面図であり、第３図及
び第４図は従来の実施例の樹脂で封止を行う前の
斜視図及び断面図である。 1 and 2 are a perspective view and a sectional view before sealing with the resin of the embodiment of the present invention, and FIGS. 3 and 4 are before sealing with the resin of the conventional embodiment. FIG. 2 is a perspective view and a cross-sectional view.
第１図の本考案の実施例において回路基板１に
集積回路素子２を搭載し、ノーマル端子３ａはボ
ンデイングワイヤー４でボンデイングされ、テス
ト端子３ｂは、封止枠５を回路基板１に搭載した
後、封止枠５の上面の一部分を覆うように固定さ
れた金属板６にボンデイングされ、封止枠５の内
側は樹脂１０で封止される。金属板６は回路基板
１にレジスト７がある為、ノーマル端子のメタラ
イズパターン８ａとは電気的に絶縁されている。 In the embodiment of the present invention shown in FIG. 1, an integrated circuit element 2 is mounted on a circuit board 1, a normal terminal 3a is bonded with a bonding wire 4, and a test terminal 3b is connected after a sealing frame 5 is mounted on the circuit board 1. , is bonded to a fixed metal plate 6 so as to cover a part of the upper surface of the sealing frame 5, and the inside of the sealing frame 5 is sealed with a resin 10. Since the metal plate 6 has the resist 7 on the circuit board 1, it is electrically insulated from the metallized pattern 8a of the normal terminal.
機能試験時は、測定治具のプローブ９を金属板
６とノーマル端子のメタライズパターン８ａに接
触させる。 During a functional test, the probe 9 of the measuring jig is brought into contact with the metal plate 6 and the metallized pattern 8a of the normal terminal.
しかし第３図の従来の実施例では回路基板１に
集積回路素子２を搭載し、ノーマル端子又はテス
ト端子３ｃはボンデイングワイヤー４でボンデイ
ングされ、封止枠５を回路基板１に搭載し、封止
枠５の内側は樹脂１０で封止される。 However, in the conventional embodiment shown in FIG. 3, an integrated circuit element 2 is mounted on a circuit board 1, a normal terminal or a test terminal 3c is bonded with a bonding wire 4, a sealing frame 5 is mounted on the circuit board 1, and the sealing frame 5 is mounted on the circuit board 1. The inside of the frame 5 is sealed with resin 10.
機能試験時は、測定治具のプローブ９をノーマ
ル端子のメタライズパターン８ａとテスト端子の
メタライズパターン８ｂに接解させる。 During the function test, the probe 9 of the measuring jig is brought into contact with the metallized pattern 8a of the normal terminal and the metallized pattern 8b of the test terminal.
又、従来の実施例では回路基板１上にノーマル
端子のメタライズパターン８ａとテスト端子のメ
タライズパターン８ｂがあるが、本考案の実施例
ではノーマル端子のメタライズパターン８ａしか
ない。 Further, in the conventional embodiment, there are a metallized pattern 8a for normal terminals and a metallized pattern 8b for test terminals on the circuit board 1, but in the embodiment of the present invention, there is only the metallized pattern 8a for normal terminals.
以上説明したように本考案によれば、回路基板
上にテスト端子のメタライズパターンが要らなく
る為、高密度実装に有利となる。
As explained above, according to the present invention, there is no need for a metallized pattern of test terminals on the circuit board, which is advantageous for high-density mounting.
第１図及び第２図は本考案の実施例の樹脂で封
止を行う前の斜視図及び断面図であり、第３図及
び第４図は従来の実施例の樹脂で封止を行う前の
斜視図及び断面図である。
１……回路基板、２……集積回路素子、３ａ…
…ノーマル端子、３ｂ……テスト端子、３ｃ……
ノーマル端子又はテスト端子、４……ボンデイン
グワイヤー、５……封止枠、６……金属板、７…
…レジスト、８ａ……ノーマル端子のメタライズ
パターン、８ｂ……テスト端子のメタライズパタ
ーン、９……測定治具のプローブ、１０……樹
脂。
1 and 2 are a perspective view and a sectional view before sealing with the resin of the embodiment of the present invention, and FIGS. 3 and 4 are before sealing with the resin of the conventional embodiment. FIG. 2 is a perspective view and a cross-sectional view. 1... Circuit board, 2... Integrated circuit element, 3a...
...Normal terminal, 3b...Test terminal, 3c...
Normal terminal or test terminal, 4... bonding wire, 5... sealing frame, 6... metal plate, 7...
...Resist, 8a...Metallized pattern of normal terminal, 8b...Metallized pattern of test terminal, 9...Probe of measurement jig, 10...Resin.
Claims (1)
子を封止枠で用い、枠の内側を樹脂で封止する集
積回路装置において、金属製の薄板（以後、金属
板と記す）が封止枠の上面の一部分を覆うように
固定されており、金属板に集積回路素子上の端子
の一部をボンデイングすることを特徴とする集積
回路装置。 In an integrated circuit device in which an integrated circuit element is mounted on a circuit board, the integrated circuit element is used as a sealing frame, and the inside of the frame is sealed with resin, a thin metal plate (hereinafter referred to as metal plate) is used as the sealing frame. An integrated circuit device, characterized in that the integrated circuit device is fixed so as to cover a portion of the upper surface of the integrated circuit device, and a portion of the terminals on the integrated circuit element are bonded to the metal plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6121687U JPH0414934Y2 (en) | 1987-04-21 | 1987-04-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6121687U JPH0414934Y2 (en) | 1987-04-21 | 1987-04-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63167735U JPS63167735U (en) | 1988-11-01 |
| JPH0414934Y2 true JPH0414934Y2 (en) | 1992-04-03 |
Family
ID=30894345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6121687U Expired JPH0414934Y2 (en) | 1987-04-21 | 1987-04-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0414934Y2 (en) |
-
1987
- 1987-04-21 JP JP6121687U patent/JPH0414934Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63167735U (en) | 1988-11-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0414934Y2 (en) | ||
| JPH039271Y2 (en) | ||
| JPS63157936U (en) | ||
| JPS6116702Y2 (en) | ||
| JPH03129840A (en) | Resin-sealed semiconductor device | |
| JPS6236345Y2 (en) | ||
| JPS57160138A (en) | Lead frame for semiconductor device | |
| JPS6224262Y2 (en) | ||
| JPH0319406A (en) | Surface mount type crystal oscillator | |
| JPH0310570U (en) | ||
| JPS61153344U (en) | ||
| JPS592034U (en) | Sealed limit switch | |
| JPH0450780A (en) | Semiconductor evaluation device | |
| JPS58125880U (en) | Semiconductor device measurement jig | |
| JPS60130518U (en) | Electrical component wiring device in copying machine | |
| JPH0336478U (en) | ||
| JPS63147818U (en) | ||
| JPS61149334U (en) | ||
| JPS5989554U (en) | Semiconductor element mounting structure | |
| JPH0377461U (en) | ||
| JPS59161057A (en) | Semiconductor integrated circuit | |
| JPS6093970U (en) | surface electrometer | |
| JPS62242829A (en) | Load cell with dampproofing structure | |
| JPH0170360U (en) | ||
| JPS59125833U (en) | semiconductor equipment |