JPS59121487A - アツプダウンカウンタ - Google Patents

アツプダウンカウンタ

Info

Publication number
JPS59121487A
JPS59121487A JP23136882A JP23136882A JPS59121487A JP S59121487 A JPS59121487 A JP S59121487A JP 23136882 A JP23136882 A JP 23136882A JP 23136882 A JP23136882 A JP 23136882A JP S59121487 A JPS59121487 A JP S59121487A
Authority
JP
Japan
Prior art keywords
output
clock signal
circuit
level
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23136882A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0149054B2 (enrdf_load_stackoverflow
Inventor
Hiroshi Mizuguchi
博 水口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23136882A priority Critical patent/JPS59121487A/ja
Priority to US06/542,195 priority patent/US4587665A/en
Publication of JPS59121487A publication Critical patent/JPS59121487A/ja
Publication of JPH0149054B2 publication Critical patent/JPH0149054B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
    • H03K23/62—Gating or clocking signals not applied to all stages, i.e. asynchronous counters reversible
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/16—Circuits for carrying over pulses between successive decades
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP23136882A 1982-10-15 1982-12-27 アツプダウンカウンタ Granted JPS59121487A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP23136882A JPS59121487A (ja) 1982-12-27 1982-12-27 アツプダウンカウンタ
US06/542,195 US4587665A (en) 1982-10-15 1983-10-14 Binary counter having buffer and coincidence circuits for the switched bistable stages thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23136882A JPS59121487A (ja) 1982-12-27 1982-12-27 アツプダウンカウンタ

Publications (2)

Publication Number Publication Date
JPS59121487A true JPS59121487A (ja) 1984-07-13
JPH0149054B2 JPH0149054B2 (enrdf_load_stackoverflow) 1989-10-23

Family

ID=16922519

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23136882A Granted JPS59121487A (ja) 1982-10-15 1982-12-27 アツプダウンカウンタ

Country Status (1)

Country Link
JP (1) JPS59121487A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0149054B2 (enrdf_load_stackoverflow) 1989-10-23

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