JPS59117148U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS59117148U JPS59117148U JP982783U JP982783U JPS59117148U JP S59117148 U JPS59117148 U JP S59117148U JP 982783 U JP982783 U JP 982783U JP 982783 U JP982783 U JP 982783U JP S59117148 U JPS59117148 U JP S59117148U
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- layer
- dielectric isolation
- isolation island
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は誘電体分離構造を用いた従来のダイオードの断
面図、第2図は誘電体分離構造を用いた従来の横型の第
1型トランジスタの断面図、第3図は第1型トランジス
タと第2型トランジスタの両方をタテ型トランジスタと
した従来の断面図、第4図は本考案の誘電体分離構造の
ダイオードの断面図、第5図は本考案による誘電体分離
構造の第1型トランジスタの断面図、第6図は本考案の
誘電体分離構造のマルチェミッタトラノジスタの断面図
、第7図は、本考案の誘電体分離構造の第1型トランジ
スタの断面図、第8図は第5図の第1型トランジスタと
同時に設ける。ための第2型トランジスタの断面図、第
9図は本考案の誘電体分離構造の第2型トランジスタの
断面図である。
3・・・第1導電型のDI島、6・・・配線、23・・
−DI島の底面および側面の第2導電型の層、27・・
・DI島の表面の第2導電型の層。
6 ?
l
!to’t ’3− t’tFigure 1 is a cross-sectional view of a conventional diode using a dielectric isolation structure, Figure 2 is a cross-sectional view of a conventional horizontal type 1 transistor using a dielectric isolation structure, and Figure 3 is a cross-sectional view of a conventional lateral type 1 transistor using a dielectric isolation structure. A conventional cross-sectional view in which both of the second-type transistors are vertical transistors, FIG. 4 is a cross-sectional view of a diode with a dielectric isolation structure according to the present invention, and FIG. 5 is a cross-sectional view of a first-type transistor with a dielectric isolation structure according to the present invention. FIG. 6 is a cross-sectional view of a multi-mitter transistor with a dielectric isolation structure according to the present invention, FIG. 7 is a cross-sectional view of a type 1 transistor with a dielectric isolation structure according to the present invention, and FIG. It is provided at the same time as the first type transistor shown in FIG. FIG. 9 is a sectional view of a second type transistor having a dielectric isolation structure according to the present invention. 3... DI island of first conductivity type, 6... Wiring, 23...
- second conductivity type layer on the bottom and side surfaces of the DI island, 27...
- Second conductivity type layer on the surface of the DI island. 6? l! to't '3- t't
Claims (1)
電型の誘電体分離島の底面と側面に第2導電型の層を設
けたことを特徴とする半導体装置。 2 実用新案登録請求の範囲第1項において、第1導電
型の誘電体分離島の表面に第2導電僧の層を設けfこと
を特徴とする半導体装置。 3 実用新案登録請求の範囲第2項において、第1′導
電型の誘電体分離島の表面の第2導電型の層内に第1導
電型の層を設け、前記第1導電型の誘電体分離島の底部
の第2導電型の層の1部あるいは全部を第1導電型の層
とし、同時に前記第1導電型の誘電体分離島と、この誘
電体分離島の底面および側面の第2導電型の層を配線で
短絡したことを特徴とする半導体装置。[Claims for Utility Model Registration] 1. A semiconductor device having a dielectric isolation structure, characterized in that a second conductivity type layer is provided on the bottom and side surfaces of a first conductivity type dielectric isolation island. 2. A semiconductor device according to claim 1, characterized in that a second conductive layer is provided on the surface of the dielectric isolation island of the first conductivity type. 3. In claim 2 of the utility model registration claim, a layer of a first conductivity type is provided within a layer of a second conductivity type on the surface of a dielectric isolation island of a first conductivity type, and the dielectric of the first conductivity type is Part or all of the layer of the second conductivity type at the bottom of the isolation island is a layer of the first conductivity type, and at the same time, the dielectric isolation island of the first conductivity type and the second conductivity type layer on the bottom and side surfaces of the dielectric isolation island are A semiconductor device characterized in that conductive type layers are short-circuited with wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP982783U JPS59117148U (en) | 1983-01-28 | 1983-01-28 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP982783U JPS59117148U (en) | 1983-01-28 | 1983-01-28 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59117148U true JPS59117148U (en) | 1984-08-07 |
JPH0333067Y2 JPH0333067Y2 (en) | 1991-07-12 |
Family
ID=30141274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP982783U Granted JPS59117148U (en) | 1983-01-28 | 1983-01-28 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59117148U (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5147583A (en) * | 1974-10-22 | 1976-04-23 | Sanyo Kako Kk | KOKETSUBOSHIHO |
JPS54159976U (en) * | 1978-04-28 | 1979-11-08 | ||
JPS55115340A (en) * | 1979-02-26 | 1980-09-05 | Hitachi Ltd | Semiconductor device |
JPS55133553A (en) * | 1979-04-03 | 1980-10-17 | Hitachi Ltd | Semiconductor integrated device |
-
1983
- 1983-01-28 JP JP982783U patent/JPS59117148U/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5147583A (en) * | 1974-10-22 | 1976-04-23 | Sanyo Kako Kk | KOKETSUBOSHIHO |
JPS54159976U (en) * | 1978-04-28 | 1979-11-08 | ||
JPS55115340A (en) * | 1979-02-26 | 1980-09-05 | Hitachi Ltd | Semiconductor device |
JPS55133553A (en) * | 1979-04-03 | 1980-10-17 | Hitachi Ltd | Semiconductor integrated device |
Also Published As
Publication number | Publication date |
---|---|
JPH0333067Y2 (en) | 1991-07-12 |
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