JPS60130652U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS60130652U
JPS60130652U JP1827384U JP1827384U JPS60130652U JP S60130652 U JPS60130652 U JP S60130652U JP 1827384 U JP1827384 U JP 1827384U JP 1827384 U JP1827384 U JP 1827384U JP S60130652 U JPS60130652 U JP S60130652U
Authority
JP
Japan
Prior art keywords
case
electrodes
semiconductor equipment
mini
mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1827384U
Other languages
Japanese (ja)
Inventor
山脇 達司
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1827384U priority Critical patent/JPS60130652U/en
Publication of JPS60130652U publication Critical patent/JPS60130652U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a及びbに従来構造によるミニモールドトランジ
スタの平面図、立面図を示す。第2図a及びbに本考案
によるミニモールドトランジスタの平面図、立面図を示
す。第3図、第4図、第5図には、本考案によるミニモ
ールドトランジスタの複数個一体化した実装方法の例を
示す。 1・・・・・・電極、2・・・・・・ケース、3・・・
・・・ケースと一体化して形成した突起、を示す。
FIGS. 1a and 1b show a plan view and an elevation view of a mini-mold transistor having a conventional structure. FIGS. 2a and 2b show a plan view and an elevation view of a mini-mold transistor according to the present invention. FIGS. 3, 4, and 5 show an example of a mounting method for integrating a plurality of mini-mold transistors according to the present invention. 1...electrode, 2...case, 3...
... indicates a protrusion formed integrally with the case.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ミニモールドトランジスタにおいて、全ての外部電極を
該トランジスタケースの同一側面に形成し、これと向い
あう側面には電極を形成せず、該ケースと一体化してモ
ールド形成した突起を設けた構造をとることにより、電
極の存在しない該ケース側面同志を互いに接着して、複
数のミニモールドトランジスタを一体化したことを特徴
とした半導体装置。
In a mini-mold transistor, all external electrodes are formed on the same side of the transistor case, no electrodes are formed on the opposite side, and a structure is provided in which a protrusion is molded integrally with the case. A semiconductor device characterized in that a plurality of mini-mold transistors are integrated by bonding side surfaces of the case where no electrodes are present to each other.
JP1827384U 1984-02-10 1984-02-10 semiconductor equipment Pending JPS60130652U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1827384U JPS60130652U (en) 1984-02-10 1984-02-10 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1827384U JPS60130652U (en) 1984-02-10 1984-02-10 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS60130652U true JPS60130652U (en) 1985-09-02

Family

ID=30506752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1827384U Pending JPS60130652U (en) 1984-02-10 1984-02-10 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS60130652U (en)

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