JPS59115543A - Forming method for coating film - Google Patents
Forming method for coating filmInfo
- Publication number
- JPS59115543A JPS59115543A JP22816682A JP22816682A JPS59115543A JP S59115543 A JPS59115543 A JP S59115543A JP 22816682 A JP22816682 A JP 22816682A JP 22816682 A JP22816682 A JP 22816682A JP S59115543 A JPS59115543 A JP S59115543A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thickness
- layer
- wiring layer
- approx
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
(al 発明の技術分野
本発明は被着膜の形成方法にかかり、特に凹凸のある基
板面に平坦な被着膜を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method of forming a deposited film, and more particularly to a method of forming a flat deposited film on an uneven substrate surface.
(b) 従来技術と問題点
例えば、半導体集積回路(IC)など半導体装置を製造
する際に、半導体基板に多数の半導体素子が設けられて
、これらの素子を接続するために基板面上に複数の配線
層が多層に形成される。その場合、半導体基板は半導体
素子を形成して凹凸があり、更にその面上に配線層と絶
縁膜とを交互に積層すると、益々凹凸が激しく段差が太
きくなって、配線層の断線や短絡が起こりやすくなるこ
とが知られている。(b) Prior art and problems For example, when manufacturing semiconductor devices such as semiconductor integrated circuits (ICs), a large number of semiconductor elements are provided on a semiconductor substrate, and in order to connect these elements, multiple semiconductor devices are placed on the substrate surface. The wiring layers are formed in multiple layers. In this case, the semiconductor substrate has unevenness due to the formation of semiconductor elements, and when wiring layers and insulating films are alternately laminated on the surface, the unevenness becomes even more severe and the steps become thicker, causing disconnections and short circuits in the wiring layer. It is known that this is more likely to occur.
第1図はその断面図例を示し、1は半導体基板。FIG. 1 shows an example of its cross-sectional view, and 1 is a semiconductor substrate.
2は配線層、3は絶縁膜で、Cは断線しやすい部分、S
は短絡しやすい部分である。そのために、従来より被着
方法や被着後の処理方法を工夫して表面を平坦にする方
法が色々と提案されているが、それらはいづれもデリケ
ートな稠整を要し、必ずしも再現性良く平坦化すること
は出来ず、その上に表面形状に左右される方法である。2 is the wiring layer, 3 is the insulating film, C is the part that is prone to disconnection, and S
is a part that is easily short-circuited. To this end, various methods have been proposed to flatten the surface by devising the deposition method and post-deposition processing method, but all of these methods require delicate preparation and do not necessarily provide good reproducibility. This method cannot achieve flattening and is dependent on the surface shape.
(e) 発明の目的
本発明はこのような欠点を除去し、安定に被着膜の表面
を平坦化する形成方法を提案するものである。(e) Object of the Invention The present invention proposes a forming method that eliminates these drawbacks and stably flattens the surface of the deposited film.
(dl 発明の構成
その目的は、薄膜を被着し、ついでその膜厚の一部をエ
ツチングする工程を繰り返し反復して、所要の膜厚まで
積層する被着膜の形成方法によって達成される。(dl)Structure of the Invention The object is achieved by a method of forming a deposited film in which the steps of depositing a thin film and then etching a part of the film thickness are repeated until the desired thickness is reached.
(e) 発明の実施例
以下1図面を参照してアルミニウム配線層上に二酸化シ
リコン膜からなる絶縁膜を積層する実施例を用いて詳細
に説明する。第2図ないし第6図は本発明にかかるその
工程順断面図を示し、このうち第2図から第5図までは
被着とエツチングとの反復工程の一部分工程図で、第6
図は所要膜厚まで被着した断面図である。(e) Embodiments of the Invention Hereinafter, an embodiment in which an insulating film made of a silicon dioxide film is laminated on an aluminum wiring layer will be described in detail with reference to one drawing. 2 to 6 show cross-sectional views of the process according to the present invention, of which FIGS. 2 to 5 are partial process views of the repeated steps of deposition and etching;
The figure is a cross-sectional view of the film coated to the required thickness.
半導体基板11面に設けた膜厚1μmのアルミニウム配
線層12上に、同じく膜厚1μmの二酸化シリコン(S
i02 )膜13をスパッタ法で積層しようとすると、
初めに第2図に示すように膜厚数100人(1000Å
以下)の5i02 H@13 aを被着する。次いで、
第3図に示すようにイオンミリング法によってその膜厚
200〜300人(被着した膜厚の数分の−)をエツチ
ング除去する。On the aluminum wiring layer 12 with a thickness of 1 μm provided on the semiconductor substrate 11, silicon dioxide (S
i02) When trying to stack the film 13 by sputtering,
First, as shown in Figure 2, the film thickness is several hundred layers (1000 Å).
5i02 H@13a (below) is applied. Then,
As shown in FIG. 3, the film thickness of 200 to 300 layers (a fraction of the deposited film thickness) is etched away by ion milling.
イオンミリング法は垂直なエツチングがなされ、上記の
エツチング膜厚200〜300人は平坦面でのエツチン
グ厚さで、突出部分(配線層12上)は激しくエツチン
グされてこれより厚い膜厚がエツチング除去される。且
つその側面の先端部分状態となる。In the ion milling method, vertical etching is performed, and the above etching film thickness of 200 to 300 mm is the etching thickness on a flat surface, and the protruding parts (on the wiring layer 12) are violently etched, and the film thicker than this is etched away. be done. And it becomes the tip part state of the side surface.
次いで、再び第4図に示すようにスパッタ法で同じく膜
厚数100人の5i02膜13bを被着する。そうする
と、5i02膜は半導体基板ll上では前回の被着分と
併せて配線層12の上より厚く形成されており、またそ
の側面先端部分子が最も薄(形成されている状態になる
。かくして再びイオンミリング法によってその膜厚20
0〜300人をエツチング除去すると、第5図に示すよ
うに配線層12上は前回と同様に多量のSiO2膜が除
去され、且つ突出部分子は激しくエツチング除去されて
殆どなくなり、第5図に示す状態に形成される。Next, as shown in FIG. 4 again, a 5i02 film 13b having a thickness of several hundred layers is deposited by sputtering. Then, the 5i02 film is formed thicker on the semiconductor substrate 11 than on the wiring layer 12 together with the previous deposition, and the 5i02 film is the thinnest (formed) at the end of the side surface. The film thickness is 20% by ion milling method.
When 0 to 300 layers were removed by etching, a large amount of the SiO2 film was removed on the wiring layer 12 as shown in FIG. It is formed in the state shown.
このような工程を数回ないし士数回繰り返し反復するこ
とによって、第6図に示すように表面のなだらかな5i
02膜13を形成することができる。By repeating this process several to several times, the surface becomes smooth 5i as shown in Figure 6.
02 film 13 can be formed.
第6図はまだ5i021%13上に凹凸があるが、一層
厚く形成すると平坦面になる。In FIG. 6, there are still irregularities on 5i021%13, but if it is made thicker, it will become a flat surface.
上記が本発明にかかる形成方法の主旨であるが、このよ
うな形成方法は1個の反応装置内で被着とエツチングと
を交互に行うことが望ましく、第7図に装置概要の一例
を示す。即ち、左側はスパッタ装置21であって、5i
02ターゲツト22をアルゴンイオンで叩いて基板23
上に5i02膜を被着する。右側はイオンミリング装置
25で、プラズマ発生器26から出たアルゴンイオンが
加速されて基板23の表面をエツチングし、かようにし
て基板を載せたテーブル30を例えば2分毎に回転する
と、上記の形成方法を容易に交互に行うことが出来る。The above is the gist of the forming method according to the present invention, but in such a forming method, it is desirable to perform deposition and etching alternately within one reaction apparatus, and an example of an outline of the apparatus is shown in FIG. . That is, the left side is the sputtering device 21, and 5i
02 Hit the target 22 with argon ions and remove the substrate 23.
A 5i02 film is deposited on top. On the right side is an ion milling device 25, in which argon ions emitted from a plasma generator 26 are accelerated to etch the surface of the substrate 23, and when the table 30 on which the substrate is placed is rotated, for example, every two minutes, the above-mentioned etching process is performed. Forming methods can easily be alternated.
尚、これらの反応は減圧中で行うが、排気系は図示して
いない。Note that these reactions are carried out under reduced pressure, but the exhaust system is not shown.
上記はスパッタ法で被着してイオンミリング法でエツチ
ングする実施例であるが、その他の被着法(例えばプラ
ズマ気相成長法)やエツチング法(例えばりアクティブ
イオンエツチング法)を用いても形成できる。又、絶縁
膜だけでなく、配線層も同様にして平坦化できることは
言うまでもない。The above is an example in which the film is deposited by sputtering and etched by ion milling, but it can also be formed using other deposition methods (e.g., plasma vapor phase epitaxy) or etching methods (e.g., active ion etching). can. Furthermore, it goes without saying that not only the insulating film but also the wiring layer can be planarized in the same manner.
(f) 発明の効果
以上の説明から明らかなように、本発明は凹凸部のある
面上に平坦な被着膜を形成する方法で、凹凸形状に左右
されることなく、表面が平坦化されるために半導体装置
の品質向上に著しく寄与するものである。(f) Effects of the Invention As is clear from the above explanation, the present invention is a method for forming a flat deposited film on a surface with unevenness, and the surface can be flattened regardless of the shape of the unevenness. This makes a significant contribution to improving the quality of semiconductor devices.
第1図は従来の多層配線層の断面図とその問題点を示す
図、第2図ないし第6図は本発明による配線層の工程順
断面図、第7図は本発明の形成法を適用する反応装置の
一例の概要図である。
図中、1,11は半導体基板、2.12は配線層、3,
13,13a、13bは絶縁膜、21はスパッタ装置、
25はイオンミリング装置、30第1図
第2図
第5図
第6図
第 7 図
Δr
手続補正書防式)
%式%
2発11月の6(h、ネク羞醪6−)勤べ方法3 浦]
1−をする省
、、事1′1との1ソ1係 11シ′「出に・
11人江所 神≦・用県川崎11川り1;l+z l:
小111中]015+(522)名称富士通株式会Figure 1 is a cross-sectional view of a conventional multilayer wiring layer and its problems, Figures 2 to 6 are cross-sectional views of the wiring layer according to the present invention in the order of steps, and Figure 7 is a diagram showing the formation method of the present invention applied. FIG. In the figure, 1 and 11 are semiconductor substrates, 2.12 are wiring layers, 3,
13, 13a, 13b are insulating films, 21 is a sputtering device,
25 is an ion milling device, 30 Fig. 1 Fig. 2 Fig. 5 Fig. 6 Fig. 7 Fig. 3 ura]
1-Ministry, 1st section with 1'1 11th'
11 people Esho Kami ≦・Uchiken Kawasaki 11 Kawari 1;l+z l:
111th grade】015+(522) Name Fujitsu Limited
Claims (1)
工程を繰り返し反復して、所要の膜厚まで積層すること
を特徴とする被着膜の形成方法。1. A method for forming a deposited film, which comprises repeating the process of depositing a thin film and then etching a part of the film thickness until the desired thickness is reached.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22816682A JPS59115543A (en) | 1982-12-22 | 1982-12-22 | Forming method for coating film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22816682A JPS59115543A (en) | 1982-12-22 | 1982-12-22 | Forming method for coating film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59115543A true JPS59115543A (en) | 1984-07-04 |
Family
ID=16872259
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22816682A Pending JPS59115543A (en) | 1982-12-22 | 1982-12-22 | Forming method for coating film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59115543A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63233549A (en) * | 1987-03-20 | 1988-09-29 | Nippon Telegr & Teleph Corp <Ntt> | Thin film formation |
-
1982
- 1982-12-22 JP JP22816682A patent/JPS59115543A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63233549A (en) * | 1987-03-20 | 1988-09-29 | Nippon Telegr & Teleph Corp <Ntt> | Thin film formation |
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