JPS6242434A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the disconnection of upper layer wiring making step difference in wiring part gentle as well as thickness of interlayer insulating film coated therewith even by means of repeating isotropic and anisotropic etching processes several times. CONSTITUTION:A wiring formation surface 1 on a substrate is coated with an Al layer 2 and then a resist mask 3 is formed thereon. Next a bit of general isotropic chemical etching or isotropic plasma etching is performed to etch the Al 2 creeping in below the mask 3. Then a bit of anisotropic etching is performed to leave the part creeping in below the mask 3 entirely. Moreover anisotropic and isotropic etching processes are alternately performed to leave Al in the mask part but removing the residual Al entirely. Finally the mask 3 is removed to produce an Al wiring 2a with both side steps forming gentle slopes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that is effective for forming multilayer interconnections.

[Conventional technology]

Conventionally, when forming multilayer wiring on an insulator or semiconductor substrate, it has occurred that the upper layer wiring that intersects the lower layer wiring via the insulator is disconnected due to the shadow of a steep step in the lower layer wiring. Ru. Therefore, in order to alleviate the shadow 41 of this stepped portion, for example, as shown in the cross-sectional view of FIG. By solidifying, the polyimide layer 5 was planarized so that the slope of the step portion of the wiring 40 was made as flat as possible to prevent disconnection of the upper layer wiring formed on the polyimide layer 5.

[Problem that the invention seeks to solve]

In the conventional planarization method as described above, the corner portion 4 of the lower layer wiring 4
There was a problem in that the thickness of the polyimide ff15 in a was partially thin, which caused a problem.

[Means for solving problems]

To solve the above problem, in the present invention, when etching the lower layer wiring formed on the substrate, isotropic etching and anisotropic etching are alternately repeated multiple times, thereby eliminating the step difference in the lower layer wiring itself. The slope of the part is $ + the total is smooth.

〔Example〕

The present invention will now be explained by way of examples.

FIGS. 1(a) to 1(g) are cross-sectional views showing the process order for explaining the wiring forming process according to an embodiment of the present invention. First, in FIG. 1(a), a resist mask 3 is formed on an aluminum layer 2 deposited on a wiring formation surface 1 of a substrate. Next, as shown in FIG. 6(b), a little isotropic general chemical etching or isotropic plasma etching is performed. As a result, the aluminum 2 that enters the lower part of the mask 3 is etched. At the same time, if a little anisotropic etching such as reactive ion etching is applied, as shown in FIG. 1(C), the portion under the mask 3 is completely left intact for chemical processing and etching. Next, in Figure 1 (b
) isotropically etched again as shown in Figure 1(d).
) The etching at the bottom of the mask 3 is enlarged in the horizontal direction. Further, anisotropic etching is performed to obtain the state shown in FIG. 5(e), and finally, isotropic etching is performed to remove all aluminum except for the masked portion.

Next, by removing the mask 3, a wiring 2a with a gently sloped surface on both sides as shown in FIG. 1 is obtained. Even if the entire interlayer insulating film is formed on this layer, the coating will have a uniform thickness because the corners of the lower layer wiring are eliminated.

In the above etching step V, the order of anisotropic etching and isotropic etching may be either carried out first, and the slope of the stepped portion can be changed by fully controlling each etching step M. In that case, the anisotropic etch: L7
Increasing the amount of etching will make the slope steeper, and increasing the amount of isotropic etching will make the thorax more gentle. Furthermore, the greater the number of times each etching is performed, the smoother the etching will be.

〔Effect of the invention〕

As explained above, in the etching of the wiring part, the present invention repeats isotropic etching and anisotropic etching multiple times to smooth out the difference in the wiring part, and then apply an interlayer insulating film with a plate diameter on top of it. It is possible to make the thickness uniform and prevent disconnection accidents in the upper layer wiring.

[Brief explanation of drawings]

FIGS. 1(a) to 1(g) are preliminary cross-sectional views for explaining the wiring forming process according to the present invention, and FIG. 2 is a cross-sectional view for explaining the planarization of the wiring stepped portion of a conventional semiconductor device. 1... Wiring formation board, 2... Aluminum layer, 2a. 4... Aluminum wiring, 3... Resist mask, 5... Viscous material for flattening (polyimide layer)
. Agent Patent Attorney Susumu Uchihara l'□・, $ /
concave figure 2

Claims (1)

[Claims] In a method for manufacturing a semiconductor device including depositing a conductive layer on a substrate and forming wiring of the conductive layer by etching, the etching includes alternating isotropic etching and anisotropic etching. A method for manufacturing a semiconductor device, characterized in that the process is repeated several times.