JPS5911531U - Voltage-frequency conversion circuit - Google Patents
Voltage-frequency conversion circuitInfo
- Publication number
- JPS5911531U JPS5911531U JP10552482U JP10552482U JPS5911531U JP S5911531 U JPS5911531 U JP S5911531U JP 10552482 U JP10552482 U JP 10552482U JP 10552482 U JP10552482 U JP 10552482U JP S5911531 U JPS5911531 U JP S5911531U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- frequency conversion
- conversion circuit
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の電圧−周波数変換回路を示す回路図、第
２図は本考案の電圧−周波数変換回路の一実施例を示す
ブロック図、第３図は第２図に示す本考案の電圧−周波
数変換回路の谷周回路を示す回路図、第４図はＡ／Ｄコ
ンバータ、メモリ回路における出力信号、入力信号およ
びデータの内容を示す図である。
１．５・・・・・・ＯＰアンプ、２，６，７．８・・・
・・・抵−抗、３・・・・・・コンデンサ、４・・・・
・・電界効果トランジスタ、９・・・・・・Ａ／Ｄコン
バータ、１０・・・・・・メモリー回路、１１・・・・
・・分周回路、１２・・・・・・クロック回路。Fig. 1 is a circuit diagram showing a conventional voltage-frequency conversion circuit, Fig. 2 is a block diagram showing an embodiment of the voltage-frequency conversion circuit of the present invention, and Fig. 3 is a circuit diagram showing the voltage-frequency conversion circuit of the present invention shown in Fig. 2. - A circuit diagram showing the valley circuit of the frequency conversion circuit. FIG. 4 is a diagram showing the contents of output signals, input signals, and data in the A/D converter and the memory circuit. 1.5...OP amplifier, 2,6,7.8...
...Resistance, 3...Capacitor, 4...
...Field effect transistor, 9...A/D converter, 10...Memory circuit, 11...
...Frequency divider circuit, 12...Clock circuit.
Claims (1)
換して出力するＡ／Ｄコンバータと、所定の周波数の基
本クロック信号を出力するクロック回路と、前記Ａ／Ｄ
コンバータからのデジタル信号に対応するアドレスを有
しかつこのアドレスに前記クロック回路の基本クロック
信号を分周制御する所定の制御信号がメモリされるとと
もに、前記Ａ／Ｄコンバータからのデジタル信号によっ
てこれに対応するアドレスの前記制御信号を出力するメ
モリ回路と、−前記クロック回路からの基本クロック信
号を前記メモリ回路からの制御信号で分周する分周回路
とを具備してなることを特徴とする電圧−周波数変換回
路。an A/D converter that converts an analog signal into a corresponding predetermined digital signal and outputs it; a clock circuit that outputs a basic clock signal of a predetermined frequency;
A predetermined control signal having an address corresponding to the digital signal from the converter and controlling the frequency division of the basic clock signal of the clock circuit is stored at this address, and is also controlled by the digital signal from the A/D converter. a memory circuit that outputs the control signal of a corresponding address; and - a frequency dividing circuit that divides the basic clock signal from the clock circuit by the control signal from the memory circuit. -Frequency conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10552482U JPS5911531U (en) | 1982-07-12 | 1982-07-12 | Voltage-frequency conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10552482U JPS5911531U (en) | 1982-07-12 | 1982-07-12 | Voltage-frequency conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5911531U true JPS5911531U (en) | 1984-01-24 |
Family
ID=30247307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10552482U Pending JPS5911531U (en) | 1982-07-12 | 1982-07-12 | Voltage-frequency conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5911531U (en) |
-
1982
- 1982-07-12 JP JP10552482U patent/JPS5911531U/en active Pending
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