JPS58121435U - Logic circuit that selects and holds one of multiple inputs - Google Patents
Logic circuit that selects and holds one of multiple inputsInfo
- Publication number
- JPS58121435U JPS58121435U JP12396681U JP12396681U JPS58121435U JP S58121435 U JPS58121435 U JP S58121435U JP 12396681 U JP12396681 U JP 12396681U JP 12396681 U JP12396681 U JP 12396681U JP S58121435 U JPS58121435 U JP S58121435U
- Authority
- JP
- Japan
- Prior art keywords
- selects
- holds
- logic circuit
- multiple inputs
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の回路を示す図、第２図は本考案の一実施
例を示す図、′第３図はそのタイムチャートである。
２３．２４．２５．２６．２７・・・ナントゲート。FIG. 1 is a diagram showing a conventional circuit, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a time chart thereof. 23.24.25.26.27... Nantes Gate.
Claims (1)
複数個のゲートと、これらのゲートの出力信号を入力と
するオア回路と、このオア回路の出力信号とこの出力信
号を制御する制御信号を入力とし出力信号をオア回路の
入力とするゲートから成る複数入力の−を選択し保持す
る論理回路。A plurality of gates that receive an input signal and a control signal that controls the input signal, an OR circuit that receives the output signals of these gates, and an output signal of this OR circuit and a control signal that controls this output signal. A logic circuit that selects and holds the - of multiple inputs, consisting of a gate whose input is an output signal and whose output signal is an input of an OR circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12396681U JPS58121435U (en) | 1981-08-21 | 1981-08-21 | Logic circuit that selects and holds one of multiple inputs |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12396681U JPS58121435U (en) | 1981-08-21 | 1981-08-21 | Logic circuit that selects and holds one of multiple inputs |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58121435U true JPS58121435U (en) | 1983-08-18 |
Family
ID=30101341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12396681U Pending JPS58121435U (en) | 1981-08-21 | 1981-08-21 | Logic circuit that selects and holds one of multiple inputs |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58121435U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4843253A (en) * | 1971-10-01 | 1973-06-22 | ||
| JPS5236960A (en) * | 1975-09-19 | 1977-03-22 | Hitachi Ltd | Miltiplexer circuit |
-
1981
- 1981-08-21 JP JP12396681U patent/JPS58121435U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4843253A (en) * | 1971-10-01 | 1973-06-22 | ||
| JPS5236960A (en) * | 1975-09-19 | 1977-03-22 | Hitachi Ltd | Miltiplexer circuit |
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