JPS5986731U - Tuning control circuit - Google Patents
Tuning control circuitInfo
- Publication number
- JPS5986731U JPS5986731U JP18343282U JP18343282U JPS5986731U JP S5986731 U JPS5986731 U JP S5986731U JP 18343282 U JP18343282 U JP 18343282U JP 18343282 U JP18343282 U JP 18343282U JP S5986731 U JPS5986731 U JP S5986731U
- Authority
- JP
- Japan
- Prior art keywords
- tuning
- delay
- control circuit
- tuning control
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の選局装置の概略ブロック図である。第２
図は従来の選局装置における同調制御電圧と設定電圧と
の関係を示す図である。第３図は〜 この考案の一実施
例の概略ブロック図である。第４図は第３図に示すＤ−
Ａ変換器の概略ブロック図である。第５図は第３図の各
部の波形図である。
第６図はこの考案の他の実施例の概略ブロック図である
。 −
図において、４は制御素子、５はＤ−Ａ変換器、６は電
子チューナ、７は遅延回路、８はトランジスタ、９は抵
抗、１０は可変抵抗器、１１はコンデンサ、５１はパル
ス変調器、５２は低域通過フィルタ、８は制御回路を示
す。FIG. 1 is a schematic block diagram of a conventional channel selection device. Second
The figure is a diagram showing the relationship between tuning control voltage and setting voltage in a conventional channel selection device. FIG. 3 is a schematic block diagram of an embodiment of this invention. Figure 4 shows D- shown in Figure 3.
FIG. 2 is a schematic block diagram of an A converter. FIG. 5 is a waveform diagram of each part of FIG. 3. FIG. 6 is a schematic block diagram of another embodiment of this invention. - In the figure, 4 is a control element, 5 is a D-A converter, 6 is an electronic tuner, 7 is a delay circuit, 8 is a transistor, 9 is a resistor, 10 is a variable resistor, 11 is a capacitor, 51 is a pulse modulator , 52 is a low-pass filter, and 8 is a control circuit.
Claims (1)
て、 遅延時間が可変に構成され、電圧が与えられたことに応
じて設定された遅延時間経過後に遅延信号を出力する遅
延手段、および 前記遅延手段に前記電圧を与えるとともに前記遅延信号
を設け、前記遅延信号の遅延量に基づいて前記同調回路
の同調周波数を制御する牛Ｉ御手段を備えた、同調制御
回路。 （２）前記制御手段は、前記遅延手段出力の遅延時間に
比例したパルス幅のパルス列を発生し、このパルス列に
応じて前記同調回路の同調周波数を制御するようにした
、実用新案登録請求の範囲第１項記載の同調制御回路。[Claims for Utility Model Registration] '(1) A tuning control circuit for controlling a tuning circuit, the delay time of which is variable, and after the delay time set according to the application of voltage has elapsed. A delay means for outputting a delayed signal, and a control means for applying the voltage to the delay means and providing the delay signal, and controlling the tuning frequency of the tuning circuit based on the amount of delay of the delay signal, Tuning control circuit. (2) The scope of the utility model registration claim, wherein the control means generates a pulse train with a pulse width proportional to the delay time of the output of the delay means, and controls the tuning frequency of the tuning circuit in accordance with this pulse train. The tuning control circuit according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18343282U JPS5986731U (en) | 1982-12-01 | 1982-12-01 | Tuning control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18343282U JPS5986731U (en) | 1982-12-01 | 1982-12-01 | Tuning control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5986731U true JPS5986731U (en) | 1984-06-12 |
Family
ID=30396991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18343282U Pending JPS5986731U (en) | 1982-12-01 | 1982-12-01 | Tuning control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5986731U (en) |
-
1982
- 1982-12-01 JP JP18343282U patent/JPS5986731U/en active Pending
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