JPS5911443A - 記憶制御回路 - Google Patents

記憶制御回路

Info

Publication number
JPS5911443A
JPS5911443A JP57120531A JP12053182A JPS5911443A JP S5911443 A JPS5911443 A JP S5911443A JP 57120531 A JP57120531 A JP 57120531A JP 12053182 A JP12053182 A JP 12053182A JP S5911443 A JPS5911443 A JP S5911443A
Authority
JP
Japan
Prior art keywords
data
memory
circuit
block
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57120531A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6310449B2 (enExample
Inventor
Toshio Yoshikawa
敏雄 吉川
Kimihiro Ishitobi
石飛　公啓
Yamato Sato
大和 佐藤
Noriya Murakami
村上　憲也
Seikichi Takeuchi
竹内　晟吉
Tomohisa Hirokawa
広川　智久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57120531A priority Critical patent/JPS5911443A/ja
Publication of JPS5911443A publication Critical patent/JPS5911443A/ja
Publication of JPS6310449B2 publication Critical patent/JPS6310449B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP57120531A 1982-07-13 1982-07-13 記憶制御回路 Granted JPS5911443A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57120531A JPS5911443A (ja) 1982-07-13 1982-07-13 記憶制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57120531A JPS5911443A (ja) 1982-07-13 1982-07-13 記憶制御回路

Publications (2)

Publication Number Publication Date
JPS5911443A true JPS5911443A (ja) 1984-01-21
JPS6310449B2 JPS6310449B2 (enExample) 1988-03-07

Family

ID=14788576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57120531A Granted JPS5911443A (ja) 1982-07-13 1982-07-13 記憶制御回路

Country Status (1)

Country Link
JP (1) JPS5911443A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193190A (ja) * 1987-02-06 1988-08-10 ヤマハ株式会社 電子楽器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131228A (en) * 1975-04-25 1976-11-15 Philips Nv Device for processing digital information element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51131228A (en) * 1975-04-25 1976-11-15 Philips Nv Device for processing digital information element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193190A (ja) * 1987-02-06 1988-08-10 ヤマハ株式会社 電子楽器

Also Published As

Publication number Publication date
JPS6310449B2 (enExample) 1988-03-07

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