JPS5911403A - Backup system of sequence control - Google Patents

Abstract

PURPOSE:To ensure a smooth operation of a backup controller when a main controller has a fault, by transferring an index showing the executing unit of a control sequence to the backup controller via a switch. CONSTITUTION:Both a main controller MDC and a backup controller BDC contain fixed memories ROMM and ROMB, variable memories RAMM and RAMB, and input/output circuits I/OM and I/OB centering on processors CPUM and CPUB respectively. The CPUM usually executes the instruction of the ROMM and controls the I/OM in accordance with a data base DB. At the same time, a CPUS of a switch SW transfers periodically the DB of the RAMM to an RAMS. A pointer area is provided to each RAM to store an index showing the executing unit of a control sequence. This index RAMS is transferred in response to the transfer of the DB to the SW. When the MDC has a fault, a fault signal COS is applied to the BCD via the SW. Then the index is transferred to the pointer of the DBMB, and at the same time the start is indicated to the CPUB to substitute the control.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a backup method applied to a sequence control device.

As a backup method for the control device, controller 1
There is a dual system in which a spare controller is provided for each controller to perform parallel operation, and a duplex system in which one spare controller is installed for several controllers.
In the dual system, the controller outputs of the active and standby controllers are compared and verified while running in parallel, and failures due to discrepancies between the two rivers are detected and control is performed to switch between the active and standby systems. Since the logic configuration becomes complicated and the number of standby controllers increases, it is uneconomical, so the duplex method is generally adopted.

However, in the duplex system, in the case of sequence control, when the main controller fails and the control is switched to the standby controller, the standby controller (<fl) starts a new control operation, so the control operation is The starting situation is unspecified υ, resulting in the disadvantage that the control operation cannot be taken over smoothly.

The present invention has the purpose of fundamentally eliminating such disadvantages of the conventional system, and uses a backup system consisting of a main controller, a switch, and a standby controller, each having a processor and a memory, to transfer execution units of control sequences to each memory. A pointer area is provided to store the index indicated, and the index in the pointer area in the main controller is transferred to the pointer area of the switch in accordance with the database transfer, and when a failure occurs in the main controller, the index is transferred from the pointer area of the switch to the standby pointer area. An extremely effective backup method for sequence control is provided in which an index is transferred to the pointer area of the controller, and a standby controller starts performing control operations on behalf of the controller based on the index.

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

The figure is a block diagram showing the entire configuration, and the main controller MDC and backup controller BDC are centered around a processor such as a microprocessor CPUM%CPUB, and fixed memories ROMM and ROMB.

Variable memory RAMM, RAMB and input/output circuit I/
Arrange OM, I/OB around the periphery and connect them to bus line B.
Normally, the processor CPU executes instructions stored in the fixed memory ROMM and performs control operations based on the database stored in the variable memory IJRAMM.
Sequence control for processes, etc. is performed by exchanging data with the outside via the OM.

The switch SW also includes a similar processor CPU s and variable memory RAM 5, and is connected to the buffer memory BMM and register RGM of the main controller MDC via the interface I/Fa. Transfer control is periodically performed to receive and store the MM database into the variable memory RAM 5 via the buffer memory BMM.

For this reason, the variable memory RAM has variable memory RAM.
The same database as the M M database is stored, so if the main controller MDC fails, variable memo! The database in the JRAM 5 is to be transferred to the variable memory RAM B of the standby controller BDC.

1 That is, it is connected to the register RGB and buffer memory BMB of the spare controller BDC via the interface IZFb, and the main controller MDC
The failure signal (COS) by self-diagnosis of
If T occurs, a fault command (ps) is sent via the OR gate axis.
is given to the interface I/Fa, and in response, the processor CPU 5 transfers the database in the variable memory RAM s to the variable memory IJ via the register RG +f:
In addition to transferring the data to RAMB, it also instructs processor CPUB to start acting as a control operation.

Therefore, in the backup controller BDC, the processor CPUn executes the instructions in the fixed memory IJROMB having the same storage contents as the fixed memory ROMM, and performs control operations based on the transferred database in the variable memory IJRAM. It starts exchanging data with processes etc. via the input/output circuit I10° and performs control operations on behalf of it.

In addition, the main controller MDC and the backup controller BDC
Since they have the same configuration, if a failure occurs in the backup controller BDC, the backup controller BDC
OR gate CB? A fault command (DS) is sent out via the main controller M for control in the opposite direction to that described above.
The DC initiates the control operation.

However, variable memory RAM M s RAM S %
RAM B is provided with a pointer area (hereinafter referred to as pointer) that stores an index indicating the execution unit of the control sequence.
As the control sequence of the DC progresses, indicators A to A, etc. indicating execution units are sequentially updated and stored in a program counter or the like in accordance with the order of execution.

In other words, in the main controller MDC, as the content of the 1 pointer is updated from A to 1, the qi execution sequence changes from a to i, but at times t8 and t. If the database transfer I is carried out between
is updated from to D.

Also, time t. However, when the operation of the main controller MDC is unstable, when a failure command (DS) is sent at time ttl, the processor CPU5 of the switch sw transfers the index to the backup controller BDC at time t5. The content of the 1 pointer in the controller BDC is D, and based on this, the backup controller BDC starts the same operation as the main controller MDC, and updates the index from D to G, etc.

Therefore, although the execution sequence in the standby controller BDC overlaps slightly with the execution sequence in the main controller MDC, it is possible to continue the control that the main controller MDC has executed until now. The backup controller BDC will smoothly take over the control operation.

Note that the time interval for "database transfer" may be determined depending on the situation, and the number of main controllers MDC and corresponding switching devices may be determined arbitrarily. can be freely modified.

As is clear from the above explanation, according to the present invention, if a failure occurs in the main controller, the backup controller will take over the previous control sequence as it is. Since the control situation is smoothed by switching from the controller to the standby controller, remarkable effects can be obtained in sequence control for various applications.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment of the present invention. MDC--Main controller, SW/Fist...Switcher,
BDC@--Spare controller, CPU MsCP
Us% CPUB@Fist- Processor, RAMM. RAM5. RAMB "..." Variable memory. Applicant: Yamatake Honeywell Hayashiki Company Agent
Person Masaki Yamakawa (and 1 other person) 4-28-1 Nishirokugo, Ota-ku, Tokyo Yamatake Honeywell Co., Ltd. Kamadamaba 0 Inventor Tadashi Koibuchi - 4-28-1 Nishirokugo, Ota-ku, Tokyo Yamatake Honeywell Co., Ltd. Kamide Ballpark 0 Inventor: Uchinuma side - Ro 4-28-1 Nishirokugo, Ota-ku, Tokyo Yamabu Honeywell Co., Ltd. Kamide Ballpark 0 Inventor: Magai Atsushi 4-28 Nishirokugo, Ota-ku, Tokyo No. 1 Yamatake Honeywell Co., Ltd. Kamata Tamaba 0 Inventor Miyuki Shimizu 4-28-1 Nishirokugo, Ota-ku, Tokyo Inside Yamatake Honeywell Co., Ltd. Kamata Factory

Claims (1)

[Claims] a main controller including a processor that performs control operations and a memory that stores a database; a switching device that includes a memory to which the database in the memory is transferred; and a processor that performs transfer control; In a backup system comprising a memory that receives a database transferred from a memory of a switching device and a backup controller equipped with a processor that performs control operations on behalf of the main controller based on the database, an index indicating an execution unit of a control sequence to each of the memories. A pointer area is provided for storing the index of the pointer area in the main controller, and the index of the pointer area in the main controller is transferred to the pointer area of the switch in accordance with the transfer of the database, and when a failure occurs in the main controller, the index of the pointer area is transferred to the reserve. A sequence control backup method characterized by data transfer to the pointer area of the controller.