JPH06243102A - Interruption synchronizing method for multiplex information processing system - Google Patents

Abstract

PURPOSE:To attain interruption processing among plural CPUs with better performance and better synchronism by increasing the communicating speed between a pair of CPUs. CONSTITUTION:A main storage MS 101 is used in common by the CPU 102, 103 and 104 which are connected to each other via a signal line 160. A hardware application area HSA of the MS 101 includes an inter-CPU communication area CCA. When the MS 101 requests the operations of both CPU 102 and 103, the operation contents parameter is stored in its own area 112 and at the same time sends the operation requests to both CPU 103 and 104 via the line 160. Thus the CPU 103 and 104 interrupt their normal processings and read the operation content parameter respectively out of the area 112 of the MS 101 to carry out each prescribed processing. Then both CPU 103 and 104 reports the end of each operation to the CPU 102 via the line 160.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to interrupt processing in a multiple information processing system, and more particularly to an interrupt synchronizing method between a plurality of central processing units having a tightly coupled configuration.

[0002]

2. Description of the Related Art Generally, a plurality of central processing units (hereinafter referred to as CP
In a multiple information processing system (hereinafter, referred to as an MP system) including a main memory (hereinafter, referred to as MS) and a main memory (hereinafter, referred to as MS) shared by these CPUs, it is essential to exchange information between the CPUs.

As a first example, for example, C by an instruction word issued by software running on each CPU
There is communication between PUs. Conventionally, this is realized as a so-called signal processor instruction (hereinafter referred to as SIGP instruction).

When it becomes necessary to send and receive information between CPUs, software running on the requesting CPU issues a SIGP instruction with the CPU address of the requesting destination and the requested operation as operands. Operand (also called order) as parameter CP of request destination
The request-destination CPU, which is sent to U and is the receiving side, performs a predetermined operation in accordance with the sent parameters. The process of sending this parameter to the requested CPU is performed by hardware, and this interface is called a multiprocessor interface (hereinafter referred to as MP interface). There are various operations in the predetermined operation according to this parameter. For example, when communication is performed between CPUs, the software running on the requesting CPU is the CP of the requesting destination.
Issue a SIGP instruction to U that has an external interrupt request of an external call (External Call) as an operand,
The request-destination CPU, which is the receiving side, calls the external call (External Call) if the interrupt mask of the external interrupt is on.
) External interrupt, and the request-side CPU that is the receiving side
The software running above recognizes that another CPU is requesting the exchange of information between the CPUs. This software is generally called a supervisor or an operating system (hereinafter referred to as OS) and controls the entire MP system. Subsequent exchange of information between CPUs is software under the control of this OS. To be done.

As a second example, for example, when each CPU has an address translation buffer (hereinafter referred to as TLB) and shares the MS, when one CPU rewrites the address translation table, other CPUs TLB
Must be purged, and there is an exchange of purge TLB requests between CPUs. For this reason, each CPU that has conventionally constituted the MP system has a purge T
It is provided with an inter-CPU interface (hereinafter referred to as PTLB interface) depending on the hardware that sends and receives the LB request.

As described above, in the prior art, two types of interfaces, an MP interface and a PTLB interface, are provided as CPU-to-CPU interfaces depending on the hardware that controls the exchange of information between the CPUs constituting the MP system. There is. The general functions of these two types of interfaces have the following differences.

The PTLB interface generally has an invalidating page table entry command (hereinafter referred to as IPT).
Since it is used according to (E command), it has a one-to-many communication function between two or more CPUs at the same time, but has a function to generate an interrupt to the CPU that receives the purge TLB request. Not not. Further, since the PTLB interface is used as a part of IPTE instruction execution, the operations are synchronized in each CPU and are realized as a high-speed inter-CPU interface. On the other hand, since the MP interface is used according to the SIGP instruction, it has only a one-to-one communication function between two CPUs at the same time, but an interrupt is generated to the CPU that receives the order of the SIGP instruction. It has the function of Further, since the MP interface is used as a part of the interrupt accompanying the execution of the SIGP instruction, it is realized as a relatively low-speed inter-CPU interface.

[0008]

In the prior art, a certain C
When the PU requests an interrupt to a plurality of other CPUs having the MP configuration, the PU requests an interrupt to each CPU via the MP interface according to the SIGP instruction. In this case, the other configured The number of SIGP instructions corresponding to the number of CPUs was sequentially issued. Furthermore, as a means for the OS running on the CPU that issued the SIGP instruction to detect that an interrupt has occurred in all the other CPUs, another C
A method has been adopted in which the interrupt handler of the OS that starts running when an interrupt occurs in the PU and the interrupt request handler of the OS that issued the SIGP instruction are realized by software agreement.

However, the interrupt synchronization method realized by the software arrangement of this OS is not limited to other CPUs.
Overhead for sequentially issuing SIGP instructions to SIGP
MP, which is an inter-CPU interface with relatively slow instructions
Overhead for using the interface and O
There is a software overhead for S to recognize that an interrupt has occurred in all the other CPUs, and these overheads are performance degradation factors that cannot be ignored in realizing interrupt synchronization in a plurality of CPUs.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an interrupt synchronization method for a multiple information processing system, which has significantly improved performance.

[0011]

According to the present invention, there is provided a multiple information processing system comprising a plurality of processing devices and a storage device shared by the respective processing devices, wherein the processing is performed as a communication means between the processing devices. A first communication means for directly exchanging information between the devices and a second communication means for exchanging information between the processing devices via the hardware use area in the shared storage device are provided. By configuring the entire MP interface by combining the communication means of
This is to realize speeding up of one-to-many communication of the processing devices and generate synchronous interrupts to the plurality of processing devices.

[0012]

When each processing unit (CPU) has the address translation buffer (TLB) and shares the storage unit (MS), the PTLB interface between the CPUs simultaneously becomes two.
This is used for the first communication means by utilizing the fact that it has a one-to-many communication function between one or more CPUs.

The CPU requesting the interrupt stores the parameter relating to the interrupt factor in the hardware use area in the shared MS which is the second communication means, and simultaneously sends it to other CPUs by the PTLB interface which is the first communication means. A read request for the parameter is sent to. The CPU that has received the request via the PTLB interface, which is the first communication means, recognizes that it is an interrupt request by accessing the hardware use area of the shared MS, which is the second communication means. Hold the interrupt in the CPU or complete the interrupt execution. After that, a signal indicating that the request has been accepted is returned to the requesting CPU via the PTLB interface which is the first communication means, and the own CPU enters the waiting state. The request source CPU sends an operation start permission signal to the first communication after a signal indicating that the request has been received is returned from all the CPUs that have transmitted the interrupt request via the PTLB interface that is the first communication means. PTLB as a means
All Cs that have sent an interrupt request via the interface
Send to PU. Each CPU that has received the operation start permission signal releases the waiting state and starts a normal processing operation.

Regarding the point that the PTLB interface has a function of synchronizing the operations in each CPU because it is used as a part of instruction execution, the CPU that has received the request is the second main communication means, which is the shared main memory. When the interrupt is suspended in the own CPU by accessing the above hardware use area, a signal indicating that the request is accepted via the PTLB interface which is the first communication means is issued to the requesting CPU.
It is realized by separating whether to return to the request source CPU or to return a signal indicating that the request is accepted at the time of completion of interrupt execution.

As described above, according to the present invention, it is possible to realize the MP interface which speeds up the one-to-many communication between the CPUs, and the performance is remarkably improved and the CPUs having a better synchronization can be realized. It is possible to realize interrupt processing synchronization.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an interrupt synchronization method for a multiple information processing system according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a configuration example (MP system) of a multiple information processing system which realizes the interrupt synchronization method of the present invention. This is an example of a configuration with three central processing units (CPUs), but a configuration with four or more units is also possible. In FIG. 1, the shared main memory (MS) 101 has a signal line 15
0, 151 and 152 through the CPUA 102, CPU
B103 and CPUC104 are connected, and CPUA
102, CPUB103 and CPUC104 are signal lines 1
They are mutually connected via 60. CPUA102,
CPUB103 and CPUC104 are signal lines 1 respectively
Shared M independently via 50, 151 or 152
Any area in S101 can be accessed. Furthermore, CPUA102, CPUB103 and CPUC10
4 are CPs independent of each other and simultaneously through the signal line 160.
Information can be exchanged between U. The information transmitted and received via the signal line 160 includes interrupt processing request to the partner CPU, waiting state cancellation instruction request information, request acceptance information which is a response from the partner CPU, and the like, as related to the present invention. This signal line 160 is connected to the CPUA10.
2. If each of the CPUB103 and the CPUC104 has an address translation buffer (TLB), each CPU
Can use the inter-CPU interface (PTLB interface) that sends and receives the purge TLB request.

The shared MS 101 is a software use area (hereinafter referred to as SUA) used by general software and a hardware use area (hereinafter referred to as HSA) that is uniquely used by the hardware system in hardware operation processing.
Is divided into Both SUA and HSA are signal lines 150,
Through the 151 or 152, it is possible to access from all the CPUs 102, 103, 104 that compose the MP system. In other words, if any area in the HSA is used as a communication buffer between CPUs (communication area between CPUs), it does not affect the software running on the system and all CPUs in the system are affected. Information can be exchanged between the two. CCA is an HSA for shared MS 101
It is an inter-CPU communication area provided inside.

In this embodiment, CCA is a system common area (hereinafter referred to as SCA) 111, a CPUA used area (hereinafter referred to as CPUAA) 112, a CPUB used area (hereinafter referred to as CPUBA) 113, and a CPUC used area (hereinafter referred to as CPUCA). ) 114.
The SCA 111 stores information commonly used by all the CPUs forming the MP system. This S
The information stored in the CA 111 includes, for example, a measurement block key, a measurement block update mode bit, a measurement block starting point address, or a lock area for exclusively using the SCA area from each CPU. CPUAA112
Is information uniquely used by the CPU A 102 and other CPUs.
This is an area for storing information to be sent to. CPUBA
113 and CPUCA114 are respectively CPUB10
3 and CPUC104 use the role of CPUAA
Similar to 112. In the present invention, this area 11
2, 113, 114 are used to transfer information to be exchanged via the MP interface to another CPU.

FIG. 2 is a flowchart showing a processing procedure as an embodiment of the interrupt synchronization method of the present invention, and FIG. 3 is a detailed flowchart of some steps in FIG. Hereinafter, referring to FIGS. 2 and 3, the CPUA 10 in FIG.
2, the transfer of information related to the interrupt processing between the CPUB 103 and the CPUC 104 will be described in detail. Note that, here, the CPUA 102 is the interrupt request source, and the CPU
The request destinations are B103 and CPUC104, but needless to say, the present invention is not limited to this.

Step 201 : CPUA 102 is C
When requesting some operation from the PUB 103 and the CPUC 104, the CPUA 102 first stores the MP interface parameter defining the requested operation content in the HSA CPUAA 112 in the shared MS 401 via the signal line 150. The storage operation in this case is performed in the same manner as the normal main memory storage access.

Step 202 : Next, CPUA10
2 is a signal line 1 for CPUB103 and CPUC104
An operation request signal is sent via 60.

Step 203 : The CPU A 102
Signal line 160 for CPUB103 and CPUC104
After sending the operation request signal via the line, the CPU B 103 and the CPU C 104 enter a waiting state until a report signal indicating that the requested operation is completed is returned via the signal line 160.

Steps 211 and 221 :
When the CPUB 103 and the CPUC 104 receive the operation request signal from the CPUA 102 via the signal line 160,
The normal processing currently being executed is temporarily suspended to start the MP interface communication operation (hereinafter referred to as break-in).

Step 212 and step 222 :
The CPUB 103 and the CPUC 104 temporarily suspend the process being executed due to the break-in and start the MP interface communication process.

Step 213 and step 223 :
In this MP interface communication process, CPUB1
03 and the CPUC 104 share the MP interface parameter that regulates the requested operation content stored in advance by the CPUA 102, and the CPUAA 11 in the HSA of the shared MS 101.
2 through the signal lines 151 and 152, respectively. The fetch operation in this case is performed in the same manner as the normal main memory fetch access.

Steps 214 and 224 :
The CPUB 103 and the CPUC 104 transmit the operation request sent via the signal line 160 and the HSA of the shared MS 101.
Depending on the MP interface parameter that regulates the requested operation content extracted from the internal CPUAA 112, the CPUA 1
It determines what operation 02 is requesting and executes the specified operation.

Steps 215 and 225 :
When the execution of the operation designated by the CPUA 102 is completed, the CPUB 103 and the CPUC 104 send an operation end signal to the CPUA 102 via the signal line 160.

Steps 216 and 226 :
CPUB103 and CPUC104 are CPUA102
On the other hand, after sending the operation end signal through the signal line 160, the CPU A 102 waits until a signal instructing to continue the normal processing is returned through the signal line 160.

Step 204 : The CPUA 102 enters the waiting state in Step 203, and then the CPUB 103
Also, it is monitored that the operation end signal is returned from both of the CPUC 104 and the CPUC 104 via the signal line 160. And
When recognizing that the operation end signals are returned from both the CPUA 103 and the CPUC 104 via the signal line 160, the CPUA 102 proceeds to step 205.

Step 205 : Both CPUs 10
When the operation end signal is returned from 3,104, CP
The UA 102 sends a normal processing continuation request signal to the CPUB 103 and the CPUC 104 via the signal line 160. After that, the CPUA 102 restarts the normal processing.

Steps 219 and 229 :
Upon receiving the normal processing continuation request signal from the CPUA 102 via the signal line 160, the CPUB 103 and the CPUC 104 end the waiting state of steps 216 and 226 and restart the normal processing. This normal processing restart is normal instruction processing restart if the interrupt mask for the pending interrupt is off, and if the interrupt mask for the pending interrupt is on, the hardware-dependent interrupt is restarted. It is the activation from the operation, and when the interruption operation by the hardware is completed, it is the activation of the interrupt processing by the software.

FIG. 3 shows steps 213, 214 and 215, C of the CPUB 103 in FIG.
9 is a flowchart showing a more detailed processing procedure of operations of steps 223, 224, and 225 of the PUC 104.

Step 301 : The CPUB 103 and the CPUC 104 fetch the MP interface parameters, which pre-store the required operation contents of the CPUA 102, from the HSA CPUAA 112 of the shared MS 101 via the signal lines 151 and 152, respectively. The fetch operation in this case is performed in the same manner as the normal main memory fetch access.

Step 302 : The CPUB 103 and the CPUC 104 take out the MP interface parameter from the CPUAA 112 in the HSA of the shared MS 101 via the signal lines 151 and 152, respectively, and then M
The instruction information in the P interface parameter is checked, and at this time, it is determined whether or not to send the operation end signal to the CPUA 102. At this point, if it is instructed to send the operation end signal, the procedure goes to step 307, and if not, the procedure goes to step 303.

Step 303 : The CPUB 103 and the CPUC 104 send the operation request sent via the signal line 160 and the CPUAA112 in the HSA of the shared MS 101.
Based on the MP interface parameter that regulates the requested operation content extracted from the above, what operation the CPU A 102 requests is determined. In this example, CPUB10
The CPU 3 and the CPU C 104 hold the interrupt factor defined according to the MP interface parameter.

Step 304 : The CPUB 103 and the CPUC 104 hold the interrupt factor and then execute the shared MS.
The instruction information in the MP interface parameter that regulates the requested operation content extracted from the CPUAA 112 in the HSA 101 is checked, and at this time, it is determined whether or not to send the operation end signal to the CPUA 102. If it is instructed to send the operation end signal at this point, step 30
7. If not instructed, go to step 305.

Step 305 : The CPU B 103 and the CPU C 104 activate the interrupt operation on their respective CPUs if the corresponding interrupt masks are on, and the normal instruction processing operation on their respective CPUs if the corresponding interrupt masks are off. Return to.

Step 306 : The CPUB 103 and the CPUC 104 wait for the completion of the interrupt operation on their respective CPUs. If the interrupt operation is completed, step 307
go to.

Step 307 : When the execution of the operation designated by the CPUA 102 is completed, the CPUB 103 and the CPUC 104 send an operation end signal to the CPUA 102 via the signal line 160.

[0041]

As is apparent from the above description, according to the present invention, the MP interface for transferring the communication information regarding the interrupt processing between the processing devices can be provided at a higher speed and from one processing device to a plurality of other processing devices. M that can simultaneously communicate with the group
Realized by P interface, HSA of shared storage
By exchanging the parameter relating to the interrupt factor using the area, it is possible to improve the performance and perform the interrupt synchronization processing between a plurality of processing devices with better synchronization. Furthermore, PTL
By utilizing the fact that the B interface has a one-to-many communication function between two or more processing devices at the same time, the hardware cost is increased from one processing device to another processing device group. It is possible to generate a synchronous interrupt which is not accompanied by the above and in which the overhead of interrupt synchronization is greatly reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a multiple information processing system to which an interrupt synchronization method of the present invention is applied.

FIG. 2 is a flowchart showing a processing procedure of an embodiment of an interrupt synchronization method of the present invention.

FIG. 3 is a flowchart showing details of some steps of the processing procedure of FIG.

[Explanation of reference numerals] 101 shared main storage device 102 to 104 central processing device 111 to 114 communication area between processing devices in HSA 150 to 152 signal line 160 communication line between processing devices

Claims (4)

[Claims] 1. A multiple information processing system comprising a plurality of processing devices and a storage device shared by the respective processing devices, wherein information is directly exchanged between the processing devices as a communication means between the processing devices. Information is exchanged between the processing devices via a first communication means for performing the above and a predetermined area of the hardware use area in the shared storage device (hereinafter, referred to as an inter-processing device communication area). A second communication means for performing the first communication means according to the type of communication between the processing devices,
Multiple information, characterized in that the second communication means or a combination of the first communication means and the second communication means exchanges information between processing devices and generates synchronized interrupts for a plurality of processing devices. An interrupt synchronization method for a processing system. 2. A processing device requesting an interrupt stores a parameter relating to an interrupt factor in a communication area between processing devices in a storage device which is the second communication means, and at the same time, performs other processing by the first communication means. A read request of a parameter related to an interrupt factor stored in the inter-processor communication area in the storage device is sent to the device, and the other processing device that receives the read request of the parameter related to the interrupt factor is the second communication unit. The parameter related to the interrupt factor stored in the inter-processor communication area in the storage device is read, the interrupt operation is performed according to the designation of the parameter related to the interrupt factor, and the operation completion report is transmitted by the first communication means. 2. The interrupt synchronization method for a multiple information processing system according to claim 1, wherein the interrupt is sent to a processing device that has requested the interrupt. 3. An inter-processor communication area in a storage device shared by each of the plurality of processors has an area unique to each of the plurality of processors, and the processor requesting an interrupt is an interrupt factor. Parameters related to the inter-processor communication area in the storage device are stored in its own area, and the other processing device receiving the read request of the parameter related to the interrupt request is the interrupt request of the inter-processor communication area in the storage device. 3. The parameter relating to the interrupt request is read from the area corresponding to the original device.
An interrupt synchronization method for the described multiple information processing system. 4. When a plurality of processing devices each have an address translation buffer (hereinafter referred to as TLB) and there is a communication means for directly sending and receiving a purge TLB request between the processing devices, the communication means is used. The interrupt synchronization method for a multiple information processing system according to claim 1, 2 or 3, wherein the interrupt synchronization method is used for the first communication means.