JPH10301795A - Virtual computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the scalability of a system by performing communication between virtual computers (LPAR) inside the same information processor and performing the communication with a different information processor as well. SOLUTION: Respective operating systems(OSes) 11-13 and a coupling facility(CF) 10 can be independently operated on the respective LPARs by a hypervisor 14. The communication of the OSes 11-13 and the CF 10 is performed through a micro program(μP) 150 in a basic processing unit(BPU) 15. The OS 11 can communicate with the CF 2 of the different information processor through a Sender CH 161 and a Receiver CH 21 and the CF 10 can communicate with the OS 3 of the different processor through the Receiver CH 162 and the Sender CH 32. Inside the BPU 16, the inter-LPAR communication (communication of the OSes 11-13 and the CF 10) and the communication with the different information processor can be simultaneously and parallelly operated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus of a virtual computer system, and more particularly, to communication between OSs on a virtual computer of the same information processing apparatus.

[0002]

2. Description of the Related Art An OS (IBM MV) is used for communication between virtual machines (hereinafter referred to as LPARs) in the same information processing apparatus.
S) and a coupling facility (hereinafter referred to as a CF) regarding a parallel sysplex.

[0003] GA22-7123-11 "Processor Resource / System
Manager Planning Guide (EnterpriseSystem 9000/309
0) ”describes a description of a parallel sysplex between the OS and the CF in the same information processing apparatus.
It provides a mechanism called the ated Coupling Migration Facility (hereinafter referred to as ICMF). The Parallel Sysplex aims to treat transactions distributed among each OS as a single data management system in which a plurality of OSs are connected via a CF. However, ICMF uses an OS and a CF in the same information processing device as a single data management system. It is limited to the Parallel Sysplex, and it is not possible to construct a Parallel SysFlex environment between different information processing devices. ICMF will be described with reference to FIG.

The information processing apparatus 1 includes a plurality of OSs 11 to 1
3. An instruction processor (hereinafter referred to as IP) for processing instructions from the CF 10 and a control program (hereinafter referred to as a high-power controller) 14 is a TC.
A BPU 15 composed of a Tightly Coupled Multi-Processor (MP) and an input / output processing device (hereinafter referred to as an IOP) 16 (IOP) 16 for performing a communication operation of each of the OSs 11 to 13 and the CF 10.
The OP16 includes a channel device. ). In addition, each OS 11 to 13 and CF 10 are high-powered
4 assures independent operation on each LAPR. In FIG. 1, communication between each OS 11 to 13 on LAPR1 / LAPR3 / LPAR4 and CF10 on LPAR2 is as follows.
It is configured using ICMF, and all of the communication is performed by emulation of the high-versus-pulse 14. In the ICMF, the high-validator 14 emulates the communication between the OS and the CF,
Communication is not performed using a channel device (hereinafter referred to as CH) in the IOP 16. In addition, since all the communication between the OS and the CF is once passed to the high-over-hauler 14 (simulation), an over-head of the high-over-hauler 14 occurs.

When the ICMF is used, communication within the same information processing apparatus 1 is possible, but communication with another information processing apparatus is not possible.

FIG. 2 shows an example in which communication within the same information processing apparatus is performed without using ICMF. In FIG. 2, IOP1
6 includes a Sender CH 163 and a Receiver CH 164, and the Sender CH 163 and the Receiver CH 164 are connected by an interface cable 7. Sender CH163 is O
Accessible from S11 to S13, and also Receiver CH1
64 is accessible only from CF11. Therefore LAPR1 / L
OS11-13 on APR3 / LPAR4 and CF1 on LPAR2
Communication between 0 is performed using the Sender CH 163 and the Receiver CH 164. In the case of FIG. 2, since emulation of the high-power decoder 14 is not necessary, no overhead of the high-power transmitter 14 occurs, but the Sender CH 163 and the Receiver CH 16
4 is required. However, L of the same information processing device
The exchange of data in the PAR communication is movement in a memory in the information processing apparatus. Therefore, LPA of the same information processing device
In the inter-R communication, there is no need to use the CH, and the IP should perform the communication.

[0007]

The cost of the user should be reduced by consolidating many LPARs into one high-performance information processing device and reducing the number of information processing devices. from now on,
This tendency will be further strengthened as faster information processing devices appear. The more high-performance information processing devices are provided, the more the parallel plex environment is constructed on one information processing device, and the more cases of LPAR communication within the same information processing device. However, the scalability of the system cannot be improved with a parallel sysplex using only the same information processing device.

[0008] An object of the present invention is to provide an LA broadcast processing apparatus for transmitting broadcast data to an LA.
The scalability of the system is ensured by performing high-speed communication between PRs and enabling communication with another information processing device.

[0009]

[Means for Solving the Problems]

1. Control information required for communication between OSs is stored. A control flag is provided in a communication control block provided in a hardware area in the main storage device.
Means for notifying the instruction processor of the FFs, and means for transmitting to the instruction processor information on the correspondence between the respective communication control blocks of the virtual machines communicating within the same information processing apparatus, the control program comprising: Means for turning on / off the control flag in the control block, means for storing information sent from the control program in the control block, and an instruction processor for performing communication between OSs. If the control flag in the communication control block is ON, it is determined that the virtual machine is in the same information processing apparatus, the virtual machine of the communication destination is obtained by associating the communication control block between the virtual machines, and the OS on the virtual machine is determined. The instruction processor transfers control information and data to the area specified by
Means for notifying the OS on the virtual machine of the arrival of the data; and, if the control flag is OFF, communication between different information processing apparatuses is determined, and the communication destination of the communication destination is determined via the channel device of each information processing apparatus. The instruction processor is provided with means for transferring control information and data to an area designated by the OS on the information processing device and for notifying the OS on the information processing device of the arrival of the control information and data.

[0010] 2. Hardware (instruction processor, channel device,
And the like, and there are asynchronous instructions in which hardware executes processing asynchronously with OS and control program instructions.
It is possible to specify either the synchronous type or the asynchronous type. When the hardware executes the instruction processing in either the synchronous type or the asynchronous type according to the specification, when the control flag is ON, the OS If the command for starting the communication is synchronous, the means when the control flag of claim 1 is ON is executed, but if the instruction is asynchronous, the control flag of claim 1 is OF
Means for executing the means at the time of F are provided in the instruction processor.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.

FIG. 3 shows an outline of the present invention. The information processing apparatus 1 includes a plurality of OSs 11 to 13,
10, a BPU 15 for processing an instruction from a control program (hereinafter referred to as a high-power signal) 14, OS 11 to 13, and a CF 10
The IOP 16 is configured to perform a communication operation and the like. The OSs 11 to 13 and the CF 10 can operate independently on the respective LAPRs by the high-powered lasers 14. OS11-
The communication between the CF 13 and the CF 10 is performed via a microprogram (μP) 150 in the BPU 15. In the BPU 15, each instruction processor (hereinafter, referred to as IP) has a TCMP (Tightly C
Oupled Multi-Processor), and each IP has a built-in control microprogram 150. OS
11 is SenderCH161 and Receiver
It can communicate with CF2 of another information processing device via CH21. CF10 is ReceiverCH162,
OS of another information processing device via SenderCH32
3 is communicable. And CF2 and OS3 are Rec
via eeverCH22, SenderCH31,
Communication is possible. Communication between LPARs within the BPU 15 (OS
11-13 and communication with the CF 10) and communication with another information processing apparatus (communication between the OS 11 and the CF 2 or communication between the CF 10 and the OS 10).
3) can operate simultaneously and in parallel. The details will be described below.

FIG. 4 is a communication control block in FIG.
(Sub-channel, channel correspondence list, etc.), detailed description of each unit, LPAR, IP
, A sub-channel (hereinafter called SBCH), and a Sende
It shows the correspondence between rCH / ReceiverCH. In FIG. 4, the BPU 15 has I
PA151 / IPB152 / IPC153 / IPD15
4 and each IP constitutes the BPU 15 by TCMP. The information processing device 1 has a main storage device (hereinafter referred to as M
S 17). The MS 17 has a hardware system area (hereinafter, referred to as HSA) 171 that is accessed only by hardware (IP, IOP, etc.) in addition to the space used by the program. The HSA 171 contains an OS
SBCH storing SBCHs 1721 to 1726 used when the CF 10 communicates with other OSs and CFs.
There are a storage area 172, a channel correspondence list 173, and a sub-channel table 174. Also, the IOP 16 includes the SenderCH 161 described in FIG.
In addition to the verCH 162, the SenderCH 163 for performing communication between the OSs 11 to 13 and the CF 10 and the Receiver
erCH164. Operators and each harness
Hardware units (Hypervisor 14, IPA1
51 / IPB152 / IPC153 / IPD154, I
OP16) To exchange with Service Processor
(Hereinafter referred to as SVP) 18 is provided in the information processing apparatus 1. In addition to the IP, a microprogram is built in the IOP 16 (including the CH) and the SVP 18 for controlling the unit.

The OS 11 of the LPAR 1 has an IP
PA 151 is assigned and S for communication with CF 2
SBCH for communication between BCH # 1 1721 and CF10
# 21722 is assigned. OS1 of LPAR3
2 is assigned IPC 153 as IP and SBCH # 5 1725 for communication with CF 10. In the OS 13 of the LPAR4, the IP
D154 is assigned and S for communication with CF10.
BCH # 6 1726 is allocated. And L
An IPB 152 is assigned to the CF 10 of the PAR 2 as an IP, and an SBCH for communication with the OSs 11 to 13 is provided.
# 3 1723 and SBCH # 41 for communication with OS3
724 are assigned. Each SBCH is Send
erCH161 / 16, ReceiverCH162
/ 163. This correspondence is in HSA171
Stored in sub-channel table 174 (shown in FIG. 9). In FIG. 9, 256 entries having a 4-byte width are held for each channel device (hereinafter, referred to as CH), and the SBCH number corresponding to the CH is stored in each entry. Whether the entry is valid is determined by the V-bit in the flag in the entry. (If V = 1, the entry is valid; if V = 0, the entry is invalid.) In order to obtain the area of the CH, the sub-channel table pointer indicating the relative address from the head of the HSA 171 has a CH number × 256. × 4 is determined. Therefore, the area of the sub-channel table 174 for the SenderCH 163 has the SBCH # 2 1722 /
Three entries of SBCH # 5 1725 / SBCH # 61726 are included, and only the V of the flag of the entry is 1, and the V of the flags of the other entries related to SenderCH163 is 0. Send in the same way
SBCH # 1 1721 is stored in the area of the sub-channel table 174 for the erCH 161.
SBCH # 4 1724 is stored in the area of the subchannel table 174 for the verCH 162,
SBCH # 3 1723 is stored in the area of the subchannel table 174 for the averCH 164. This relationship holds both when LPAR communication is performed and when LPAR communication is not performed within the same information processing apparatus, and this information is determined when the configuration of the system is defined.

When performing inter-LPAR communication, it is necessary to define LPARs that communicate with each other. The designation of the LPAR for communication is instructed from the operator to the hypervisor 14 via the SVP 18. An existing means is used for the interface between the SVP 18 and the hypervisor 14, but a new setting screen is required for that. However, since this case is out of the scope of the present invention, a detailed description is omitted.

The operator specifies, via the SVP 18, a pair of channels for performing LPAR communication. In the example of FIG. 4, SenderCH 163 and Receiver
Specify CH164. A pair for performing inter-LPAR communication with the hypervisor 14 via the SVP 18 (SenderC
H163 and ReceiverCH164), the hypervisor 14 assigns it to any one IP15.
1 to 154. Normally from the hypervisor 14,
Instructions for the IPs 151 to 154 use hypervisor-specific instructions (hereinafter referred to as HVA instructions) in addition to the instructions used by the OS. The HVA instruction for that uses an instruction code not used by the OS. When defining the communication between LPARs, the HVA command is newly added. With the added HVA instruction, the hypervisor 14 sets a pair for performing LPAR-to-LPAR communication to any one of the IPs 151 to 151.
Instruct 154. The added HVA instruction is issued for each CH, and three operands are added to the operand of the instruction.

The respective operands will be described below.

Operand 1 is a CH number of a CH to which the HVA instruction is applied.

Operand 2: The CH number of the CH paired with the CH specified by operand 1. This operand has no meaning if the control flag indicated by operand 3 is 0.

Operand 3: Operand 1 specified C
H is a control flag indicating whether or not to perform inter-LPAR communication. If this control flag is 1, it indicates that communication between LPARs is performed, and if it is 0, it indicates that communication between LPARs is not performed.

From the hypervisor 14, the added H
In response to the VA instruction, the IP that has received the instruction registers the operand information of the HVA instruction in the channel correspondence list 173 in the HSA 171. The format of the channel correspondence list 173 is described in FIG. In FIG. 8, 8
An entry having a byte width is prepared, and the corresponding CH # of each entry is provided.
The area stores the CH number of the CH that is paired with the CH. The flag of the entry includes a V bit indicating validity / invalidity of the entry and a C bit indicating whether the CH corresponding to the entry performs inter-LPAR communication. When the IP receives an HVA instruction added for performing inter-LPAR communication from the hypervisor 14, the entry of the channel correspondence list 173 corresponding to the CH specified by operand 1 of the instruction is updated. In addition, in order to obtain the entry of the CH in the channel association list 173, the channel number is obtained by adding the CH number × 8 to the channel association list pointer indicating the relative address from the head of the HSA 171. In the example of FIG.
163 and ReceiverCH 164 form a pair. First, the hypervisor 14 issues the operand 1 of the HVA instruction to the IP with the CH number of the SenderCH 163, the operand 2 with the CH number of the ReceiverCH 164, and the control flag of the operand 3 as 1. Therefore, the IP sets the V of the flag of the entry of the channel correspondence list 173 corresponding to the SenderCH 163 to 1, reflects the value of the control flag of the operand 3 on the C bit (1 in this example), and #
ReceiverC specified by operand 2 in the area
The number corresponding to H164 is stored.

Similarly, the hypervisor 14 converts the operand 1 of the HVA instruction into the CH of the receiver CH 164.
Number and operand 2 is the C of SenderCH163.
An H number is issued, and the control flag of operand 3 is set to 1 and issued to the IP. Therefore, the IP is Receiver
The V of the flag of the entry of the channel correspondence list 173 corresponding to the CH 164 is set to 1, the value of the control flag of the operand 3 is reflected in the C bit (1 in this example), and the corresponding CH # area of the entry corresponds to the Sender CH 163. Store the number to be used. As described above, the association of the communication control blocks for performing the inter-LAPR communication is completed.

In the added HVA instruction, the C bit of the entry in the channel correspondence list 173 can be dynamically set to 0 or 1 by the control flag of the operand 3.

FIG. 5 shows the format of the SBCH. Hereinafter, each area of the SBCH will be described.

LOCK When the SBCH is updated, a value other than 0 is always set. If the area is other than 0, each IP 151-154,
IOP16 (SenderCH, Receive under IOP)
The same applies to “overCH”), the SBCH cannot be updated. The code stored in the LOCK area is
(IP, IOP, CH, etc.) are uniquely determined.

Information storage address area When the OS and the CF perform a communication operation, an address for storing request information, data (data to be transmitted and data to be received), and response information accompanying the communication is stored. From the information storage address, request information, response information, and data (data to be transmitted and data to be received) are stored in this order, and the request information and the response information have a fixed length. Therefore, by knowing the information storage address, each address of request information, data (data to be transmitted and data to be received), and response information can be obtained. A valid value must always be stored in the information storage address area. This value must be set at the time of initial program loading of each OS and each CF.

SBCH status flag (hereinafter referred to as SCSW) Details of the flag are shown in FIG. The flag has a P bit and an X bit. The P bit is a flag indicating communication function pending, and when this bit is 1, the OS or C
It is set to 1 when the communication start / response is started from F, and set to 0 when the start operation is completed. The X bit is a bit indicating a status pending.
It is set to 1 when there is a request to the OS or CF assigned to the OS or when there is an abnormality in the communication operation, and is set to 0 by the OS or CF that has detected the state.

Control Flag The control flag has an I bit and an R bit. The I bit designates the SBCH, and when the OS or CF activates communication / response activation, if this bit is 1, the IP directly processes without passing through the hypervisor 14 (this is executed directly). If the I bit is 0, the processing is passed to the hypervisor 14, and the hypervisor 14 performs a simulation operation of the instruction. The I bit is set to 1 or 0 by the hypervisor 14. The R bit indicates whether the SBCH is an SBCH assigned to a SenderCH or an SBCH assigned to a ReceiverCH. That is, the SBC
If H = 1, it is the SBCH for ReceiverCH, and if R = 0, it is the SBCH for SenderCH.

LPAR Number The LPAR number to which the SBCH is allocated is stored.

SBCH Number Stores the number of the SBCH that uniquely classifies the SBCH.

Connection CH number group Stores the number of the CH corresponding to the SBCH. Up to eight can be stored.

Corresponding SBCH Number When performing LPAR-to-LPAR communication, the SBCH corresponding to the SBCH
The number of the CH is stored. In FIG. 4, SBCH # 2
1722 / SBCH # 5 1725 / SBCH # 6 1
726 and SBCH # 3 1723 are in a correspondence relationship.
Therefore, in the corresponding SBCH number area of SBCH # 31723, SBCH # 2 1722 / SBCH # 5 1725 /
One of the SBCH numbers of SBCH # 61726 may be stored.

The case where communication is performed from the OS 11 of the LPAR 1 to the CF 10 of the LPAR 2 will be described with reference to FIGS. 4, 10 and 11 in the following steps 1 to 5. FIG. 10 shows C
FIG. 11 shows an example in which H is used, and FIG. 11 shows an example in which IP is used. FIG. 10 shows LPs in the same information processing apparatus.
Although the case where inter-AR communication is performed on the CH is described, the operation shown in FIG. 14 is also performed for communication between different information processing devices.

Step 1: From OS 11 to IPA 151 startup This step is common to FIGS. 10 and 11.

The OS 11 of the LPAR 1 issues SBCH # 2 1722 when issuing a communication start to the CF 11. (Before the issuance, the request information and the data (OS 11) are stored in the area indicated by the information storage address of SBCH # 2 1722.
) Is stored in the CF 10 from the user. In this example, it is assumed that the I bit of the control flag in the SBCH # 2 1722 is 1, and therefore, the communication activation is directly performed by the IP without passing through the hypervisor 14. LPAR1
IPA 151 assigned to OS 11 is SBC
The P bit of the SCSW of H # 2 1722 is updated to 1. Thereafter, from the connection CH number group area in the SBCH # 2 1722, a CH connected to the SBCH is obtained. Thereby, IPA 151 obtains SenderCH 163 as the CH connected to SBCH # 2. Then, according to the channel correspondence list 173, Sen
An entry for derCH 163 is determined. The same applies to FIG. 10 (communication using CH) and FIG. 11 (communication using IP) up to the point where the C bit of the flag of the obtained entry is determined.

Step 2: Step 1 to SBCH # 3
Until X of SCSW becomes 1 (case of FIG. 10) If the C bit is 0, C
H (FIG. 10).

IPA 15 which has determined that the C bit is 0
1 is Sen connected to SBCH # 2 1722
SBCH of SBCH # 2 1722 on derCH 163
Start notification including the number. And then, IPA
151 indicates that the SCSW of SBCH # 2 1722 has P = 0,
Or wait until X = 1. Se that received the start notification
nderCH 163 is the SBC taught with the notification.
The information storage address in the SBCH is read by the H number (SBCH # 2 1722). Then, the request information and data (from the OS 11 to C
If it is determined that data is to be sent to F10, the data is already stored in the data area. ) And send it to Sen
The data is sent to ReceiverCH 164 connected to derCH 163 via interface cable 7. And S
The ender 163 waits for a response from the receiver CH 164. RequestC sent from SenderCH163, ReceiverC that received the data
H164 stores request information and data sent to the area indicated by the information storage address of the SBCH (SBCH # 3 1723 in this example) allocated to ReceiverCH 164. After that, ReceiverC
H164 sets the X bit of SCSW of SBCH # 3 1723 to 1. Then, it waits for a response activation from the CF 10.

In addition, SenderCH163, Recei
Each of the CHs such as verCH164 is the SBCH assigned to the CH when the initial microprogram is loaded.
The number is obtained from a sub-channel table in the information processing apparatus.

(Case in FIG. 11) If the C bit is 1, communication by IP (FIG. 11) is performed.

IPA 15 that has determined that the C bit is 1
1 is Sen obtained from the channel correspondence list 173.
According to the corresponding CH # stored in the entry for derCH163, the connection destination is ReceiverCH16.
We know that it is 4. And the sub-channel table 174
From the SBC connected to ReceiverCH 164
Find H.

As a result, SBCH # 3 is obtained. At this time, the SCSW of SBCH # 3 1723 is checked.
(Because the SBCH # 3 1723 can correspond to the SBCH # 5 1725 / SBCH # 6 1726 in addition to the SBCH # 2 1722, the SCS of the SBCH # 3 1723 is
The IP needs to check W. ) If the SBC
If H is not IDLE (not all '0'), the Re
It is determined from the sub-channel table 174 whether there is any other SBCH connected to the receiverCH 164, and if so, the SCSW of the determined SBCH is checked. Rec
All the SBCHs connected to the overheadCH 164 are I
If not DLE, connection C in SBCH # 2 1722
Check if there is another valid CH in the H number. In this example, there is only one CH, but if there is, for that CH, the CH of the connection destination is obtained from the channel correspondence list 173, and the SBCH under the CH is obtained from the sub-channel table 174 from the obtained CH. As a result of performing such an operation, all SBs corresponding to SBCH # 2 1722
If the SCSW of the CH is not IDLE, SBCH # 2
At 1722, X is set to 1 while P of the SCSW remains 1, and the communication activation is terminated. The SBCH (SBCH # 3 1723 in this example) corresponding to SBCH # 2 1722 has the ID
If it is LE, the following is performed. IPA151 is SBC
Read the information storage address in H # 2. Then, the request information and data (the OS 1
If it is determined that the data is to be transmitted from 1 to the CF 10, the data is already stored in the data area. ) And SB
The request information and data are stored in the area indicated by the information storage address of CH # 3 1723. After that, IPA15
1 stores the SBCH number of SBCH # 2 1722 in the corresponding SBCH number area of SBCH # 3 1723,
The X bit of the SCSW of BCH # 3 1723 is set to 1. After that, the IPA 151 sets the SBCH # 2 1722 S
Wait until CSW becomes P = 0 or X = 1.

Step 3: The response activation from step 2 is I
This step is performed until the PB 152 receives the response activation.
0 and FIG.

CF10 is a subordinate ReceiverCH.
(In this example, the SCSWs of all SBCHs connected to the ReceiverCHs 162 and 164 (in this example, SBCH # 3 1
723 / SBCH # 4 1724). In step 2, since the X bit of SBCH # 3 1723 has become 1, it is known that a factor for processing the SBCH has occurred. Thereafter, CF10 sets S
The X bit of BCH # 3 1723 is set to 0, and SBCH # 3
The request information and data (when it is determined that data has been received from the request information) stored in step 2 at the information storage address of No. 3 1723 are processed, and the CF 10 processes the SBCH # 31.
The storage address of the response information is obtained from the information storage address of 723, and the response information is written there. (When data is sent from the request information from the CF 10 to the OS 11, the data is also stored.) Then, the IPB assigned to the CF 10
152, a response start is issued by indicating SBCH # 3 1723. In this example, it is assumed that the I bit of the control flag in the SBCH # 3 1723 is 1, and therefore, the response activation is performed directly by the IP without passing through the hypervisor 14. The IPB 152 that has issued the response activation is the SBCH
# 3 The P of the SCSW of 1723 is set to 1. And S
Resei from the connection CH number in BCH # 3 1723
Then, an entry related to the ReceiverCH 164 is obtained from the channel correspondence list 173. In this entry, if the flag C is 0, C
Communication by H (FIG. 10), and if the C bit is 1, communication by IP (FIG. 11).

Step 4: SBCH # 2 from step 3
Until the SCSW P = 0 becomes the case (the case of FIG. 10).
Ask for an entry for the everCH164. In this entry, if the flag C is 0, the IPB 152
Is connected to SBCH # 3 1723
A start notification is performed to the rCH 164 including the SBCH number of the SBCH # 3 1723, and the receiver CH 16
From 4, wait for the end of the activation. The ReceiverCH 164 that has received the activation notification from the IPB 152 is the SBCH # 3
1723 is read, and response information and data (CF10 to OS
When there is data to be sent to 11. The presence or absence is indicated in the response information. ) Is read out, and ReceiverCH164
Senn connected to the interface cable 7
Send to derCH163. Then, an end report is sent to the IPB 152. The IPB 152 that has been waiting for the end report from the ReceiverCH 164 updates P of the SCSW of the SBCH # 31723 to 0, and then returns a condition code (CC) in response to the response activation from the CF10. And Res
The SenderCH 163 that has received the response information and the data from the receiverCH 164 writes the response information and the data sent from the ReceiverCH 164 to the information storage address in the SBCH # 2 1722. Then, S
endCH163 is S of SBCH # 2 1722.
Set P of CSW to 0.

(Case of FIG. 11) The IPB 152 obtains from the channel correspondence list 173,
Ask for an entry for In this entry, if the flag C is 1, the IPB 152 sets SBCH # 3 17
23 (in this example, IPA1
51 stores the number of SBCH # 2 1722)
Is read. And IPB 152 is SBCH # 3 17
The response information and data included in the information storage address of No. 23 are stored in the storage location of the response information and data indicated by the information storage address of SBCH # 2 1722. And IP
B152 sets the SCSW P of SBCH # 3 1723 to 0.
And set the SCSW P of SBCH # 2 1722 to 0.
To After that, the IPB 152 returns a condition code (CC) in response to activation of a response from the CF 10.

Step 5: From Step 4 to End Report from OS 11 This step is common to both FIGS. 10 and 11.

The IPA 151 that has been waiting until the SCSW P of the SBCH # 2 1722 becomes 0 becomes “0” in step 4 because the P of the SCSW of the SBCH # 2 1722 becomes 0. Responds with a condition code (CC).

By the above steps 1 to 5,
From the C bit set in the corresponding entry of the channel correspondence list, communication between LPARs by IP or CH
Can be used for communication. Also, the channel correspondence list 173
However, even if the C bit set in the corresponding entry is 1, the same operation as C = 0 can be performed depending on the situation. For example, the communication activation issued from the OS 11 ends asynchronously as seen from the program (the actual processing is being executed even if the end condition code is returned to the program.
SM described in 4490 "Data Processing System"
The SG instruction can specify whether the hardware starts the communication synchronously or asynchronously. ) If it was a communication start,
The same processing as C = 0 may be performed.

Communication between the OSs 11 to 13 in the information processing apparatus 1 and the CF 2 in another information processing apparatus, and communication between the CF 10 in the information processing apparatus 1 and the OS 3 of another information processing apparatus are performed by Sender CH 161 used for communication. 31, 32 / Re
Since the C bits of the flags of the entries in the channel correspondence list corresponding to the receiverCHs 162, 21, and 22 are all 0, the operation is the same as the example shown in FIG.
In the above example, the communication from the OS 11 to the CF 10 is performed. However, when the communication is considered in reverse, the communication from the CF 11 to the OS 10 is also possible.

As described above, in the present embodiment, it is possible for the IP to perform inter-LPAR communication without passing through the CH and to perform communication via the CH, and to set the C bit of the channel correspondence list to 0. By setting to 1 or 1, it is possible to dynamically control whether to perform communication between LPARs by IP or communication by CH.

[0051]

According to the present invention, LA on the same broadcast processing device
Since communication between PRs is performed at high speed and communication with other information processing devices is enabled, scalability of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional method (in the case of using emulation of a high-powered laser).

FIG. 2 is a diagram showing a conventional method (when a channel is used).

FIG. 3 is a diagram showing an outline of the present invention.

FIG. 4 is a diagram showing the correspondence between LPAR, IP, SBCH, and CH.

FIG. 5 is a diagram showing a format of a subchannel (SBCH).

FIG. 6 is a diagram showing an SBCH status flag (SCSW).

FIG. 7 is a diagram showing a control flag in the SBCH.

FIG. 8 is a diagram showing a channel correspondence list.

FIG. 9 is a diagram showing a sub-channel table.

FIG. 10 is a diagram illustrating an example of inter-LPAR communication using a channel.

FIG. 11 is a diagram illustrating an example of inter-LPAR communication according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 10 CF (Coupling Facility) 11-13 OS (Operating System) 14 Hypervisor 15 BPU (Basic Processing Unit) 150 IP microprogram (μP) 151 IPA (Instruction Processor) 152 IPB (Instruction Processor) Instruction processor) 153 IPC (Instruction Processor) 154 IPD (Instruction Processor) 16 IOP (Input / Output Processor) 161/163 SenderCH 162/164 ReceiverCH 17 Main memory 171 HSA (Hardware System Area) 17 Sub-channel storage area 1721 to 1726 Sub-channel (SBCH) 173 Channel correspondence list 174 Sub-channel table 18 SVP (SerVice Processor) 2 CF of another information processing device 21/22 ReceiverCH 3 OS of the information processing apparatus 31/32 SenderCH 4/5/6/7 interface cable

Claims (2)

[Claims] An operating system (hereinafter referred to as an OS) operating on a virtual machine, a plurality of instruction processors for processing instructions of a control program for controlling the operation of a plurality of virtual machines, and a plurality of communication processors for performing communication processing between the OSs. In an information processing apparatus including a channel device and a main storage device, control information required for communication between OSs is stored, and a control flag is provided in a communication control block provided in a hardware area in the main storage device. A means for notifying the instruction processor of ON / OFF of the control flag and a means for transmitting to the instruction processor information on the correspondence between the respective communication control blocks of the virtual machines communicating within the same information processing apparatus are provided in the control program. The control flag in the control block is turned on by the notification by the control program.
/ OFF means, means for storing information sent from the control program in the control block, and when performing communication between OSs, the instruction processor determines if the control flag in the communication control block is ON. It is determined that the virtual machine is in the same information processing apparatus, a virtual machine of the communication destination is obtained by associating the communication control blocks between the virtual machines, and the instruction processor executes control information and data for an area designated by the OS on the virtual machine. And a means for notifying the OS on the virtual machine of the arrival of the control information and data. If the control flag is OFF, it is determined that communication between different information processing apparatuses is performed. The control information and data are transferred to an area designated by the OS on the information processing device of the communication destination via the channel device, and the arrival of the control information and data is transmitted to the area specified by the OS. Virtual computer system is characterized by providing a means for notifying the OS on the processor, the instruction processor. 2. In synchronization with an instruction of an OS or a control program,
There are a synchronous instruction that the hardware (instruction processor, channel device, etc.) executes the processing, and an asynchronous instruction that the hardware executes the processing asynchronously with the instruction of the OS or the control program. 2. The information processing system according to claim 1, wherein any one of a synchronous type and an asynchronous type can be designated, and the hardware executes the processing of the instruction in one of a synchronous type and an asynchronous type according to the designation. When the control flag of the control block is ON, if the instruction for activating communication between OSs is a synchronous type, the means when the control flag is ON of claim 1 is executed. 2. A virtual computer system, comprising: a means for executing the means when the control flag is OFF according to claim 1 provided in an instruction processor.