JPS59112635A - Manufacture of ceramic package for semiconductor device - Google Patents
Manufacture of ceramic package for semiconductor deviceInfo
- Publication number
- JPS59112635A JPS59112635A JP22247682A JP22247682A JPS59112635A JP S59112635 A JPS59112635 A JP S59112635A JP 22247682 A JP22247682 A JP 22247682A JP 22247682 A JP22247682 A JP 22247682A JP S59112635 A JPS59112635 A JP S59112635A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- melting point
- internal
- crystallized
- internal leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000011521 glass Substances 0.000 claims abstract description 62
- 238000002844 melting Methods 0.000 claims abstract description 34
- 230000008018 melting Effects 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 18
- 238000007789 sealing Methods 0.000 abstract description 13
- 239000011230 binding agent Substances 0.000 abstract description 8
- 239000002904 solvent Substances 0.000 abstract description 8
- 238000006073 displacement reaction Methods 0.000 abstract description 5
- 239000000843 powder Substances 0.000 abstract description 3
- 238000002425 crystallisation Methods 0.000 abstract 1
- 230000008025 crystallization Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 230000007547 defect Effects 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は低融点ガラス封止型半導体装置用土ラミックパ
ッケージの製造方法に関し、一層詳細には半導体素子を
収容するセラミックベース面上に低融点ガラスを用いて
り−°ドフレームの内部リードを変形や位置ずれなく固
着しうる半導体装置用セラミックパッケージの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a low-melting point glass-sealed ceramic package for a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a ceramic package for a semiconductor device sealed with a low-melting point glass, and more specifically, a low-melting point glass is used on a ceramic base surface that houses a semiconductor element. The present invention relates to a method of manufacturing a ceramic package for a semiconductor device in which the internal leads of a frame can be fixed without deformation or displacement.
近年これら半導体装置の機能の多様化に伴い集積度が著
しく高まり、半導体素子と電気的導通をとる内部リード
の本数が増大している。In recent years, with the diversification of functions of these semiconductor devices, the degree of integration has increased significantly, and the number of internal leads that establish electrical continuity with semiconductor elements has increased.
一方、半導体素子はますます小型化する傾向が強いから
、結局素子周辺の内部リードは極めて密となり、少しの
変形や位置ずれでも、リードが接触してリード間の絶縁
不良を起こしたり、自動のワイヤボンダーを用いる上で
障害となっている。On the other hand, as semiconductor devices tend to become smaller and smaller, the internal leads around the device end up becoming extremely dense, and even the slightest deformation or misalignment can cause leads to come into contact, resulting in poor insulation between the leads and automatic malfunctions. This is an obstacle to using a wire bonder.
このため、内部リード先端が変形や位置ずれなく固着さ
れているとともに、素子材は工程や気密封止工程で加熱
されても内部リードに変形や位置ずれが生しることのな
い半導体装置用セラミックパッケージが要望されている
。For this reason, the tips of the internal leads are fixed without deformation or misalignment, and the element material is a ceramic for semiconductor devices that does not cause deformation or misalignment of the internal leads even when heated during the process or hermetic sealing process. package is requested.
しかしながら従来においては、後記するようにリードフ
レーム自体の有する欠陥に起因して、内部リードを変形
や位置ずれなく固着することは困難であった。However, in the past, it has been difficult to fix the internal leads without deformation or positional displacement due to defects in the lead frame itself, as will be described later.
すなわち、この種の半導体装置用セラミックパッケージ
に用いられるリードフレームは、アルミクラツド材やア
ルミ蒸着材などが用いられ、主としてプレス加工により
形状形成されているが、母材自体の残留歪に加えて前記
アルミクラツド材の場合にはアルミニウム箔を圧着する
なとの製造履歴、を経ることから、アルミ蒸着材なとに
比してその製造工程に起因する残留歪を多く帯有してお
り、また上記残留歪に加えてプレス加工での抜き２曲げ
、平押しなどによる加工歪が生じ、加工後の内部リード
先端にこれらの内部残留歪が開放され、内部リート先端
にゆがみ５才反れ、そりなどの変形や位置ずれが生じる
現象によって内部リートの位置精度の優れたリードフレ
ームが得られていないのが現状である。In other words, lead frames used in this type of ceramic package for semiconductor devices are made of aluminum clad material or aluminum evaporated material, and are shaped mainly by press working, but in addition to residual strain in the base material itself, the aluminum clad material In the case of aluminum foil, it has a manufacturing history that prohibits crimping aluminum foil, so it has more residual strain due to the manufacturing process than aluminum vapor-deposited materials, and the residual strain mentioned above In addition, processing distortion occurs due to punching, bending, flat pressing, etc. during press processing, and these internal residual strains are released at the tip of the internal lead after processing, causing deformation such as distortion, warping, and warping at the tip of the internal lead. At present, a lead frame with excellent positional accuracy of internal leads cannot be obtained due to the phenomenon of positional deviation.
これらの内部残留歪を容認したまま、内部リードを位置
決め精度よく固着するものとして、第１図に示すごとく
、セラミックベース１の上面に凸部２を設けておき、こ
の凸部２上にリードフレームの内部リード３先端をつき
当てて、この状態で低融点カラス４で固着するものがあ
る。し、かじながら上記従来例によるときは、後の素子
付は工程や、低融点ガラス５を用いてキャンプ６により
気密封止する際に再度加熱されて内部リート３を固着し
ている低融点ガラス４がその都度軟化し、この軟化によ
りそれまで抑えられていた前述の内部残留歪が内部リー
ド３に開放され、前述のごとく内部リード３の変形や位
置ずれが生じ、ワイヤボンディング時の障害やリード間
の接触による絶縁不良なとが招来されている。In order to fix the internal leads with high positioning accuracy while accepting these internal residual strains, a protrusion 2 is provided on the upper surface of the ceramic base 1 as shown in Fig. 1, and a lead frame is mounted on the protrusion 2. There is one in which the tip of the internal lead 3 is abutted and in this state it is fixed with the low melting point glass 4. However, when using the above conventional example, the later attachment of the element is done in a process, and when the low melting point glass 5 is used for airtight sealing with the camp 6, the low melting point glass is heated again and fixes the internal reed 3. 4 softens each time, and due to this softening, the aforementioned internal residual strain that had been suppressed until then is released to the internal lead 3, causing deformation and positional shift of the internal lead 3 as described above, resulting in failure during wire bonding and lead damage. This leads to poor insulation due to contact between the two.
また第２図に示すように、リードフレームの形状加工の
段階で内部リード３の先端をつなげる連結片７を残して
、この連結片７によって前述の内部残留歪を抑えたまま
低融点ガラス４て内部り−１３を固着し、しかる後に連
結片７をもぎ取るようにしたものが知られている。Furthermore, as shown in FIG. 2, a connecting piece 7 that connects the tips of the internal leads 3 is left at the stage of shaping the lead frame, and this connecting piece 7 allows the low melting point glass 4 to be connected while suppressing the internal residual strain described above. It is known that the inner part 13 is fixed and the connecting piece 7 is then peeled off.
しかしながらこの方法によるときも、前記従来例と同様
に素子付は工程や、低融点カラス５を用いてキャップ６
により気密封止する際に内部り−ド３を固着している低
融点ガラス４が軟化し、前述同様の欠陥が生ずるほか、
前記連結片７をもぎ取る際に低融点ガラス４にクランク
を生じさせる難点かある。However, even when this method is used, the attachment of the element is done in a process similar to the conventional example, and the cap 6 is attached using the low melting point glass 5.
During hermetic sealing, the low melting point glass 4 that fixes the internal wire 3 becomes soft, causing the same defects as mentioned above.
There is a problem in that when the connecting piece 7 is torn off, the low melting point glass 4 is caused to crack.
発明昔は上記のように、素子付は工程や、低融点カラス
を用いてキャップにより気密封止する際に、内部リード
−を固着している低融点ガラスが軟化する結果種々の弊
害が招来されることに鑑み、鋭意検討を重ねた結果、内
部リードを固着する低融点ガラスとして、結晶化して固
化した後は融点が上昇する結晶化ガラスを用い、結晶化
して同化プ゛ることによって内部リードを固着すること
により、上記の素子付は工程やキャップの気密封止の際
にも軟化せず、内部リードを変形や位置ずれなく固着し
うろことに想到した。In the past, as mentioned above, the process of attaching an element was difficult, and when low-melting glass was used to hermetically seal it with a cap, the low-melting glass that fixed the internal leads would soften, resulting in various problems. In view of this, after careful consideration, we decided to use crystallized glass, which has a higher melting point after crystallizing and solidifying, as a low-melting glass to fix the internal leads, and by crystallizing and assimilating the internal leads. By fixing the cap, the above-mentioned element attachment will not soften during the process or hermetic sealing of the cap, and the internal leads will be fixed without deformation or displacement.
従来においても内部リードを固着するものとして結晶化
ガラスを用いるものがあるが、内部ＩＪ−１・を固着す
る段階では結晶化し固化する温度・までは加熱せず、ギ
ャップにより最終的に気密封止する際に初めて結晶化し
固化させている。Conventionally, crystallized glass has been used to fix internal leads, but at the stage of fixing the internal IJ-1, it is not heated to the temperature at which it crystallizes and solidifies, and the final hermetic seal is created using a gap. It is only during this process that it crystallizes and solidifies.
これは、結晶化し固化した結晶化ガラスと結晶化し固化
する温度まで加熱していない結晶化ガラス又は非結晶化
カラスを重ね合せて加熱してもなじみが悪く、気密封止
特性や接合強度が所要の特性を満足させることができな
いとされてきたためである。This means that even if you stack and heat crystallized glass ceramics that have crystallized and solidified and crystallized glass that has not been heated to the temperature that crystallizes and solidifies them and heat them, they will not blend well, and airtight sealing properties and bonding strength are required. This is because it has been considered that it is not possible to satisfy the characteristics of
しかしながら結晶化した結晶化カラスと、非結晶化ガラ
スまたは結晶化ガラスでも結晶化し固化させていないガ
ラスとの組合せによる溶着は、双方の低融点ガラスさえ
結晶化させていなければその接合強度において何ら問題
かなく、また気密封止特性においても従来と遜色がない
ことが確認された。However, when welding a combination of crystallized glass and amorphous glass or crystallized glass that has not been crystallized and solidified, there will be no problem in the bonding strength unless both low-melting glasses are crystallized. It was also confirmed that the hermetic sealing properties were comparable to conventional products.
すなわち本発明の目的とするところは、素子付は工程や
気密封止する際に加熱してもリードフレームの内部リー
ドを変形や位置ずれを生ずることなく固着することので
きる、半導体素子を収容するセラミックベース面上に低
融点カラスを用いてリードフレームの内部リードを固着
する低融点ガラス封止型半導体装置用セラミックパッケ
ージの製造方法において、前記内部リードを固着する低
融点ガラスに融解した後結晶化して固化する結晶化カラ
スを用い、内部リードを位置決めして前記結晶化カラス
を結晶化して固化することにより前記セラミックベース
面上に固着することを特徴とする半導体装置用セラミッ
クパッケージの製造方法を提供するにある。In other words, the object of the present invention is to house a semiconductor element in which the internal leads of the lead frame can be fixed without deforming or shifting the position even if heated during the process or hermetic sealing. In a method for manufacturing a ceramic package for a semiconductor device sealed in low melting point glass, in which internal leads of a lead frame are fixed on a ceramic base surface using low melting point glass, the internal leads are melted into the low melting point glass and then crystallized. Provided is a method for manufacturing a ceramic package for a semiconductor device, characterized in that the ceramic package is fixed on the ceramic base surface by positioning the internal leads and crystallizing and solidifying the crystallized glass. There is something to do.
、以下本発明の好適な実施例を添付図面を参照して詳細
に説明する。Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第３図は、本発明方法によって製造したセラミックパッ
ケージを用いた半導体装置の一例を示す。FIG. 3 shows an example of a semiconductor device using a ceramic package manufactured by the method of the present invention.
図において］０はセラミックベースであり、素子１１を
収容している。１２はリードフレームでアリ、その内部
リード１３はセラミックベース１゜のベース面上に結晶
化ガラス１４によって固着され、ワイヤ１５によって素
子１１と電気的に導通している。１６はキャップであり
、低融点ガラス１７によってセラミックベース内に収容
し、た半導体素子が気密封止されている。In the figure] 0 is a ceramic base that houses the element 11. Reference numeral 12 denotes a lead frame, the internal leads 13 of which are fixed on the base surface of the ceramic base 1° with crystallized glass 14, and are electrically connected to the element 11 through wires 15. Reference numeral 16 denotes a cap, in which a semiconductor element housed within the ceramic base is hermetically sealed with a low melting point glass 17.
以下に製造方法を示す。The manufacturing method is shown below.
まずセラミックベース１０の上面に、低温で融解しつる
結晶化ガラス粉末に適宜な有機バインダー、溶剤を添加
してペースト状にしたものをスクリーン印刷等により塗
布する。次いで８０″Ｃ〜１５０°Ｃに加熱して溶剤を
揮散させ、約３００℃に加熱して有機バインダーを飛ば
し、結晶化する温度２時間以下で加熱しグレーズした後
、別途プレス加工により所定形状に形状加工した単位リ
ードフレーム１２を、その内部リード１３部が前記塗布
した結晶化ガラス１４面上にくるように載せ、約４５０
゛Ｃに加熱して結晶化ガラス１４を融解させ、前記した
内部残留歪による変形や位置ずれが生じないように、適
宜治具などによって位置決めした状態で結晶化し固化さ
せて内部リード１３をベース面上に精度よく固着する。First, a paste made by adding an appropriate organic binder and solvent to crystallized glass powder that melts at a low temperature and vines is applied onto the upper surface of the ceramic base 10 by screen printing or the like. Next, heat to 80"C to 150°C to volatilize the solvent, heat to about 300°C to evaporate the organic binder, heat to crystallize temperature for 2 hours or less to glaze, and then press separately to form a predetermined shape. The shaped unit lead frame 12 is mounted so that its internal leads 13 are on the surface of the coated crystallized glass 14, and the
The crystallized glass 14 is melted by heating to ゛C, and the internal leads 13 are crystallized and solidified while being properly positioned using a jig or the like to prevent deformation or misalignment due to the internal residual strain described above. Adheres to the top with precision.
結晶化し固化した結晶化ガラス１４は結晶化したため融
点は初期の融解時よりも高くなり、前述の４５０℃程度
では融解されない状態となる。Since the crystallized and solidified crystallized glass 14 has been crystallized, its melting point is higher than that at the initial melting point, and it is not melted at the above-mentioned temperature of about 450°C.
結晶化ガラス１４としてはコーニング７５８３（商品名
）、オーエンスイリノイス０Ｖ−１１１（商品名）等が
好適に用いうるがこれに限定されることはない。As the crystallized glass 14, Corning 7583 (trade name), Owens Illinois 0V-111 (trade name), etc. can be suitably used, but the present invention is not limited thereto.
なお１ｊｎ述の有機バインダー、溶剤の４’ＪｆＫ＜は
別工程とすることなく、前記塗布した結晶化ガラス１４
上にり−トフレーム１２を直接載せ、徐々に昇温して有
機バインダー、溶剤を揮散させると同時に、結晶化カラ
ス上４を融解させ、さらに結晶化させるようにすること
もてきる。Note that the organic binder and solvent 4'JfK< described in 1jn are not treated as separate steps, but are applied to the coated crystallized glass 14.
It is also possible to directly place the top frame 12 on top and gradually raise the temperature to volatilize the organic binder and solvent, and at the same time melt the crystallizing glass top 4 and further crystallize it.
次ニ、上記リードフレーム１２を固着したセラミックベ
ース１０内に素子１１を搭載し、素子１］−と内部リー
ド１３との間に必要なワイヤボンディングを施し、次い
で内部リード１３上面に常法のごとく低融点ガラス１７
を用いてキャップ１６により気密封止するものである。Next, the element 11 is mounted in the ceramic base 10 to which the lead frame 12 is fixed, and necessary wire bonding is performed between the element 1 and the internal leads 13, and then the upper surface of the internal leads 13 is bonded in the usual manner. Low melting point glass 17
The cap 16 is used for airtight sealing.
低融点ガラス１７は、その粉末に適宜な有機バインター
、溶剤を添加してペースト状にしたものラスクリーン印
刷等によって気密封止パターンに対応してキャップ１６
上に塗布し、これを８０’Ｃ〜１５Ｑ″Ｃに加熱して溶
剤を揮散させ、約３ｏｏ″Ｃで有機バインダーを飛ばし
、次いで約４２０”Ｃに加熱してキャップ１６上にグレ
ーズしておくと好適である。この低融点ガラス１７をグ
レーズしたキャップ１６を前記リードフレームを固着し
たセラミックベースＩＱＪ−に重ね、約４５０″Ｃに加
熱することによってギャップ］６による気密封止が行え
る。このようにして製造したセラミックパッケージは、
前記素子工１＋Ｊけの際の加熱や上記キャップ１６によ
り気密封止する際の加熱温度では、前記内部！Ｊ −１
−１３を固着している結晶化し固化しｔ、＝ ｋ 晶化
ガラス１４は軟化せず、リードフレーム１２に帯有する
前述の内部残留歪は結晶化カラス１４を用いることによ
って開放されることがなくなり、内部リード１３の変形
や位置ずれが生ずることなく、精度よく固着されたまま
となり、所望の半導体装置用セラミック／ぐツヶージを
得ることかできる。The low melting point glass 17 is made by adding an appropriate organic binder and solvent to the powder to form a paste.The cap 16 is made by la screen printing or the like to form an airtight sealing pattern.
This is heated to 80'C to 15Q"C to volatilize the solvent, and the organic binder is evaporated at about 30"C, and then heated to about 420"C to glaze it on the cap 16. The cap 16 glazed with the low melting point glass 17 is stacked on the ceramic base IQJ- to which the lead frame is fixed and heated to about 450''C, thereby achieving airtight sealing through the gap]6. The ceramic package manufactured in this way is
The inside! J-1
-13 is crystallized and solidified, t,=k, and the crystallized glass 14 does not soften, and the above-mentioned internal residual strain in the lead frame 12 is not released by using the crystallized glass 14. Therefore, the internal leads 13 remain fixed with high precision without being deformed or misaligned, making it possible to obtain the desired ceramic/glue cage for semiconductor devices.
なお上記低融点ガラス１７としては、非結晶化ガラスで
ある日本電気硝子製ＬＳ−０１１０を使用して好結果を
得たが、これに限定されないことはもちろんである。Although good results were obtained by using LS-0110, a non-crystallized glass manufactured by Nippon Electric Glass, as the low-melting glass 17, it is needless to say that the present invention is not limited thereto.
低融点ガラス１７に結晶化ガラスを用いた場合には、結
晶化して固化させて気密封止してもよく、あるいは結晶
化させずに気密封止してもよい。When crystallized glass is used as the low melting point glass 17, it may be crystallized and solidified and hermetically sealed, or it may be hermetically sealed without being crystallized.
」二記のごとく接合したキャップ１６とセラミックベー
ス１０間の接合強度を引張りによる破壊試験で確認した
ところ、セラミックベースｌＯ°と結晶化ガラス１４と
の境界またはキャップ１６と低・融点ガラス１７との境
界で破断し、低融点ガラス１７と結晶化ガラス１４との
境界で破断することは皆無であった。また、その気密封
止特性においても従来のものと何ら遜色がないことか確
認された。When the bonding strength between the cap 16 and the ceramic base 10 bonded as described in 2 was confirmed by a tensile destructive test, it was found that the bond strength between the ceramic base lO° and the crystallized glass 14 or between the cap 16 and the low melting point glass 17 There was no breakage at the boundary, and no breakage at the boundary between the low melting point glass 17 and the crystallized glass 14. It was also confirmed that its hermetic sealing properties were no different from conventional ones.
以」二のように本発明方法によれば、結晶化ガラスを用
い、内部リードを位置決めして結晶化し固化させること
により、以後の素子材は工程やキャンプによる気密封止
の際に加わる熱によっても、結晶化ガラスが軟化せず、
内部残留歪を帯有する内部リートは結晶化ガラスによっ
て完全に固着されてしまい、内部リードが変形したり位
置ずれすることなく、内部リードの位置精度のよい半導
体装置用セラミックパッケージを歩留りよく製造するこ
とができる。As described below, according to the method of the present invention, crystallized glass is used, and by positioning the internal leads and crystallizing and solidifying them, the subsequent element materials are resistant to heat applied during the process and hermetic sealing by camping. However, the crystallized glass does not soften,
To manufacture with a high yield a ceramic package for a semiconductor device in which internal leads have good positional accuracy without deforming or shifting the internal leads because the internal leads having internal residual strain are completely fixed by crystallized glass. I can do it.
以上本発明につき好適な実施例を挙げて種々説明、した
が、本発明はこの実施例に限定されるものではなく、発
明の精神を逸脱しない範囲内で多くの改変を施し得るの
はもちろんのことである。Although the present invention has been variously explained above with reference to preferred embodiments, the present invention is not limited to these embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention. That's true.
第１図、第２図はそれぞれ従来例を示す断面説明図であ
る。第３図は本発明に係る半導体装置用セラミックパッ
ケージの一例を示す断面図である。
１１９．セラミックベース、２．、、凸部。
３８１．内部リード、４，５．、、低融点ガラス。
６９１．キャンプ、７９．連結片。
１０、 、セラミックベース、１１．、、素子。
１２、、、 リードフレーム、１３．、、内部リード
、１４．、、結晶化ガラス、工５６１．ワイヤ。
１６、、、キャップ、１７．、、低融点カラス。
特許出願人
新光電気工業株式会社
図 面
図 面FIGS. 1 and 2 are cross-sectional explanatory views showing conventional examples, respectively. FIG. 3 is a sectional view showing an example of a ceramic package for a semiconductor device according to the present invention. 119. Ceramic base, 2. ,,Convex part. 381. Internal lead, 4,5. ,,low melting point glass. 691. Camp, 79. Connecting piece. 10. Ceramic base 11. ,,element. 12. Lead frame 13. ,,internal lead,14. ,,Crystallized Glass, Engineering 561. wire. 16., Cap, 17. ,, low melting point crow. Patent applicant Shinko Electric Industry Co., Ltd.
Claims (1)
融点ガラスを用いてリードフレームの内部リードを固着
する低融点ガラス封止型半導体装置用セラミックパッケ
ージの製造方法において、前記内部リードを固着する低
融１ξガラスに融解した後結晶化して固化する結晶化ガ
ラスを用い、内部リードを位置決めして前記結晶化ガラ
スを結晶化して固化することにより前記セラミックベー
ス面上に固着することを特徴とする半導体装置用セラミ
ックパッケージの製造方法。(2) A method for manufacturing a ceramic package for a semiconductor device sealed with low melting point glass, in which internal leads of a lead frame are fixed using low melting point glass. A semiconductor characterized in that a crystallized glass that is melted into a molten 1ξ glass and then crystallized and solidified is used, and is fixed on the ceramic base surface by positioning an internal lead and crystallizing and solidifying the crystallized glass. A method for manufacturing a ceramic package for equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22247682A JPS59112635A (en) | 1982-12-17 | 1982-12-17 | Manufacture of ceramic package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22247682A JPS59112635A (en) | 1982-12-17 | 1982-12-17 | Manufacture of ceramic package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59112635A true JPS59112635A (en) | 1984-06-29 |
Family
ID=16783011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22247682A Pending JPS59112635A (en) | 1982-12-17 | 1982-12-17 | Manufacture of ceramic package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59112635A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63275149A (en) * | 1987-05-06 | 1988-11-11 | Nec Kyushu Ltd | Semiconductor device |
-
1982
- 1982-12-17 JP JP22247682A patent/JPS59112635A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63275149A (en) * | 1987-05-06 | 1988-11-11 | Nec Kyushu Ltd | Semiconductor device |
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