JPS59111384A - Compound semiconductor element - Google Patents

Abstract

PURPOSE:To obtain the titled compound semiconductor element by which the loss of electric power is suppressed minor and, in addition, the area of the element is made smaller and the yield can be upgraded by a method wherein the collector layer of a bipolar transistor is used in common with the LD of a semiconductor laser and the LD to be used as a collector load is made into a structure which is controlled by corrector current, by arranging the bipolar transistor in longitudinal type to the LD of the semiconductor laser. CONSTITUTION:A quadrilayer 302 of InGaAsP is epitaxially grown on an N type InP substrate 301. After that, a P type InP layer 303 is epitaxially grown, and, in addition, a P type InGaAsP layer 304, the so-called cap layer 304, is grown. The back surface of the N type InP substrate 301 is performed an etching in order to grow epitaxially a buffer layer. Then, a P type InP layer 305, which is subjected to become the base layer, is epitaxially grown. Impurities are selectively diffused or implanted on the base layer 305 for forming an emitter layer 306. In this case, as the emitter layer 306 becomes an N type, an npn transistor is formed in longitudinal type to a P clad layer 303, an active layer 302 and an N clad layer 301, by which the LD is constituted, because the substrate 301 and the base layer 305, which are subjected to become the collector layer, are an N type and a P type respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compound semiconductor device, and particularly to an integrated structure of a diode such as a semiconductor laser (hereinafter abbreviated as LD) and its driving element.

Conventional configurations and their problems LDs have recently been actively developed for high-density transmission of information such as optical communications. Furthermore, LD is used in optical communication,
Integrated circuits (hereinafter abbreviated as ICs), which are elements that convert electrical signals into optical signals and which integrate electrical signal processing and LD, have recently been attracting attention.

The structure of a conventional integrated IC is a junction FET, LD, and gold I.
A version of C has been announced. This structure is shown in FIG. In Figure 1, 1 is a semi-insulating GaAs substrate, 2 is an n
3 is an n-type GaAs layer, 4 is an n-type GaAs layer, 6 is a p-type AnGaAs layer, 6 is an insulating film, 7 is a conductive metal, 8 is a source electrode, 9 is a gate electrode, 10 is a drain electrode, 11 is a gate diffusion layer, and 12 is a p-type high concentration layer. Note that FIG. 2 shows an equivalent circuit of the cross-sectional structure element shown in FIG. 1. Places with the same numbers as in FIG. 1 indicate the same names. Although this structure is close to a planar type, it is not a completely planar type (the FET part is selectively etched down to the n-type GaAs layer 2, or the LD part is selectively grown epitaxially. Therefore, a step occurs and the manufacturing yield is reduced. In addition, since it is difficult to obtain low voltage and large current, the power consumption loss is large, which increases the threshold current value (hereinafter referred to as Ith) of the LD and reduces the oscillation efficiency.Furthermore, the mutual conductance (hereinafter referred to as qm ) to increase the gate width Wq relative to the gate length Lq.
Since it is necessary to take a large ratio, the element area becomes large.

As mentioned above, the structure shown in Figure 1 has a complicated device structure, which results in poor manufacturing yields, and the large device area means that it is expensive at present, when large-diameter wafers and epitaxial growth technology are difficult to use. Become something. Furthermore, F.E.
Since it is T, it is difficult to operate at a low voltage and a large current, which results in a vicious cycle in which the power loss is large and the Ithi of the LD is increased.

Purpose of the Invention The present inventors focused on using a bipolar transistor as the driving element from the viewpoint of reducing the power loss of the driving element of the LD, and as a result, if the LD and the bipolar transistor are arranged vertically, It has been found that power loss is small and the device area is also small. Therefore, in view of the problems of the conventional example as described above, the present invention integrates a diode and a bipolar transistor, reduces power loss, minimizes increase in Ith, and further reduces the element area. The present invention provides a compound semiconductor device that can be used as a storage device.

Structure of the Invention The present invention has a bipolar transistor arranged vertically with respect to an LD, and a collector layer iL of the bipolar transistor.
This provides a structure in which the LD is shared with D and the LD as a collector load is controlled by the collector current.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a cross-sectional structure of a planar compound semiconductor device according to a first embodiment of the present invention. Figure 4 shows its equivalent circuit. In FIG. 3, 301 is a single crystal n-type InP
The substrate 3o12 is a quaternary layer of InGaAsP and is called an active layer. 303 is a p-type InP layer called a P cladding layer. 304 is a p-type quaternary layer called a cap layer. 305 is a p-type InP layer and is a base layer. 306
is an n-type 1nP layer and an emitter layer, 307.308.309
represent a collector electrode, a base electrode, and an emitter electrode, respectively.

A method of manufacturing the structure shown in FIG. 3 will be described below. An InGaAsP 04 source layer 302f is epitaxially grown on an n-type InP substrate 301. After that, p
A type 1nP layer 303'ii is epitaxially grown, and a p-type InGaAs P layer 304 is formed as a so-called cap layer 3.
Grow 04. Thereafter, the back surface of the n-type InP substrate 301 is etched to epitaxially grow an n-type 1nPl so-called buffer layer.

This is to prevent crystal defects in the substrate, and is not particularly necessary. Thereafter, a p-type InP layer 305'i, which becomes a base layer, is epitaxially grown. Using a diffusion mask or the like, impurities such as Te, S, and Si are selectively diffused or implanted onto the base layer 306 to form an emitter layer 306f. In this case, since the emitter layer 306 becomes n-type, the substrate 3o1. The base layer 306 is n-type,
Since it is a p-type, the p cladding layer 303. which the npn transistor constitutes LD'i. Active layer 302. n cladding layer 3
The present invention is characterized by a structure in which the substrate 301 shares the collector layer of the npn transistor formed vertically with respect to the npn transistor 301 and the n cladding layer of the LD.

The resistive electrodes 307, 308, and 309 are formed by depositing a metal material such as Au-Zn on the p-type InP layer and a metal material such as Au-8n on the n-type InP layer by vapor deposition or the like.

As described above, in the first embodiment of the present invention, the planer type LD and the npn bipolar transistor are
Type InP substrate 301 f n cladding layer.

By sharing each layer as a collector layer, a vertical structure is formed. The emitter electrode 309 is used as a common bias voltage, a positive voltage source is connected to the collector electrode 307, and a base current is applied to the base electrode 30B. The LD connected via the collector electrode 307'i is driven by the collector current by controlling the base current.

FIG. 6 shows a cross-sectional structure of a planar compound semiconductor device according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in that the structure of the LD is changed from a planar type to a groove type. By creating a groove structure, the current concentration to the LD is increased, thereby reducing Ithi.

In FIG. 6, 501 is an n-type InP substrate, 502 is InG
aAsP quaternary active layer, 603 is a p-cladding layer of p-type InPH, 504 is a cap layer of p-type InGaAsP, 505 is a base layer of p-type InP layer, 606 is an n-type I
507 is a collector electrode made of a metal such as Au or Zn; 508 and 509 are base and emitter electrodes made of a metal such as Au-3n; and 610 is a p-type diffusion or injection layer which serves as a current blocking layer.

611 is an n-type 1nP layer and n cladding layer, 612 is In
A GaAgP quaternary layer and 513 indicate an insulating film.

A method of manufacturing the structure shown in FIG. 5 will be described below. A p-type InP layer 510 is formed on one side of an n-type InP substrate 501 by diffusing or implanting an impurity such as Zn or Cd.

This is called the current narrowing layer. After that, selectively n-type In
A groove is formed by etching the P substrate 601 with a bromethanol-based or hydrochloric acid-phosphoric acid-based etching solution. After that, an n-type 1nP layer of n-clad Ni511, In
GaAsP quaternary active layer 502. P cladding layer tso3. of p-type InP layer. A p-type InGaAgP quaternary cap layer 604 is then epitaxially grown.

Next, after performing an etching process to remove crystal defects on the other side of the n-type InP substrate 601, an n-type InP layer is epitaxially grown as a buffer although it is not particularly necessary, and then a p-type InP layer is grown as a base layer. layer 60
5. InGaAsP 4-element layer 5 that cannot take ohmic
12ft epitaxial growth. Thereafter, the emitter layer tsoe is selectively formed so as to coincide with the groove in the longitudinal direction.
form. The emitter layer 506 is formed by diffusing or implanting impurities such as Te, s, and Si. 4-layer layer 5
After selectively etching 12 with nitric acid or sulfated hydrogen peroxide, CVD (Chemical V
After forming an insulating film 513f by a per deposition method or the like and selectively opening holes, Au-Z
Electrode 508.50 by metal such as n, Au-8n
Form 9i. Of course, a collector electrode 607 is also formed.

As described above, in the second embodiment of the present invention, the grooved LD and the npn bipolar transistor are
By sharing the type InP substrate 301i, a vertical structure is formed.

In addition, as an example related to the present invention, I nP −I n
The explanation was given using the quaternary system of GaAs P as an example, but GaAs
It goes without saying that the ternary system of s-AfiGaAs can be constructed in a very similar manner. Further, although planar and trench type LDs have been shown in the embodiments as LDs having a vertical structure and an npn bipolar transistor, buried type and TS types can also be formed in the same manner. Furthermore, other light emitting elements such as LEDs (light emitting diodes) may be formed instead of LDs.

Effects of the Invention As described above, the present invention provides (1) LDi operation with reduced power loss due to the integrated IC structure using bipolar transistors as the LD and its driving element. This prevents an increase in Ith of the LD due to heat generation, which is a conventional problem, that is, a decrease in oscillation efficiency.

(2) In an integrated IC structure of an LD and a bipolar transistor as its driving element, by sharing the cladding layer of the LD and the collector layer of the transistor, the transistor can be constructed directly above the current narrow T layer of the LD. It has a type structure. This eliminates the lateral current component, allowing current to flow through the LD layer more efficiently.

(3) Growing compound semiconductor layers on both sides of the substrate has the advantage that the impurity concentration of the LD and the impurity concentration of the transistor can be controlled independently.

(4) Since the vertical structure allows the IC area to be reduced, high-density ICs are possible.

It has useful effects such as, and has sufficient industrial value.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional LD integrated IC structure, Fig. 2 is an equivalent circuit diagram of the IC structure shown in Fig. 1, and Fig. 3 is an integrated LD and bipolar transistor according to the first embodiment of the present invention. 4 is an equivalent circuit diagram of the same device, and FIG. 5 is a sectional view of a compound semiconductor device in which an LD and a bipolar transistor are integrated, which is a second embodiment of the present invention. 301.501...Compound semiconductor element, 302°502...Compound semiconductor layer (active layer), 303
゜503...Compound semiconductor layer (cladding layer),
304°604... Compound semiconductor layer (cap layer), 306°506... Compound semiconductor layer (base layer), 306°506... Emitter layer, 3
07.507...Collector electrode, 308.50
8...Base electrode, 309°509...
Emitter electrode, 510... Layer for current narrowing, 611
・・・・・・Clad layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure f Figure 2

Claims (1)

[Scope of Claims] (1) A first compound semiconductor layer forming a heterojunction is provided on one main surface of a compound semiconductor substrate of a first conductivity type, and the conductivity type is opposite to that of the compound semiconductor substrate. a second compound semiconductor layer of a second conductivity type on the first compound semiconductor layer, and a third compound semiconductor layer of a second conductivity type on the second compound semiconductor layer. and a fourth compound semiconductor layer of a second conductivity type, which is a conductivity type opposite to that of the compound semiconductor substrate, on the other main surface of the compound semiconductor substrate, and the third compound semiconductor layer, the fourth compound semiconductor layer, each has a resistive electrode on the compound semiconductor layer of the first compound semiconductor layer, the compound semiconductor substrate is used as a collector layer, and the first compound semiconductor substrate is a collector layer. Second. It is characterized by having a diode formed by a third compound semiconductor layer and the compound semiconductor substrate, using the fourth compound semiconductor layer as a base layer, and having an emitter layer in or on the base layer. Compound semiconductor device. (2) The compound semiconductor device according to claim 1, wherein the emitter layer is formed by selectively diffusing impurities into the fourth compound semiconductor layer. (3) The compound semiconductor device according to claim 1, wherein the emitter layer is formed by selectively implanting impurities into the fourth compound semiconductor layer. (4) The emitter layer is characterized by comprising a sixth compound semiconductor layer selectively formed on the fourth compound semiconductor layer so as to form a heterophonic junction with the fourth compound semiconductor layer. A compound semiconductor device according to claim 1. (5) The compound semiconductor device according to claim 1, wherein a resistive electrode is formed on the base layer or the emitter layer via a compound semiconductor layer. (6) A compound semiconductor device according to claim 1, characterized in that a current confinement layer is selectively formed on a compound semiconductor substrate. (7) A groove is formed between the current confinement layers of the compound semiconductor substrate. The compound semiconductor device according to claim 1, characterized in that: (8) between the current confinement layer of the compound semiconductor substrate and the first compound semiconductor layer, a layer opposite to the current confinement layer; 2. The compound semiconductor device according to claim 1, further comprising a conductive type compound semiconductor layer.