JPS59113678A - Compound semiconductor element - Google Patents

Abstract

PURPOSE:To enable to upgrade the yield by a method wherein an LD and a bipolar transistor are arranged in vertical type by using the bipolar transistor for a driving element to suppress the loss of electric power less, lessen the increase of Ith and reduce the area of the element. CONSTITUTION:A four elements layer 32 of InGaAsP is epitaxially grown on an N type InP substrate 31. After that, on the four elements layer 32 is epitaxially grown a P type InP layer 33 called a P-clad layer and an N type InP layer 34 is epitaxially grown on the P-clad layer 33. And then, impurities of Zn or Cd, etc., are selectively diffused or implanted in the N type InP layer 34 for forming a P type InP layer 35. At this time, the N type InP layer 34 being interposed between the P type InP layer 35 and the InP layer 33 is turned into the base layer and the width thereof becomes the base width. The four elements layer 32 being interposed between the N type InP substrate 31 and the P type InP layer 33 forms a double junction of a different kind and shuts the carriers in by current from the emitter of the P type InP layer 35 located right over the layer 32 to generate the laser luminescense.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compound semiconductor device, and particularly to an integrated structure of a diode such as a semiconductor laser (hereinafter abbreviated as LD) and its driving element.

Conventional Structures and Problems LDs have recently been actively developed for high-density transmission of information, such as optical communications. Furthermore, in optical communications, LD is an element that converts electrical signals into optical signals, and is an integrated circuit (hereinafter abbreviated as IC) that integrates electrical signal processing and LD.
has been attracting attention recently.

The structure of the conventional integrated IC is that the junction FET and LD are
A version of C has been announced. This structure is shown in FIG. In FIG. 1, 1 is a semi-insulating GaAs substrate,
2 is an n-type Ga As layer, 3 is an n-type AI Ga
A s layer, 4 is an n-type Ga As layer, 6 is a p-type AI Ga As layer, 6 is an insulating film, 7 is a conductive metal, 8 is a source electrode, 9 is a gate electrode, 10 is a drain electrode, 11 is a gate diffusion layer, and 12 is a p-type high concentration layer.

FIG. 2 shows an equivalent circuit of the cross-sectional structure element shown in FIG. 1. The same numbers as in FIG. 1 indicate the same names. Although this structure is close to a planar type, it is not a completely planar type, and the FET portion is selectively etched down to the n-type GaAs layer 2, or the LD portion is selectively grown epitaxially. Therefore, a difference in level occurs, resulting in a poor manufacturing yield. In addition, since it is difficult to obtain low voltage and large current, the power consumption loss is large, and this results in a large current value (hereinafter referred to as Ii) of the LD.
(abbreviated as h) increases, reducing oscillation efficiency.

Furthermore, in order to increase mutual conductance (hereinafter abbreviated as gm), it is necessary to increase the ratio of gate width wg to gate length Lq, which increases the element area. As mentioned above, the structure shown in Figure 1 has a complicated device structure, which results in a poor manufacturing yield9, and the large device area is a problem in terms of cost, as large-diameter wafers and epitaxial growth technology are currently difficult to use. It becomes expensive. Furthermore, since it is a FET, low voltage and large current operation is difficult, and therefore power loss is large (a vicious cycle that increases It-h of the LD).

Purpose of the Invention The present inventors focused on using a bipolar transistor in the driving element from the viewpoint of reducing the power loss of the driving element of the LD, and as a result, the LD and the bipolar transistor were used as the driving element.
If the transistors are arranged vertically, power loss is small,
It has been found that the element area can also be reduced. therefore,
In view of the problems of the prior art as described above, the present invention integrates a diode and a bipolar transistor, minimizes power loss, minimizes increases in It and h, and further reduces the element area. Accordingly, a compound semiconductor device with improved yield can be obtained.

Structure of the Invention The present invention provides a bipolar transistor that is arranged directly above the LD, and the L
This provides a structure in which a current is allowed to flow vertically toward D, and the drive current of the LD is controlled by the base electrode.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a cross-sectional structure of a planar compound semiconductor device according to a first embodiment of the present invention, and FIG. 4 shows its equivalent circuit. In FIG. 3, 31 is a single crystal n-type InP substrate, 32 is an InGaAsP quaternary layer, 33 is a p-type InP layer, 34 is an n-type InP layer, 35 is a p-type InP layer, 36.
37 and 38 respectively indicate metals forming the resistive electrodes.A quaternary layer 32 of InGaAsP is epitaxially grown on an On-type InP substrate 31, in which a method for manufacturing the structure shown in FIG. 3 will be described below. After that, a p-type InP layer 33 called a p-cladding layer is epitaxially grown on the quaternary layer 32, and an n-type InP layer 34 is epitaxially grown on the p-cladding layer 33.
Alternatively, the p-type InP layer 35 may be formed by selectively diffusing or injecting a non-woven material such as Cd.
form. At this time, the n-type InP layer 34 narrowed by the p-type InP layer 36 and the InP layer 33 becomes a base layer,
This width becomes the base width. In addition, the n-type InP substrate 31 and the p
The quaternary layer 32 sandwiched between the type InP layer 33 forms a double heterojunction, and current from the emitter of the p-type InP layer 35 directly above traps carriers and causes laser emission. In FIG. 3, the p-Clarad layer 33 as an LD is also used as the collector layer 33 of a bipolar transistor. 36, 37, 38 are resistive electrodes.

An Au-8n electrode is used for the n-type InP layer, and the p-type InP layer is
An Au-Zn electrode may be used for the P layer.

FIG. 5 shows a second embodiment according to the invention. 51 is n-type I
nP substrate, 52 is a quaternary layer of InGaAsP, 53 is a p-type InP layer (92271 layer and collector layer), 64 is an n-type InP layer (base layer), 65 is a p-type InGaAsP formed on the base layer 64 4 elements (emitter layer), 5
6, 57, and 58 each indicate the metal forming the resistive electrode. The steps up to the epitaxial growth of the n-type InP layer of the base layer 54 are the same as in the first embodiment of the present invention. The difference between the second embodiment and the first embodiment is the configuration of the emitter layer 55.

In the first embodiment, Z
Whereas the PN junction was formed by diffusing or implanting impurities such as n or Cd, the second embodiment has a different type of junction growth layer with the base layer 64. If a heterojunction is used as shown in FIG. 6, and the one with a larger band gap is used as an emitter layer, carriers will be injected into the base region due to the difference in band gap. The structure shown in FIG. 6 is particularly effective in increasing the injection efficiency when the concentration difference between the emitter layer and the base layer cannot be increased in a PN junction.

FIG. 6 shows a third embodiment of the invention. The equivalent circuit is the fourth
Same as shown in the figure. 61 is n-type InGaAsP
63 is a p-type InP layer (92271 layer and collector layer), 64 is an n-type 1nP layer, and 65 is a p-type InP layer.
Layers 6616 and 68 each represent metal forming resistive electrodes. 69 is an n-type quaternary layer, and 610 is a p-type quaternary layer. Until the epitaxial growth of the n-type InP layer 64,
This is the same as the first embodiment according to the present invention. n-type InP layer 6
After forming the n-type quaternary layer 69, a thin n-type quaternary layer 69 is grown.

Thereafter, a p-type InP layer 66 to serve as an emitter is formed using selective diffusion or selective implantation, and quaternary layers 69 and 610 are left using selective etching. The four-layer layer 610 is
It is inverted to p-type by impurities such as Zn or Cd. After that, 66.67 by metal such as Au-Zn
An n-type Inp layer substrate 61 is formed with electrodes A
The electrode 68 is formed of metal such as uSn.

The characteristic feature of this third embodiment is that n-type InP
By providing the quaternary layer 69, so-called a cap layer, formed on the layer 64, the emitter 67 and the base 66 can be made of one type of wiring metal material such as Au-Zn.

FIG. 7 shows a fourth embodiment of the present invention.

In the first and second embodiments, the structure of the LD is a planar structure, whereas in the fourth embodiment, the structure is changed to a {circle around (2)} structure to reduce Ith. Reference numeral 701 indicates an n-type 1nP substrate, and a p-type region 71 for current narrowing is formed by diffusing or implanting Zn or Cd on the entire surface of the substrate 701.
form 1. The entire surface diffusion plate 701 is selectively etched using a bromine/methanol based or hydrochloric acid/phosphoric acid based etching solution to form a V-groove. (2) After forming the trench, grow a quaternary layer 702 of InGaAsP.

■The growth rate in the groove is fast from the first row of plane orientation.
It has a crescent shape, and the presence of the p-type region 711 allows current concentration from the transistor provided directly above it. After forming the quaternary layer 702, a p-type InP layer (922
71 layer and collector layer), 703, and further n-type InP layer (
base layer) 04, and quaternary layer (cap layer) 7
Form o9 in order.

A p-type Inp layer (emitter layer) 705 is formed by selectively diffusing or implanting impurities such as Zn or Cd so that the emitter layer 7'05 is placed directly above the V-groove. Selective etching is performed using a trowel using a nitric acid-based or sulfated hydrogen peroxide etching solution so that the quaternary layers 709 and 710 corresponding to the emitter electrode portion and the base electrode portion remain. After that, CV D (Chemical
After forming an insulating film 712 using a vapor deposition method or the like, and selectively removing the insulating film 712 corresponding to the contact windows of the emitter and base electrode parts, a metal film such as Au-Zn is formed by vapor deposition or the like. , selectively etching the wiring pattern so that it remains. The collector electrode via the LD is formed by forming a metal film such as Au-8n on the n-type InP substrate 701 by vapor deposition or the like. The completed weno is cleaved to form a mirror surface and made into chips. The IC chip is Au-8n
The surface of the electrode 708 is die-bonded to a package or the like by soldering or the like, and the electrodes 706 and 707 are assembled to the IC+7- board by wire bonding. The feature of this fourth embodiment is that the Ith of the LD is lowered by blocking the lateral current by the groove structure and the diffusion layer 711 serving as the current confinement layer, thereby reducing the current capacity of the bipolar transistor.

FIG. 8 shows a fifth embodiment of the present invention.

In the sixth embodiment, in order to further improve the lateral current blocking effect of the V-groove in the fourth embodiment, the p-type diffusion layer 711 is
The point is that an n-type 1nP layer (so-called buffer layer) 813 is provided between and the quaternary layer 702. This results in a p'npn structure in the lateral direction, blocking current flow.

FIG. 9 shows a sixth embodiment of the present invention.

■Groove structure, p-type diffusion layer 711, n-type buffer layer 813
The LD having the current blocking structure is the same as in the fourth embodiment. The feature of the sixth embodiment is that the base layer 704 and emitter layer 706 are formed by selective diffusion or implantation. This is often used in the structure of St bipolar transistors, and increases the n-type concentration directly under the base electrode 706 to lower the base resistance, and reduces the base concentration directly under the emitter layer 705 to increase injection efficiency. By using base diffusion or base implantation in this manner, transistor characteristics can be improved. Te, S, St, etc. may be used as the impurity for n-type diffusion.

In addition, as an example related to the present invention, InP-InGaA
The explanation was given using the gP04 element system as an example, but GaAs-A
, /GaAs can be similarly formed. Furthermore, other light emitting elements such as LEDs (light emitting diodes) may be formed in place of the LD.

Effects of the Invention As described above, the present invention provides (1) an integrated IC structure that uses bipolar transistors as the LD and its driving element, thereby making it possible to operate the LD with reduced power loss; This prevents an increase in 1th of the LD due to heat generation, that is, a decrease in oscillation efficiency, which has often occurred in the past.

(2) In an integrated IC structure of an LD and a bipolar transistor as its driving element, by using the cladding layer of the LD as the collector layer of the bipolar transistor, the collector base emitter is placed directly above the current confinement layer of the LD. It is a vertical structure that can be configured with This eliminates the lateral current component and improves efficiency (current can flow through the current confinement layer of the LD.Furthermore, there is less power loss and less heat generation.Also, since the IC surface is small, high-density ICs can be implemented. be.

The above-mentioned effects are sufficiently valuable and can realize a good optical IC.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional compound semiconductor device, FIG. 2 is an equivalent circuit diagram of the device shown in FIG. 1, and FIG. 3 is an integrated compound semiconductor of an LD and a bipolar transistor according to the first embodiment of the present invention A cross-sectional view of the element, Figure 4 is an equivalent circuit diagram of the element,
FIG. 6 is a sectional view of an integrated compound semiconductor device of an LD and a bipolar transistor, which is a second embodiment of the present invention, and FIG. 6 is a cross-sectional view of an integrated compound semiconductor device of an LD and a bipolar transistor, which is a third embodiment of the invention. 7 is a cross-sectional view of an integrated compound semiconductor device of an LD and a bipolar transistor according to a fourth embodiment of the present invention, and FIG. 8 is a cross-sectional view of an integrated compound semiconductor device of an LD and a bipolar transistor according to a sixth embodiment of the present invention. FIG. 9 is a sectional view of an integrated compound semiconductor device according to the sixth aspect of the present invention.
1 is a cross-sectional view of an integrated compound semiconductor device of an LD and a bipolar transistor, which is an example. 31.61.61.701... Compound semiconductor substrate, 32, 33, 34, 52, 53, 54, 702°7
03.704,711.813...Compound semiconductor layer, 36', 37,56,56', 57,706,7
07...Resistance 1 is extreme. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure f Figure 21A Figure 3 Figure 4 Figure 1J5 Figure 6

Claims (1)

[Scope of Claims] (1) - A first compound semiconductor layer forming a heterojunction on a conductivity type compound semiconductor substrate, and a second conductivity type compound semiconductor layer having a conductivity type opposite to that of the compound semiconductor substrate. a second compound semiconductor layer on the first compound semiconductor layer; a third compound semiconductor layer having a conductivity type opposite to that of the second compound semiconductor layer; Each has a resistive electrode on the third compound semiconductor layer, the second compound semiconductor layer is a collector layer, and the first... A compound semiconductor characterized by forming a diode using a second compound semiconductor layer and a compound semiconductor substrate, using the third compound semiconductor layer as a base layer, and having an emitter layer in or on the base layer. element. (Sakaki) The compound semiconductor device according to claim 1, wherein the emitter layer is formed by selectively diffusing impurities into the third compound semiconductor layer. The compound semiconductor device according to claim 1, wherein the emitter layer is formed by selectively implanting impurities into the third compound semiconductor layer. Claim 1, wherein the layer comprises a fourth compound semiconductor layer selectively formed on the third compound semiconductor layer so as to form a heterojunction with the third compound semiconductor layer. The compound semiconductor device according to claim 1. ((f) The compound according to claim 1, which has a resistive electrode on the base layer or the emitter layer via the compound semiconductor layer. Semiconductor device. (@ Compound semiconductor device according to claim 1, characterized in that the compound semiconductor substrate selectively has nine current narrowing layers. (7) Grooves are formed between the current narrowing layers of the compound semiconductor substrate. The compound semiconductor device according to claim 1, characterized in that it has a current confinement layer of the compound semiconductor substrate and the first compound semiconductor layer, which is opposite to the current confinement layer. The compound semiconductor device according to claim 1, characterized by having a conductive type compound semiconductor layer.