JPS59222988A - Compound semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To isolate a LD, a transistor as a driving element for the LD and a P-I-N APD as a light-receiving element electrically completely by forming a semiconductor substrate and a semiconductor layer and integrating an electrical element to the semiconductor layer. CONSTITUTION:An InGaAsP four-element layer 302 called an active layer, a P type InP layer 303 called a P clad layer and a P type InGaAsP layer 304 called a cap layer are grown on an N type InP substrate 301 in an epitaxial manner in succession. The cap layer 304, the P clad layer 303 and the active layer 302 are etched selectively. An insulating film 306 is formed so as to coat projecting sections (LD sections). The insulating film 306 is deposited by using a CVD method in order to also form the insulating film 306 to the vertical sections of the projecting sections. Sections required as electrical devices on polycrystalline silicon layers 307 are changed selectively into single crystals or the whole surface into single crystal by the irradiation of energy rays, thus obtaining single crystal layers 308.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an integrated structure of a diode such as a semiconductor laser (hereinafter abbreviated as LD) and its driving element.

Conventional configurations and their problems LDs have been actively developed recently because they are capable of high-density transmission of information such as optical communications.

In optical communications, an LD is an element that converts electrical signals into optical signals. Particularly recently, the development of integrated circuits (hereinafter abbreviated as ICs) that integrate electrical signal processing and LDs has been attracting attention.

The structure of conventional integrated IC is junction type FIT, LD and fi
An IC version has been announced.

This structure is shown in FIG. In Figure 1, 1 is semi-insulating G? LAs substrate, 2 is n-type GaAs layer, 3 is n-type A
1GaAs layer, 4 is n-type GaAs J@, 5 is p-type AlGaAs layer, 6 is an insulating film, 7 is a conductive metal, 8
1 is a source electrode, 9 is a gate electrode, 10 is a drain electrode, 11 is a gate diffusion layer, and 12 is a p-type cavity concentration layer. FIG. 2 shows an equivalent circuit of the element cross-sectional structure shown in FIG. 1. Places with the same numbers as in FIG. 1 indicate the same names. This structure is close to the Brehner type, but it is not a complete Brehner type.
The FET portion is selectively etched down to the n-type GaAs layer 2, or the I and D portions are selectively grown epitaxially. Therefore, a difference in level occurs, resulting in a poor manufacturing yield.

Furthermore, in the conventional example shown in FIG. 1, there is only one drive element, but it is a difficult structure to electrically isolate a plurality of elements and convert them into an IC.

Purpose of the Invention The present invention has been made in view of the problems of the conventional examples as described above.
A compound semiconductor device is obtained in which a plurality of transistors and an LD are integrated into an IC with a planar structure.

Structure of the Invention The present invention provides an LD that is selectively formed on a compound semiconductor substrate using an insulation separation technique used in a non-contact IC, such as a laser annealing technique, and an LD that is separated through an insulator to control the LD. The IC part of the electrical system that is driven by the IC is provided as a planar structure.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a cross-sectional structure of a planar compound semiconductor device according to a first embodiment of the present invention. In Figure 3 Man,
301 indicates a single crystal n-type InP substrate. 302baInG
The quaternary layer of aAsP is called the active layer, and the original confinement is performed. 303 is P type InP layer 22921
called layers. 304 is a P-type InGaAs P layer and is called a camp layer. 306 indicates an insulating film. 30
The figure shows the polycrystalline silicon layer deposited on the insulating film.

307 has been partially single-crystalized by irradiation with energy rays.

The manufacturing method of the embodiment according to the present invention will be explained below in order according to FIG.

As shown in FIG. 3A, an InGaAsP quaternary layer 302.2292 called an active layer is formed on an n-type InP substrate 301.
A P-type InP layer 303 called a first layer and a P-type InGaAsP layer 304 called a camp layer are epitaxially grown in sequence. After that, the insulation coating 306, for example, S10□
Alternatively, deposit Si3N4 or the like. A photosensitive resist is applied and a pattern is created using photolithography.
The insulating film 305 is selectively etched.

As shown in FIG. 3B, using the insulating film 305 as a mask, the camp layer 304, the P cladding layer 303, and the active layer 3 are
02 is selectively etched.

Etching may be dry etching using OF4 or Ca14 gas, or wet etching as shown below.

Use etching. In the case of wet etching, a bromine-based, hydrochloric acid-based, sulfuric acid-based, nitric acid-based etching solution is used. As shown in FIG. 3B, a protrusion "15" is selectively used on the n-type InP substrate 301, and this is used as an LD section.

Next, as shown in FIG. 3G, an insulating film 306 is formed to cover the above-mentioned convex portion (LD portion).

Since the insulating film 306 is also formed on the vertical portion of the convex portion, the CV
Deposit using method D. In this case, rather than depositing the above-mentioned insulating film 306 with a normal pressure CvD device, a reduced pressure CvD device is used.
It is preferable to deposit with a D apparatus. The insulating film 306 is made of Si
O2 or S 13 N4 may be used.

After depositing the insulating film 306, a silicon layer 3 is formed by vapor phase growth.
07 Gold grow. Silicon layer 301J: This is a polycrystalline silicon layer because it is grown in a vapor phase on the e-edge film. Alternatively, the polycrystalline silicon layer 307 may be deposited by CVD by heating the InP substrate at a low temperature to the extent that the InP crystal does not thermally decompose. After depositing the polycrystalline silicon layer 307, the polycrystalline silicon layer 307i deposited on the upper part of the LD portion is etched to flatten the surface. Etching of the polycrystalline silicon layer is carried out by dry etching using CF, system gas, or υ.
This is done using wet etching using a noic acid system. After that, a small amount of dry etching is performed, and then the insulating film above the LD section is etched to lift off the convex portion of the polycrystalline silicon layer, thereby flattening the surface.

After that, on the polycrystalline silicon layer 307, the filj necessary for electrical devices (transistors, resistors, etc.) is selectively or the entire surface is made into a single crystal by irradiation with energy rays, as shown in Figure 3. Single crystal layer 308
get. As an energy beam, an Ar laser with a continuous output of about 10 W is used as a spot with a beam diameter of 20 to 30 μm at a beam scanning speed of 10 to 20 cm/sea.
By setting the beam overlap to 60% and 1 degree, it is possible to partially produce a good single crystal layer.

In this way, the single crystal silicon layer 308 can be selectively formed on the InP substrate 301, so MO3I can be formed into the single crystal silicon layer 308 by ion implantation or the like.
- Lano resistors, resistors, etc. can be formed as required.

These electric devices can be fully used to control and drive LDs configured on the same substrate.

FIG. 4 shows a second embodiment based on the present invention. Reference numeral 301 indicates an n-type 1nP substrate. 3o2 is an InGaAsP quaternary layer (active layer), 303 is a P-type InP layer (P Clarado layer)
, 304 indicate a P-type InGaAsP layer (crystal layer). These are formed continuously by nitrile growth. The LD portion is selectively formed using an etching liquid or the like which has undergone M-temperature. Thereafter, an insulating film 306 f is formed, and an n-type polycrystalline silicon layer 307 is selectively deposited. The polycrystalline silicon layer is irradiated with energy m and re-irradiated depending on the needs of the constituting aerobic element. Crystallized single crystal N30
8f, (Formation. Form a P well 309 by ion implantation or the like. Similarly, form a source/drain region 310 with a p-type dopant. Form a source/drain region 311 with an n-type dopant. Each gate oxide film Electrodes 317 and 318 are formed via 312. Source and drain acids 41314315+316 are formed, and an electrode 314 of the LD portion is formed. 319 indicates an electrode on the back surface.

313 indicates an insulating coating.

FIG. 5 shows an equivalent (b) path of the cross-sectional structural diagram shown in FIG. In FIG. 6, the same numbers as in FIG. 4 indicate the same parts. In this embodiment, the MOS transistor has a C-MO3 structure. It is optional to form an electric element in a single-crystal silicon layer that is electrically isolated from the LD portion. In this embodiment, a G-MO5 structure of a pi-lateral switch that can drive the LD with low impedance is adopted.

In addition, as an example regarding non-invention, InP-InGaA
The explanation was given using the sP quaternary system as an example, but GaAs-A
It goes without saying that it can be similarly formed as a ternary system of lGaAs. In addition, even if the silicon layer formed separately from the LD section is an InP layer or GaAs J-, it is possible to form an air-core element. Further, although an example in which transistors are integrated has been shown as an example, it is also possible to form a light receiving section by forming a PiN diode or an APD (avalanche photodiode) in another silicon layer. Also, L
Other light emitting elements such as LEDs (light emitting diodes) may be formed in place of D.

Effects of the Invention As described above, the present invention has the following advantages: (1) LD, a transistor as its driving element, PiN as a light receiving element, and APD can be completely separated electrically. Being able to separate them increases the degree of freedom in designing each part independently, creating a completely new structure that is not available in conventional integrated structures.

(2) Also, since it has a planar structure, the manufacturing process is easier than the conventional integrated structure.

(3) By using a silicon layer, conventional silicon IC
This is extremely advantageous in terms of the manufacturing process, as the technology developed in the above can be directly applied to electrical devices.

(4) By combining the light emitting characteristics of compound semiconductors with silicon's almost completed device technology, we have realized the realization of ICs for electrical-to-optical conversion and optical-to-electrical conversion with unprecedented electrical circuitry. It is something to do.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional LD-integrated IC structure, FIG. 2 is an equivalent circuit diagram of the IC structure shown in FIG. The manufacturing process diagram of the structure, FIG.
FIG. 5 is a cross-sectional view of an integrated re structure of an LD and a transistor according to an embodiment, and FIG. 5 is an equivalent circuit diagram of the cross-sectional view shown in FIG. 4. 301... Compound semiconductor substrate, 302, 303
゜304... Compound semiconductor layer, 305 s
306. 313... Insulating coating, 307, 308...
・7 Recon layer, 309, 310, 311・Mountain...Ion implantation layer, 314, 315. 316. 317. 3
18. 319...Resistive electrode. Names of the 11 JJ members Patent attorney Satoshi Nakao Male Heart is 1
Figure 1 Figure 1 Figure 2 Figure 3 Figure 4

Claims (4)

[Claims] (1) A semiconductor light-emitting device selectively formed on a compound semiconductor substrate, and a semiconductor layer formed with an insulator interposed between the substrate and the semiconductor light-emitting device, and an electric element is integrated on the semiconductor layer, and the A compound semiconductor device that constitutes an electrical/optical integrated circuit that controls and drives semiconductor light emitting devices. (2) A compound semiconductor device according to claim 1, characterized in that a light receiving element and an electric element are integrated in a semiconductor layer. (3) The compound semiconductor device according to claim 1, wherein the semiconductor layer is a silicon layer or a compound semicircular layer. (4) a step of performing a plurality of epitaxial growths to form a double heterostructure on a compound semiconductor substrate; a step of selectively leaving an insulating film on the epitaxial layer and selectively etching the plurality of epitaxial layers; A step of depositing an insulating film on the entire surface of the substrate including the side surfaces of the convex portion formed by the etching, a step of growing a semiconductor layer on the insulating film, and a step of growing a semiconductor layer on the top of the convex portion formed by the etching. The method includes a step of etching and planarizing a semiconductor layer, a step of selectively irradiating the semiconductor layer with an energy beam or the like to form a single crystal, and a step of forming an electric element in the single crystal layer. A method for manufacturing a compound semiconductor device.