JPS59222986A - Manufacture of compound semiconductor element - Google Patents

Abstract

PURPOSE:To isolate a plurality of electrical elements and a LD, and to improve the degree of integration by selectively etching a buried epitaxial layer up to a substrate, burying polycrystalline semiconductor layers into recessed sections, flattening the surfaces and isolating and diffusing the polycrystalline semiconductor layers to the buried epitaxial layer. CONSTITUTION:An InGaAsP four-element layer 302 called an active layer, a P type InP layer 303 called a P clad layer and a P type InGaAsP layer 304 called a cap layer are grown on an N type InP substrate 301 in succession in an epitaxial manner. The cap layer 304, the P clad layer 303 and the active layer 302 are etched selectively. A projecting section is formed selectively on the N type InP substrate 301, and used as a LD section. Layers are buried and grown in the epitaxial manner so as to bury the projecting section (the LD section). The buried epitaxial layers 306 and 307 are etched selectively up to the substrate 301 to form recessed sections. Polycrystalline silicon layers 309 are buried in the recessed sections. An insulating film 320 is shaped apart from an insulating film 310 used for a mask for a P type diffusion, and an opening is bored selectively and a base is diffused 312.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integrated structure of a light emitting element such as a semiconductor laser (hereinafter abbreviated as LD) and its driving element, and its problems. Since it is possible to transmit high-density information such as optical communication, its development has been actively carried out recently.

In optical communications, LI) is an element that converts electrical signals into optical signals. Particularly recently, the development of integrated circuits (hereinafter abbreviated as ICs) that integrate electrical signal processing circuits and LDs has been attracting attention.

As a conventional integrated IC structure, one in which a junction type FIT and I and D are integrated into an IC has been announced. This structure is shown in FIG. In Fig. 1, 1 is a semi-insulating medullary substrate, 2 is an n-type stratum layer, 3 is an n-type ApaAs layer, 4 is an n-type stratiform layer, and 5 is a p-type A-shaped layer. 6 is an insulating film, 7 is a conductive metal, 8 is a source electrode, 9 is a gate electrode, 10 is a drain electrode, 11 is a gate diffusion layer, and 12 is a p-type high concentration layer.

FIG. 2 shows an equivalent circuit of the element cross-sectional structure shown in FIG. 1. The same numbers as in FIG. 1 indicate the same names. This structure is not a planar type (the FgT part is selectively etched with the n-type GaAs layer 2-1, or the LD part is selectively grown epitaxially). The formation process is difficult.Furthermore,
This is a difficult structure to electrically separate electrical elements such as a plurality of transistors and resistors into an IC.

Purpose of the Invention In view of the conventional problems as described above, the present invention provides a method for manufacturing a compound semiconductor device in which a plurality of electric devices and an LD are electrically separated from each other and integrated into an IC with a planar structure. It is something.

Structure of the Invention The present invention provides an LD selectively formed on a compound semiconductor substrate.
, 4. Regarding a buried structure LD, a buried epitaxial layer is used to make an electric element into an IC, and the buried epitaxial layer is selectively etched down to the substrate, and a polycrystalline semiconductor layer is buried in the fourth part through an insulating film, and the surface is flattened. A plurality of electric elements and the LD are electrically isolated by performing isolation diffusion in the epitaxial layer, thereby providing a planar structure.

DESCRIPTION OF EMBODIMENTS First, FIG. 3(F) shows a cross-sectional structure of a compound semiconductor device having a planar structure according to an embodiment of the present invention. Figure 3 (F)
By smell, 3o1 does not indicate an n-type InP substrate.

A quaternary layer 302 of InGaAsP is called an active layer and is used to trap light. Although not shown in the drawings, optical waveguide layers are formed above and below the active layer described above;
It is fully possible to form a diffraction grating there. 303 is a P-type InP layer and is called a P cladding layer. 304 is a P mInGaAsP layer called a cap layer. 306 is a buried epitaxial layer, which is a P-type InP layer. 307 is a buried epitaxial layer, which is an n-type InP layer.

Reference numeral 308 indicates an insulating film for insulation isolation. 309 indicates a polycrystalline layer/layer embedded for insulation isolation.

310ii shows an insulating film for forming electrode wiring.

Reference numeral 311 indicates a P-type diffusion layer for electrically isolating the buried n-type InP layer 307 described above. Reference numeral 312 indicates a P-type diffusion layer formed in a separate island of the n-type InP layer, and indicates a base region of the transistor. 313 indicates an n-type diffused emitter region in the base region. 314 indicates the anode electrode of the LD section.

Reference numeral 316 denotes a separation electrode that applies the lowest potential to electrically isolate the island-on-type InP layer 307 and the cathode 301 of the LD. 316 is a collector electrode, 317
318 is an emitter electrode, 318 is a base electrode, and 319 is a cathode electrode of the LD.

The manufacturing method of the embodiment according to the present invention will be explained below in order according to FIG. 3.

As shown in FIG. 3(A), an InGaAaP quaternary layer 302 called an active layer is formed on an n-type InP substrate 301. P-type InP layer 303 called P cladding layer. A P-type rncyaAsP layer 304 called a cap layer is epitaxially grown in sequence. As mentioned above, it is not only possible to epitaxially grow an n-type InP layer as an n-cladding layer under the active layer 302 or a quaternary layer as an optical waveguide layer above or below the active layer, but also to grow the quaternary layer as an optical waveguide layer. Reflection of light by forming a diffraction grating.

It is also possible to cause refraction.

After the epitaxial growth is completed, an insulating film 305 such as 5i02 or Si3N4 is deposited, a photosensitive lens is applied, a pattern is formed by a tsumetri-no-blowie, and the insulating film 306 is selectively etched.

As shown in FIG. 3(B), the cap layer 304. The P cladding layer 303 and the active layer 302 are selectively etched. For etching, OF4 or CC,111, dry etching using a gas system, or the following wet etching is used. In the case of wet etching, a bromine-based, hydrochloric acid-based, sulfuric acid-based, nitric acid-based etching solution is used. As shown in FIG. 3(B), a convex portion is selectively provided on the n-type 1nP substrate 301 and is used as an LD portion. Next, the above-mentioned convex portion (LD
Embedded epitaxial growth is performed to embed part). The buried epitaxial layer is first [P-type InP layer, then n
It is an InP type layer. When the liquid phase epitaxial method is used, epitaxial growth is not performed on the upper part of the insulating J-shaped layer 305.

Next, as shown in FIG. 3C, the buried epitaxial layers 306 and 307 described above are selectively etched using the substrate 3o1 to form four parts. As the etching method, both dry and wet etching mentioned above can be used. After selectively forming the recesses, an insulating film 30B is deposited over the entire surface of the recesses, including the side and bottom surfaces. In order to improve the coverage of the above-mentioned insulating film 308 at the steps, low pressure CVD is performed.
Just use the law. The insulating film 308 may be made of SiO, Si3N4, or the like. Note that Si3N4, which has approximately the same coefficient of thermal expansion as InP, is somewhat preferable.

As shown in FIG. 3), a polycrystalline silicon layer 309 is buried in the selectively formed recesses. Polycrystalline silicon can be deposited by heating the substrate at a temperature lower than the thermal decomposition temperature of nP and depositing it by CVD.

The polycrystalline silicon layer deposited in areas other than the recessed portions can be removed by dry etching using a gas system such as 02 and ay2c4 through a photosensitive resist, and the surface can be flattened. At this time, the etching of the insulating film 30B formed on the surface can be used to detect the end point of etching the polycrystalline silicon layer. Alternatively, wet etching may be performed using a phosphoric acid or nitric acid based etching solution.

As shown in FIG. 3(E), an insulating film 310 as a diffusion mask is deposited on the surface. After that, holes are selectively opened in the insulating film 310 and Zn, Cd, etc. are deposited on the P-type InP layer 3o6.
Diffusion at t-. In this way, the n-type 1nP layer 307, which is the buried epitaxial layer described above, is selectively separated into islands. The n-type InP layer 307 separated into islands can be electrically separated by keeping the P-type InP layer 306 including the P-diffusion layer described above at the lowest potential and applying a reverse bias voltage. Moreover, since it can be electrically isolated from the n-type InP substrate 301, the island-shaped n-type InP layer 307 can be electrically isolated from the LD section. Island-shaped n-type In that can be electrically isolated
In the P layer 307, transistors, resistors, capacitors, etc. can be formed by applying conventional silicon IC manufacturing techniques.

FIG. 3 <y> shows a cross-sectional structure of an element when bipolar transistors are integrated. An insulating film 320 is formed separately from the insulating film 310 used as the P-type diffusion mask, and base diffusion 312 is performed by selectively opening holes. Although the base layer in this case is of P type, it is Zn.

Alternatively, impurities such as Cd, Be, Mg, etc. are used. Alternatively, ion implantation may be performed without using thermal diffusion.Next, emitter diffusion 313 is performed. In this case, the emitter layer is n
Since it is a type, it is formed by thermal diffusion or ion implantation using impurities such as S, Se, Te, etc. Although a resistor is not formed in this embodiment, it can be made using a base diffusion layer. An insulating film 320 is formed for forming electrode wiring, and holes are selectively opened to form electrode wiring 314. 315. 31
6,317°318 is formed. Au/G as electrode
e, Au/Zn.

Vapor deposition is performed using Ti/Au, Au/Be, Au/Sn, etc., and the wiring shape is created using photolithography technology. Next, an electrode 319 is formed on the n-type InP substrate 301 using a similar electrode cutting process.

The manufacturing method of the embodiment of the present invention has been described above.

Next, voltage application in the embodiment according to the present invention shown in FIG. 3(F) will be described. As described above, the P-type InP layer 306 including the isolation diffusion 311 is kept at the lowest potential than any other semiconductor layer. FIG. 4 shows an equivalent circuit of the cross-sectional structure of the integrated device according to the embodiment of the present invention shown in FIG. As described above, by setting the electrode 316 to the lowest potential, the PN junction is reverse biased and the transistor and LD are separated.

In this embodiment, a polar transistor may be used, and 7c may be a J-FET, MOS, or FET. 1. It is also possible to form a receiver and an element in a separate island-like portion. Further, although the emitter-base junction is a homojunction, it is also possible to improve the injection efficiency by using a peterojunction. In the example, InP-based ZIrIGaAsP
Although this is a system, it goes without saying that this may be a connected/A%aAs system or may be a mixed crystal system of other compounds.

Effects of the Invention (1) The LD and its control, the transistor as the drive system, the PiN as the light receiving element, the -mu PD element, etc. can be completely separated electrically. The ability to separate them increases the degree of freedom in designing each component independently, and dramatically improves the degree of integration with a completely new structure that is not available in conventional integrated structures.

(2) If a distributed feedback type or distributed reflection type I and D are configured in combination with an optical waveguide and a diffraction grating, the chip size does not depend on the resonator length as in the Fabry-Bérot type. By using this manufacturing method, the degree of integration of electrical elements can be dramatically improved.

(3) Since it has a planar structure, there is no disconnection of the electrode wiring at the stepped portion unlike in the conventional integrated structure. Further, the manufacturing process is easy, as special etching for separating the LD portion and the electric element portion is not required.

(4) Separation from the LD by a dielectric material facilitates high-speed modulation of the LD because junction capacitance can be reduced.

(5) Since a compound semiconductor layer separated into islands can be used for an electric element, it is easy to form a high-speed electric element.

(6) Electro-optical
It is possible to realize an opto-electrical optical integrated circuit.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional LD-integrated IC structure, Figure 2 is an equivalent circuit diagram of the IC structure shown in Figure 1, and Figures 3 (A) to (
Figure 4 is an equivalent circuit diagram of the IC structure shown in Figure 3 (Fig. 3). 301... Compound semiconductor substrate, 302 ,303
j304.306, 307... Compound semiconductor layer, 305.308, 310, 320... Insulating film, 309... Polycrystalline semiconductor layer, 311...
... Separation diffusion layer, 312 ... Base diffusion layer, 3
13...Emitter diffusion layer, 314.316.
316.317) 318.319...Resistive electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure t Figure 2

Claims (1)

[Scope of Claims] (1) A step of performing a plurality of epitaxial growths to form a double Peter structure on a compound semiconductor substrate, and selectively leaving an insulating film on the epitaxial layer to selectively grow the plurality of epitaxial layers. a step of performing a plurality of epitaxial growths to bury the side surfaces of the convex portions formed by the etching; a step of selectively etching the buried epitaxial layer to the substrate; A step of depositing an insulating film on the entire surface including the side and bottom surfaces of the recess formed by etching, a step of burying a polycrystalline semiconductor layer in the recess and flattening the surface, and a step of flattening the surface of the buried epitaxial layer surrounded by the polycrystalline semiconductor layer. A method for manufacturing a compound semiconductor device, comprising the steps of performing isolation diffusion within a layer, and forming an electric element within a buried epitaxial layer surrounded by the isolation diffusion. (b) Method 9 for manufacturing a compound semiconductor device according to claim 1, characterized in that the polycrystalline semiconductor layer is a polycrystalline silicon layer (3) The step of performing separation and diffusion selects a buried epitaxial layer. Claim 1, characterized in that the method further comprises the steps of: etching the recess, forming an insulating film on the surface including the recess formed by the step, and burying a polycrystalline semiconductor layer in the recess. A method for manufacturing a compound semiconductor device according to .