JPS61108187A - Semiconductor photoelectronic device - Google Patents

Semiconductor photoelectronic device

Info

Publication number
JPS61108187A
JPS61108187A JP59230947A JP23094784A JPS61108187A JP S61108187 A JPS61108187 A JP S61108187A JP 59230947 A JP59230947 A JP 59230947A JP 23094784 A JP23094784 A JP 23094784A JP S61108187 A JPS61108187 A JP S61108187A
Authority
JP
Japan
Prior art keywords
thin film
single crystal
compound semiconductor
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59230947A
Other languages
Japanese (ja)
Inventor
Hiroshi Komatsu
博志 小松
Hiroyuki Oshima
弘之 大島
Hideaki Iwano
岩野 英明
Yoshifumi Tsunekawa
吉文 恒川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP59230947A priority Critical patent/JPS61108187A/en
Publication of JPS61108187A publication Critical patent/JPS61108187A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/026Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0262Photo-diodes, e.g. transceiver devices, bidirectional devices
    • H01S5/0264Photo-diodes, e.g. transceiver devices, bidirectional devices for monitoring the laser-output

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Photovoltaic Devices (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To integrate a light-emitting element, a light-receiving element and an electronic element on a single substrate and to obtain an photoelectronic device with high utility, by selectively utilizing the upper or lower face of the Si single-crystal substrate and by superposing thereon an amorphous insulation film, a thin film of a compound semiconductor and multilayer thin film of said compound semiconductor. CONSTITUTION:An SiO2 film 2 on an N type Si substrate 1 is provided, on the surface thereof, with rectangular stripe grooves with a depth of 10-10<5>Angstrom and a width of 0.1-10mum by means of etching. Amorphous or polycrystalline N type GaAs 3 is then deposited thereon by the vapor growth, and is heated so that it is rearranged along the grooves and that single crystal is caused to grow. Subsequently, an N type AlGaAs layer 4, an AlGaAS active layer 5, a P type AlGaAs layer 6 and a P type GaAs layer 8 are epitaxially deposited to form a laser diode. An N<+> layer 10 is provided in the P<+> layer 9 of the substrate 1 to form an NPN transistor. These are provided with protective films 11 and 12, electrodes 8, 13 and 14 and wiring 15, respectively. According to this construction, the intensity of laser beams can be controlled with the base current in the transistor. Further, it is also possible to integrate a laser element, a light-receiving element and a driving element on one face while integrating a driving element and a signal processing arithmatical element on the opposite face.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体光電子装置の基板構造と機部に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a substrate structure and a mechanical part of a semiconductor optoelectronic device.

〔従来の技術〕[Conventional technology]

光の高速性、多重性、精密性等の特長を生かして、電子
技術の代わシに情報伝送や情報処理に光技術が導入これ
始めている。例えば、光ファイバとレーザ光を利用して
の長距離光通信技術や、光ディスクと半導体レーザを組
み合わせた音声並びに画像の再生技術などはその代表的
な例である。
Taking advantage of the features of light, such as its high speed, multiplicity, and precision, optical technology is beginning to be introduced in place of electronic technology for information transmission and processing. Typical examples include long-distance optical communication technology that uses optical fibers and laser light, and audio and image reproduction technology that combines optical disks and semiconductor lasers.

これらの光システムにおいては、レーザ光等を発する発
光素子と、伝送光信号を電気信号に変換する受光素子と
、それらの発光・受光素子を駆動する電子装置はいわば
光システムの心臓部である。
In these optical systems, a light-emitting element that emits laser light or the like, a light-receiving element that converts a transmitted optical signal into an electrical signal, and an electronic device that drives these light-emitting and light-receiving elements are the heart of the optical system.

システムの小型化、高機能化、高速化などのために、こ
れらの光素子と電子装置が一体化ばれ始めている。すな
わち、半導体レーザ(LD)やフォトダイオード(PD
)と電界効果トランジスタ(F E T、)を同一半導
体基板表面に作シ、L D+F DをF]1liTで駆
動している。例えば、昭和59年度電通学会講演論文集
4−28、講演番号974のようにりん化インジウム化
合物半導体基板上に、インジウム・ガリウム・ひ素・シ
ん系の化合物半導体よ構成るLDと、りん化インジウム
FETを作製し、レーザ光をFF1Tで変調している。
These optical elements and electronic devices are beginning to be integrated in order to make systems smaller, more sophisticated, and faster. In other words, semiconductor lasers (LDs) and photodiodes (PDs)
) and a field effect transistor (FET, ) are fabricated on the same semiconductor substrate surface, and L D+F D is driven by F]1liT. For example, as shown in IEICE Proceedings 4-28, Lecture No. 974, an LD composed of an indium-gallium-arsenic-synphorus compound semiconductor and an indium phosphide compound semiconductor are mounted on an indium phosphide compound semiconductor substrate. An FET was fabricated and the laser beam was modulated by FF1T.

また同論文集4−24、講演番号970のようにフォト
ダイオードとFETを同一基板表面に作製している。こ
のよ)な半導体光電子装置に用いる半導体基板は従来り
ん化インジウム(工η、P)基板やひ化ガリウム(Ga
As)基板が主に使われている。これらの基板上には特
性の良い半導体レーザ素子を作υ易い。
Also, as in the same collection of papers 4-24, lecture number 970, a photodiode and a FET are fabricated on the same substrate surface. Semiconductor substrates used in such semiconductor optoelectronic devices have conventionally been indium phosphide (P) substrates and gallium arsenide (Ga) substrates.
As) substrates are mainly used. It is easy to fabricate semiconductor laser devices with good characteristics on these substrates.

一方、シリコン基板上に化合物半導体を成長させて、半
導体光電子装置を作製しているものもある。昭和59年
度電通学会講演論文集2−17、講演番号255ではシ
リコン単結晶基板上にゲルマニウムをエピタキシャル成
長はせ、づらにその表面にひ化ガリウムをエピタキシャ
ル成長させて、そのひ化ガリウムにFE’Tを作ってい
る。また、The 16th Con、ference
on Bolicl 5tate Devicesan
d Materials 1984、講演番号C11で
は前述の例と同様にゲルマニウムを介してシリコン単結
晶・基板上にひ化ガリウムを結晶成長シせたのも、その
表面にレーザダイオードを作りパルス発揚ζせている。
On the other hand, some semiconductor optoelectronic devices are manufactured by growing compound semiconductors on silicon substrates. In 1985 IEICE Conference Proceedings 2-17, Lecture No. 255, germanium was epitaxially grown on a silicon single crystal substrate, gallium arsenide was epitaxially grown on the surface of the silicon single crystal substrate, and FE'T was applied to the gallium arsenide. I'm making it. Also, The 16th Con, ference
on Bolicl 5tate Devicesan
d Materials 1984, lecture number C11, similarly to the previous example, gallium arsenide was grown on a silicon single crystal substrate via germanium, and a laser diode was created on the surface to emit pulses.

〔発明が解決しよ)とする問題点〕[Problems that the invention aims to solve]

しかし、前述の従来技術は次のような問題点をもつ。す
なわち、化合物半導体を基板にしたF ’FiTなどの
電子素子には駆動電圧を高くできない、M:r s (
Metal−■nsrblator−8emicond
uctor)界面に準位が多く閾値電圧を制御しにくい
、正孔の移動度が小ζい、禁制帯幅が広すぎるといった
特性を左右する問題点の他に、安定性・信頼性に乏しい
といった問題点がある。また、化合物半導体基板自体に
も、結晶性が悪い、基板価格が高い、割れやすい、大口
径化が困難といった問題がある。したがって従来の化合
物半導体基板を用いた半導体光電子装置には実用に際し
十分満足できる特性のものが得られていない。
However, the above-mentioned conventional technology has the following problems. In other words, it is not possible to increase the driving voltage for electronic devices such as F'FiT using a compound semiconductor as a substrate, and M:rs (
Metal-■nsrbrator-8emicond
In addition to problems that affect the characteristics, such as the large number of levels at the interface, making it difficult to control the threshold voltage, low hole mobility, and too wide a forbidden band width, there are also problems such as poor stability and reliability. There is a problem. Further, the compound semiconductor substrate itself has problems such as poor crystallinity, high substrate price, easy breakage, and difficulty in increasing the diameter. Therefore, semiconductor optoelectronic devices using conventional compound semiconductor substrates do not have sufficiently satisfactory characteristics for practical use.

シリコン単結晶基板を用いたものについては、シリコン
単結晶とひ化ガリウム単結晶の格子路数に4俤以上の差
があるため、それらの結晶間に格子不整合が生じる。そ
のためひ化ガリウム単結晶に格子歪入や格子欠陥が起き
、ひ化ガリウム単結晶上の電子素子や光素子の特性に良
いものが得られず、信頼性および再現性に欠けるといっ
た問題点があった。
For those using a silicon single crystal substrate, there is a difference of 4 or more in the number of lattice paths between the silicon single crystal and the gallium arsenide single crystal, resulting in lattice mismatch between these crystals. As a result, lattice distortion and lattice defects occur in gallium arsenide single crystals, making it difficult to obtain good characteristics for electronic and optical devices made of gallium arsenide single crystals, resulting in problems such as a lack of reliability and reproducibility. Ta.

そこで本発明はこのような問題点を解決するためのもの
で、その目的とするところは、特性に優れ信頼性の高い
発光素子、受光素子および電子素子を同一基板上に集積
化して、実用性の高い半導体光電子装置を提供するとこ
ろにある。
The present invention is intended to solve these problems, and its purpose is to integrate a light-emitting element, a light-receiving element, and an electronic element with excellent characteristics and high reliability on the same substrate, thereby making it practical. The purpose of the present invention is to provide a semiconductor optoelectronic device with high performance.

r問題点を解決するための手段〕 本発明の半導体光電子装置はシリコン単結晶基板と、該
シリコン単結晶基板の表又は裏面の全体又は一部に存在
する非晶質絶縁膜と、該非晶質絶縁膜表面の全体又は一
部に存在する化合物半導体薄膜と該化合物半導体薄膜表
面の全体又は一部に存在する多層化合物半導体薄膜から
成り、前記化合物半導体薄膜はグラフオエピタキシャル
成長法により形成した単結晶薄膜より成り、前記多層化
合物半導体薄膜はエピタキシャル成長法により形成した
多層の単結晶薄膜より成り、前記シリコン単結晶基板と
前記化合物半導体薄膜と、前記多層化合物半導体薄膜を
発光素子又は受光素子の構成材料として用い、前記シリ
コン単結晶基板の衣又は裏面にシリコン半導体より成る
発光素子又は受光素子を作動せしめる電子素子と、信号
の処理および演算の機能を有する電子回路を形成したこ
とを特徴としている。
Means for Solving Problems] The semiconductor optoelectronic device of the present invention includes a silicon single crystal substrate, an amorphous insulating film existing on the whole or a part of the front or back surface of the silicon single crystal substrate, and the amorphous It consists of a compound semiconductor thin film existing on the whole or part of the surface of the insulating film and a multilayer compound semiconductor thin film existing on the whole or part of the surface of the compound semiconductor thin film, and the compound semiconductor thin film is a single crystal thin film formed by a grapho-epitaxial growth method. The multilayer compound semiconductor thin film is made of a multilayer single crystal thin film formed by an epitaxial growth method, and the silicon single crystal substrate, the compound semiconductor thin film, and the multilayer compound semiconductor thin film are used as constituent materials of a light emitting element or a light receiving element. , an electronic element for operating a light emitting element or a light receiving element made of a silicon semiconductor, and an electronic circuit having signal processing and arithmetic functions are formed on the outer surface or the back surface of the silicon single crystal substrate.

〔実施例1〕 第1図に本発明の一実施例を示す。第1図において、1
け面方向が(100)で不純物濃度が1015儒1程度
のn形シリコン単結晶基板である。2け前記n形シリコ
ン基板表面に熱酸化法または化学気相成長法あるいはス
パッタ法などによ多形成した厚き数ミクロンのSi 0
2 (二酸化シリコン)よシ成る非晶質絶縁膜である。
[Embodiment 1] FIG. 1 shows an embodiment of the present invention. In Figure 1, 1
It is an n-type silicon single crystal substrate with a (100) plane direction and an impurity concentration of about 1015 F1. A layer of Si 0 of several microns thick is formed on the surface of the n-type silicon substrate by thermal oxidation, chemical vapor deposition, or sputtering.
It is an amorphous insulating film made of 2 (silicon dioxide).

この非晶質絶縁膜の表面に深濾10〜1’ 0000オ
ングストロ一ム程度、幅01〜10ミクロン稈度の矩形
のストライプ溝を0.1〜10ミクロンピッチにエツチ
ングによυ形成する。エツチング法にけ、フッ化水素系
のエッチャントを用いる湿式1ヴチング法やフレオン(
OF4)等を反応性ガスとして用いる反応性イオンエヴ
チング法などがある。溝の長ζ方向は任意である。非晶
質絶縁膜として本実施例ではSj O□を使用したが、
その仙に窒化シリコン(SixNy)、アルミナ(1s
120s )等が使用できる。3は前記非晶質絶縁膜上
にグラフオエピタキシャル成長したn形のひ化ガリウム
単結晶薄膜である。ひ化ガリウム単結晶のグラフオエピ
タキシャル成長は、まず気相成長法あるいは有機金属気
相成長法あるいけ分子線エピタキシャル法などにより、
非晶質あるいけ多結晶のひ化ガリウム薄膜を2に示すよ
うな溝のあるSi O2膜等の表面に堆積させ、次にレ
ーザ又は赤外線ランプ又はヒーター等を用いて加熱し、
ひ化ガリウムを溝に沿って再配列きせることで単結晶成
長できる。グラフオエピタキシャル成長させたひ化ガリ
ウム単結晶の膜厚は数〜数十ミクロンである。ひ化ガリ
ウムの表面上での単結晶性を良くするために、グラフオ
エピタキシャルひ化ガリウム結晶表面に液相成長法や気
相成長法など熱平衡成長法により模質の良い単結晶ひ化
ガリウムを成長づせても良い。グラフオエピタキシャル
法はひ化ガリウムだけでなく、他の冒−V族系化合物半
導体、U−Vl族系化合物半導体、■族化合物半導体、
シリコンおよびその他の結晶の成長に活用できる。第1
図の4〜8は3を含めてダブルへテロ構造の?)−n接
合半導体レーザを構成している化合物半導体薄膜である
。4けn形のアルミニウム・ガリウム・ひ素早結晶より
成る第一クラ・ソド層、5は低不純物濃度のアルミニウ
ム会ガリウム・ひ素早結晶より成る活性層、6はp形の
アルミニウムーガリウム・ひ素早結晶より成る第二クラ
ッド層、7はn形のガリウム・ひ素よシ成る雷、流制限
層、8はp形のガリウム・ひ素より成る表面キャップ層
である。本実施例ではダブルへテロ構造の半導体レーザ
ダイオードを作製しているが、この仙に分布帰還形レー
ザ、多重量子井戸又は超格子レーザ等の作製も可能であ
る。16は8のp形のガリウム・ひ素層よジオ−ミック
コンタクトをとるための八u −Zn/八Uへり成る電
極である。
On the surface of this amorphous insulating film, rectangular stripe grooves with a depth of about 10 to 1'0000 angstroms and a width of 01 to 10 microns in culmability are formed by etching at a pitch of 0.1 to 10 microns. In the etching method, wet etching method using hydrogen fluoride-based etchant and Freon (
There is a reactive ion etching method using OF4) etc. as a reactive gas. The length ζ direction of the groove is arbitrary. In this example, SjO□ was used as the amorphous insulating film, but
Silicon nitride (SixNy), alumina (1s
120s) etc. can be used. 3 is an n-type gallium arsenide single crystal thin film grown graphoepitaxially on the amorphous insulating film. The graphite epitaxial growth of gallium arsenide single crystals is first carried out by vapor phase epitaxy, organometallic vapor phase epitaxy, molecular beam epitaxial method, etc.
An amorphous or polycrystalline gallium arsenide thin film is deposited on the surface of a grooved SiO2 film as shown in 2, and then heated using a laser, an infrared lamp, a heater, etc.
Single crystals can be grown by rearranging gallium arsenide along grooves. The thickness of a graphoepitaxially grown gallium arsenide single crystal is several to several tens of microns. In order to improve the single crystallinity on the surface of gallium arsenide, single crystal gallium arsenide with a good pattern is grown on the surface of the graphoepitaxial gallium arsenide crystal by a thermal equilibrium growth method such as liquid phase growth or vapor phase growth. You can let it grow. The graphoepitaxial method can be applied not only to gallium arsenide, but also to other group V compound semiconductors, U-Vl group compound semiconductors, group II compound semiconductors,
Can be used to grow silicon and other crystals. 1st
Are numbers 4 to 8 in the diagram, including number 3, double heterostructures? )-N junction semiconductor laser is a compound semiconductor thin film. 4 is the first crystal layer consisting of n-type aluminum gallium arsenide fast crystals, 5 is an active layer consisting of aluminum gallium arsenide fast crystals with a low impurity concentration, and 6 is a p-type aluminum gallium arsenide fast crystal. A second cladding layer made of crystal, 7 a lightning current restriction layer made of n-type gallium arsenide, and 8 a surface cap layer made of p-type gallium arsenide. In this embodiment, a double heterostructure semiconductor laser diode is manufactured, but it is also possible to manufacture a distributed feedback laser, a multiple quantum well laser, a superlattice laser, or the like. Reference numeral 16 denotes an electrode consisting of 8U-Zn/8U edges for making geometric contact with the p-type gallium-arsenide layer of 8.

9は外形シリコン単結晶基板内陀不純物導入して形成し
たp+形層、10は前述のp形層中に不純物導入して形
成したn+形層である。1.9および二52.− −くし4 10fn7+wWバイポーラトランジスタを形成する。
9 is a p+ type layer formed by introducing impurities into the external silicon single crystal substrate, and 10 is an n+ type layer formed by introducing impurities into the aforementioned p type layer. 1.9 and 252. - -Comb 4 10fn7+wW bipolar transistor is formed.

すなわち1がコレクタ、9がベース、10がエミ9夕で
ある。11はシリコン基板の表面バ・・ノシベーション
膜、12け化合物半導体層の表面保護膜である。13け
シリコンからオーミ・ツクコンタクトをとるAt電極で
ある。14はn形のひ化ガリウム単結晶薄膜よりオーミ
ックコンタクトをと゛るAu−G’g/A%電極である
。15は配線である。
That is, 1 is the collector, 9 is the base, and 10 is the emitter. Reference numeral 11 designates a surface inoculation film of the silicon substrate, and reference numeral 12 designates a surface protection film of the compound semiconductor layer. This is an At electrode that makes ohmic contact with silicon. Reference numeral 14 denotes an Au-G'g/A% electrode having ohmic contact from an n-type gallium arsenide single crystal thin film. 15 is wiring.

第1図の構造ではバイポーラトランジスタのコレクタ部
に半導体レーザダイオードのn側が接続されている。ζ
らに半導体レーザダイオードのp側を正雷位に、バイポ
ーラトランジスタのエミッタを負電位はして、バイポー
ラトランジスタのベースにある電位を与えることにより
、半導体レーザダイオードに電流が流れてレーザ発振し
、この半導体光電子装置はレーザ光を出射する。出射す
るレーザ光の強度はバイポーラトランジスタのベース電
流で制御できる。
In the structure shown in FIG. 1, the n-side of the semiconductor laser diode is connected to the collector portion of the bipolar transistor. ζ
Furthermore, by setting the p-side of the semiconductor laser diode to a positive voltage potential and the emitter of the bipolar transistor to a negative potential, and applying a certain potential to the base of the bipolar transistor, a current flows through the semiconductor laser diode, causing laser oscillation. Semiconductor optoelectronic devices emit laser light. The intensity of the emitted laser light can be controlled by the base current of the bipolar transistor.

本実施例は半導体レーザと駆動用バイポーラトランジス
タを集積化した半導体光1子装置の一例7′; 、−1p1〇− 、<’”)、”、’1 である。バイポーラトランジスタの代わりに電界効果ト
ランジスタ、静電誘導トランジスタ等を用いても良い。
This embodiment is an example of a semiconductor optical single-device device 7'; , -1p10- , <'''), '', '1 in which a semiconductor laser and a driving bipolar transistor are integrated. A field effect transistor, a static induction transistor, etc. may be used instead of a bipolar transistor.

ζらに、複数の半導体レーザ、複数のトランジスタ集積
してもかまわない。
Alternatively, a plurality of semiconductor lasers and a plurality of transistors may be integrated.

〔実施例2〕 第2図に本発明の第2の実施例を示す。本実施例の特徴
は、半導体レーザとフォトダイオードと駆動用トランジ
スタを同一基板表面に集積化したところKある。
[Embodiment 2] FIG. 2 shows a second embodiment of the present invention. The feature of this embodiment is that a semiconductor laser, a photodiode, and a driving transistor are integrated on the same substrate surface.

第2図中17はp形シリコン単結晶基板である。17 in FIG. 2 is a p-type silicon single crystal substrate.

1′は前記p形シリコン単結晶基板上にエピタキシャル
成長したn形シリコン単結晶膜である。本n形シリコン
単結晶膜の仕様と使用目的は実施例1に記述した1のn
形シリコン単結晶基板と同一である。第2図中2′〜8
′および16′は実施例1に記述した2〜8および16
に対応する。18は素子分離用のP+形拡散層である。
1' is an n-type silicon single crystal film epitaxially grown on the p-type silicon single crystal substrate. The specifications and purpose of use of this n-type silicon single crystal film are as described in Example 1.
It is the same as a silicon single crystal substrate. 2' to 8 in Figure 2
' and 16' are 2 to 8 and 16 described in Example 1
corresponds to 18 is a P+ type diffusion layer for element isolation.

19,21.23はP+形拡散層、20.22は?+、
+形拡散層である。24はシリコンの表面パッシベーシ
ョン膜、25〜32けシリコンのそれぞれの領域からオ
ーミックコンタクトをとる金属雷、極である。1″がコ
レクタ、19がベーセ、20がエミッタであり、25,
26.27はそhぞれコレクタ、ペースエミッタの電極
であり、第1のバイポーラトランジスタを形成する。
19, 21.23 are P+ type diffusion layers, 20.22 is? +,
It is a + type diffusion layer. 24 is a silicon surface passivation film, and 25 to 32 are metal poles that make ohmic contact with each region of the silicon. 1″ is the collector, 19 is the base, 20 is the emitter, 25,
26 and 27 are collector and pace emitter electrodes, respectively, forming a first bipolar transistor.

1”’、21,22,28.29および30は前述の1
″、19゜20.25.26および27にそれぞれ対応
し、第2のバイポーラトランジスタを形成する。f″は
n形シリコン、23けp 形シリコン、61はn伸側電
極、32けp+形伸側電極、イ”、23.31および3
2でp+n+ォトダイオードを形成している。第1のバ
イポーラトランジスタが半導体レーザを、駆動し、第2
のバイポーラトランジスタがフォトダイオードを駆動す
る。この半導体光電子装置け1チヅプで受光と発光が行
な先るため、光ファイバによる信号伝送の中継器として
使えるばかりでなく光増幅器や光−光信号変換器などに
応用できる。
1"', 21, 22, 28.29 and 30 are the above 1
'', 19 degrees, 20 degrees, 25 points, 26 and 27, respectively, to form a second bipolar transistor. Side electrodes, A”, 23.31 and 3
2 forms a p+n+ photodiode. A first bipolar transistor drives a semiconductor laser, and a second bipolar transistor drives a semiconductor laser.
A bipolar transistor drives the photodiode. Since this semiconductor optoelectronic device receives and emits light in a single chip, it can be used not only as a repeater for signal transmission through optical fibers, but also in optical amplifiers, optical-to-optical signal converters, and the like.

フォトダイオードには本実施例ではp+n+ォトダイオ
ードを用いたが、他にpinフォト〃゛イオード、アバ
ランシェフォトダイオードも使用できる。
Although a p+n+ photodiode is used as the photodiode in this embodiment, a pin photodiode or an avalanche photodiode can also be used.

〔実施例3〕 本発明のも)一つの実施例を第3図に示す。この実施例
の特徴はシリコン基板の表裏両面を利用して半導体光電
子装置を構成したところにある。
[Embodiment 3] One embodiment of the present invention is shown in FIG. The feature of this embodiment is that a semiconductor optoelectronic device is constructed using both the front and back sides of a silicon substrate.

第3図において、35は表裏両面共に研磨鏡面仕上げき
れたp形シリコン単結晶基板である。基板の面方向は(
100)で不純物濃度は1×1011′crrL−3程
度である。64〜40および41は実施例1に示した2
〜8および16に対応し、シリコン単結晶基板裏側面で
レーザ素子を構成している。35はグラフオエピタキシ
ャル法にて、36〜40は一般のエピタキシャル法にて
それぞれ成長はせた化合物半導体薄膜である。41およ
び42は金属電極である。
In FIG. 3, numeral 35 is a p-type silicon single crystal substrate which has been polished to a mirror finish on both the front and back surfaces. The surface direction of the board is (
100) and the impurity concentration is about 1×1011'crrL-3. 64-40 and 41 are 2 shown in Example 1
8 and 16, a laser element is formed on the back side of a silicon single crystal substrate. 35 is a compound semiconductor thin film grown by a grapho-epitaxial method, and 36 to 40 are compound semiconductor thin films grown by a general epitaxial method. 41 and 42 are metal electrodes.

43け33のp−形シリコン単結晶基板裏側面に形成し
たM OS F ET OKetal−oxide−8
emiconthbctor Fieltl Bffe
ct Transistor)のn+形ソースヌはドレ
イン領域である。このn+形領領域イオン注入法又は拡
散法によシ形成する。44はゲート絶縁膜、45はゲー
ト電極、46は表面バツシベージョン用絶縁膜、47は
金属配線である。表側面に形成されたMOSFETは信
号処理および演算機能を有する電子回路を構成している
。裏側面に形成ばれている受光・発光素子を駆動する重
子素子をシリコン基板の表又は裏奈面に形成しても良い
MOS FET OKetal-oxide-8 formed on the back side of the p-type silicon single crystal substrate of 43 x 33
emiconthbctor Fieldl Bffe
The n+ type source region of the ct transistor is the drain region. This n+ type region is formed by ion implantation or diffusion. 44 is a gate insulating film, 45 is a gate electrode, 46 is an insulating film for surface buffing, and 47 is a metal wiring. The MOSFET formed on the front side constitutes an electronic circuit having signal processing and calculation functions. A heavy element for driving the light-receiving/emitting element formed on the back side may be formed on the front or back side of the silicon substrate.

受光素子も同様に形成して良い。これらの複数の素子は
有機的に結合されておシ、演算機能を有する電子回路で
制御ばれるため、光ファイバを用いた光信号伝送系の中
継器や端末のインターフェイスとして活用できる。
The light receiving element may also be formed in the same manner. These multiple elements are organically coupled and controlled by an electronic circuit with arithmetic functions, so they can be used as an interface for repeaters and terminals in optical signal transmission systems using optical fibers.

〔発明の効果〕〔Effect of the invention〕

本発明には次のような効果がある。 The present invention has the following effects.

■ 同一基板上に複数の発光素子、受光素子、駆動用電
子素子および信号処理演算素子を集積できる。また、集
積化することによって装置の小形化が容易となり、信頼
性の高い半導体光電子装置が得られる。
(2) A plurality of light emitting elements, light receiving elements, driving electronic elements, and signal processing arithmetic elements can be integrated on the same substrate. Further, by integrating the device, it becomes easier to downsize the device, and a highly reliable semiconductor optoelectronic device can be obtained.

■ 化合物半導体薄膜はシリコン基板上へ5ic12等
の不活性絶縁膜を中間層として形成されるので化合物半
導体薄嘆形成時に、シリコン単結晶基板中への不純物汚
染を避けられる。また化合物半導体薄膜より成る素子と
、シリコン基板表面上の電子素子とけ相互干渉が少なく
装置の電気的制御性が良い。また装置の設計がし易い。
(2) Since the compound semiconductor thin film is formed on the silicon substrate with an inert insulating film such as 5IC12 as an intermediate layer, impurity contamination into the silicon single crystal substrate can be avoided when forming the compound semiconductor thin film. Further, there is little mutual interference between the element made of the compound semiconductor thin film and the electronic element on the surface of the silicon substrate, and the electrical controllability of the device is good. Also, the device is easy to design.

■ グラフオエピタキシャル技術の導入により成長させ
た単結晶の格子不整合による結晶歪みや結晶欠陥の問題
がなくなり特性の良い素子が得られる。また多種類の化
合物半導体単結晶を成長できるため、多種類の半導体光
電子装置が構成できる。
■ The introduction of grapho-epitaxial technology eliminates the problems of crystal distortion and crystal defects caused by lattice mismatch in the grown single crystal, making it possible to obtain devices with good characteristics. Furthermore, since many types of compound semiconductor single crystals can be grown, many types of semiconductor optoelectronic devices can be constructed.

■ シリコン単結晶基板表面に形成するシリコン電子素
子やシリコンフォト〃゛イオードには既存のシリコンブ
レーナ技術が導入できるので、性能や信頼性はもちろん
、機能性に優れた素子を作ることができる。
■ Existing silicon brainer technology can be applied to silicon electronic devices and silicon photodiodes that are formed on the surface of silicon single crystal substrates, making it possible to create devices with excellent performance, reliability, and functionality.

■ シリコン単結晶基板は大量生産づれ、大面積のもの
が安価に入手できる。またシリコン単結晶基板の質も良
好である。したがってシリコン単結晶基板を使った半導
体光電子装置は歩留り良く大量生産できるので安価であ
る。
■ Silicon single-crystal substrates are being mass-produced and large-area substrates can be obtained at low cost. Furthermore, the quality of the silicon single crystal substrate is also good. Therefore, semiconductor optoelectronic devices using silicon single crystal substrates can be mass-produced with high yield and are therefore inexpensive.

【図面の簡単な説明】[Brief explanation of drawings]

第1図から第3図に本発明の具体的だ実施例の概略を水
子。第1図は同一シリコン基板上に半導体レーザ素子と
、駆動用シリコン電子素子を集積化した実施例を示す図
、第2図は半導体レーザ素子とシリコン受光素子と駆動
用シリコン電子素子を集積化した実施例を示す図、そし
て第3図はシリコン基板表面に半導体レーザーを示す図
、そして表面に駆動用素子および、信岩処理演算素子を
集積化した実施例をそれぞれ示す。 1・・n形シリコン単結晶基板 1′、1”、1“′・・n形シリコン単結晶2、2’、
 34・・非晶質絶縁膜 3、3.35・・ひ化ガリウム単結晶薄膜4.4’、3
6・・n形アルミニウム・ガリウム中ひ素早結晶 5.5’、37・・アルミニウム・カリウム・ひ素早結
晶 6、6’、 38・・p形アルミニウム・ガリウム・ひ
素早結晶 7、7’、 39 ・・n形ガリウムひ素8.8’、4
0 ・・p形ガリウムひ素9・・シリコンク形層 10・・シリコ/n形層 11・・表面ハッシペーション膜 12・・表面保護膜 13・・電極 14・・電極 15・・配線 16.16’、41・・電極 17・・p形シリコン単結晶基板 18・・p十形拡散層 19.21.23・・p十形拡散層 20.22・・n十形拡散層 24・・表面パッシベーション膜 25〜32・・金属電極 33・・p−形シリコン単結晶基板 42・・電極 43 ・・n十形ソースφドレイン領域44・・ゲート
絶縁膜 一17= 45・・ゲート電極 46・・表面パッシベーション用絶縁膜47・・金属配
線 以  上
Figures 1 to 3 outline specific embodiments of the present invention. Figure 1 shows an example in which a semiconductor laser element and a driving silicon electronic element are integrated on the same silicon substrate, and Figure 2 shows an example in which a semiconductor laser element, a silicon photodetector, and a driving silicon electronic element are integrated on the same silicon substrate. FIG. 3 is a diagram showing an embodiment, and FIG. 3 is a diagram showing a semiconductor laser on the surface of a silicon substrate, and an embodiment in which a driving element and a Shingan processing arithmetic element are integrated on the surface. 1... N-type silicon single crystal substrate 1', 1", 1"'... N-type silicon single crystal 2, 2',
34...Amorphous insulating film 3, 3.35...Gallium arsenide single crystal thin film 4.4', 3
6...N-type aluminum/gallium arsenic early crystal 5.5', 37...aluminum/potassium/arsenic early crystal 6,6', 38...p-type aluminum/gallium/arsenic early crystal 7,7', 39 ...N-type gallium arsenide 8.8', 4
0...p-type gallium arsenide 9...silicon layer 10...silico/n-type layer 11...surface hashipation film 12...surface protection film 13...electrode 14...electrode 15...wiring 16.16' , 41... Electrode 17... P type silicon single crystal substrate 18... P 10 type diffusion layer 19.21.23... P 10 type diffusion layer 20.22... N 10 type diffusion layer 24... Surface passivation film 25-32...Metal electrode 33...P-type silicon single crystal substrate 42...Electrode 43...nx-type source φ drain region 44...Gate insulating film 17=45...Gate electrode 46...Surface passivation Insulating film 47 for metal wiring or more

Claims (4)

【特許請求の範囲】[Claims] (1)シリコン単結晶基板と、該シリコン単結晶基板の
表又は裏面の全体又は一部に存在する非晶質絶縁膜と、
該非晶質絶縁膜表面の全体又は一部に存在する化合物半
導体薄膜と、該化合物半導体薄膜表面の全体又は一部に
存在する多層化合物半導体薄膜から成ることを特徴とす
る半導体光電子装置。
(1) a silicon single crystal substrate; an amorphous insulating film existing on the entire or part of the front or back surface of the silicon single crystal substrate;
A semiconductor optoelectronic device comprising a compound semiconductor thin film existing on the whole or a part of the surface of the amorphous insulating film and a multilayer compound semiconductor thin film existing on the whole or a part of the surface of the compound semiconductor thin film.
(2)前記化合物半導体薄膜は前記非晶質絶縁膜表面へ
グラフォエピタキシャル成長法により形成した単結晶薄
膜より成り、前記多層化合物半導体は前記化合物半導体
薄膜表面へエピタキシャル成長法により形成した多層の
単結晶薄膜より成ることを特徴とする特許請求の範囲第
1項に記載の半導体光電子装置。
(2) The compound semiconductor thin film is a single crystal thin film formed on the surface of the amorphous insulating film by a graphoepitaxial growth method, and the multilayer compound semiconductor is a multilayer single crystal thin film formed on the surface of the compound semiconductor thin film by an epitaxial growth method. A semiconductor optoelectronic device according to claim 1, characterized in that the semiconductor optoelectronic device comprises:
(3)前記シリコン単結晶基板と、前記化合物半導体薄
膜と、前記多層化合物半導体薄膜のうち少なくとも一つ
を、電子・光変換機能を有する発光素子又は光・電子変
換機能を有する受光素子の構成材料として用いたことを
特徴とする特許請求の範囲第1項に記載の半導体光電子
装置。
(3) At least one of the silicon single crystal substrate, the compound semiconductor thin film, and the multilayer compound semiconductor thin film is a constituent material of a light emitting element having an electron/light conversion function or a light receiving element having a light/electron conversion function. A semiconductor optoelectronic device according to claim 1, which is used as a semiconductor optoelectronic device.
(4)前記シリコン単結晶基板の表又は裏面に、シリコ
ン半導体より成る前記発光素子又は前記受光素子を作動
せしめる電子素子と、信号の処理および演算の機能を有
する複数の電子素子のうち少なくとも一つを形成したこ
とを特徴とする特許請求の範囲第1項又は第3項に記載
の半導体光電子装置。
(4) On the front or back surface of the silicon single crystal substrate, at least one of an electronic element that operates the light emitting element or the light receiving element made of a silicon semiconductor, and a plurality of electronic elements having signal processing and calculation functions. A semiconductor optoelectronic device according to claim 1 or 3, characterized in that the semiconductor optoelectronic device is formed with:
JP59230947A 1984-11-01 1984-11-01 Semiconductor photoelectronic device Pending JPS61108187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59230947A JPS61108187A (en) 1984-11-01 1984-11-01 Semiconductor photoelectronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59230947A JPS61108187A (en) 1984-11-01 1984-11-01 Semiconductor photoelectronic device

Publications (1)

Publication Number Publication Date
JPS61108187A true JPS61108187A (en) 1986-05-26

Family

ID=16915802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59230947A Pending JPS61108187A (en) 1984-11-01 1984-11-01 Semiconductor photoelectronic device

Country Status (1)

Country Link
JP (1) JPS61108187A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334994A (en) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp Photoelectric integrated circuit device and manufacture thereof
JPS63142861A (en) * 1986-12-05 1988-06-15 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
WO2001059837A1 (en) * 2000-02-10 2001-08-16 Motorola Inc. Integrated circuit
WO2002031872A1 (en) * 2000-10-12 2002-04-18 Motorola, Inc. Semiconductor amorphous layer formed with energy beam
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
WO2002033385A3 (en) * 2000-10-19 2002-08-29 Motorola Inc Biochip excitation and analysis structure
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
WO2002071458A3 (en) * 2001-02-28 2003-02-13 Motorola Inc Growth of compound semiconductor structures on patterned oxide films
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
EP2380251B1 (en) * 2009-01-20 2020-08-12 Raytheon Company Silicon based opto-electric circuits

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334994A (en) * 1986-07-29 1988-02-15 Mitsubishi Electric Corp Photoelectric integrated circuit device and manufacture thereof
JPS63142861A (en) * 1986-12-05 1988-06-15 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
WO2001059837A1 (en) * 2000-02-10 2001-08-16 Motorola Inc. Integrated circuit
WO2001059821A1 (en) * 2000-02-10 2001-08-16 Motorola Inc. A process for forming a semiconductor structure
WO2001059835A1 (en) * 2000-02-10 2001-08-16 Motorola, Inc. Semiconductor devices
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
WO2002031872A1 (en) * 2000-10-12 2002-04-18 Motorola, Inc. Semiconductor amorphous layer formed with energy beam
WO2002033385A3 (en) * 2000-10-19 2002-08-29 Motorola Inc Biochip excitation and analysis structure
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
WO2002071458A3 (en) * 2001-02-28 2003-02-13 Motorola Inc Growth of compound semiconductor structures on patterned oxide films
EP2380251B1 (en) * 2009-01-20 2020-08-12 Raytheon Company Silicon based opto-electric circuits

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