JPS59108326A - Integrated circuit - Google Patents

Abstract

PURPOSE:To suck up parasitic currents flowing through a substrate effectively, and to prevent a blocking oscillation by forming wiring layers to be connected to grounding potential to the upper layers of isolation regions isolating a plurality of transistors. CONSTITUTION:The power transistors 10 are isolated from adjacent transistors 10 by the p<+> isolation regions 11, 11. The Al wiring layers 12 are formed on the isolation regions 11, and the wiring layers 12 are brought to grounding potential collectively together with a pad 13 for grounding. When collector potential is made lower than base potential, the parasitic p-n-p transistor is formed among a p<+> base region 2, and n<-> epitaxial layer 5 and the p<+> isolation region 11 connected to the substrate 4. An increase, etc. more than grounding potential of the potential of the substrate 4 and the isolation regions 11 can be prevented because currents flowing through a substrate resistor 4a are sucked up by the presence of the wiring layers 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in integrated circuits, and more specifically, to propose an integrated circuit that can prevent blocking oscillations in integrated circuits for high output power amplifiers.

In integrated circuits for high-output power amplifiers, in order to drive the NPN power transistor into the saturation region and operate it, the high potential VC,! A phenomenon occurs in which the collector potential becomes lower than the base potential.

As a result, a parasitic PNP transistor is formed in the base-collector substrate, and as a result, a large amount of parasitic current flows into the substrate, and due to the existence of the substrate resistance, the potential of that part becomes higher than the ground potential. However, it has the disadvantage that it may cause abnormalities in the bias relationship and may cause blocking oscillation.

The present invention has been made to solve this problem, and the entire wiring layer to be connected to the ground potential is formed in the upper layer of the isolation region, thereby absorbing the parasitic current and preventing blocking oscillation. An object of the present invention is to provide an integrated circuit that prevents the occurrence of

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below based on drawings showing embodiments thereof. FIG. 1 is a plan pattern diagram of a mounting part of an integrated circuit according to the present invention, and FIG. 2 is a schematic cross-sectional structural diagram thereof. The elongated region shown surrounded by solid lines in FIG. 1 is an n-type collector region l, and is formed in multiple strips spaced apart by appropriate lengths. Kon
Between the collector regions 1.1 and 1.1, there is formed a wide p-shaped base region 2, which is shown surrounded by solid lines in FIG. An n+ type emitter region 3 (shown surrounded by solid lines in FIG. 1) is formed. Each of these regions], 2 and 3 are formed on an n-epitaxial layer 5 on a p-type substrate 4, as shown in FIG. In the upper layer of the collector region 1, base region 2, and emitter region 3, there is a collector wiring 7 (shown by a broken line in FIG. 1) and a base wiring 8 (also 2 Indicated by the dotted chain line.
j) and an emitter wiring 9 (also shown by a dashed line) are formed, and are connected to each of the lower collector region 11, base region 2, and emitter region 3 via contact holes shown with hatching. . The collector wiring 7 has a long lead-out portion 7 in a direction perpendicular to the direction in which the collector region 1 extends.
It is located on the ai- side and has a comb-like pattern in plan view. The emitter wiring 9 has a take-out part 9a' at the end opposite to the take-out part 7a, and has a comb-like pattern in plan view that meshes with the collector wiring 7. Then, the entire base wiring 8 is formed in a zigzag pattern so as to cover all the gaps between the comb patterns of the collector wiring 7 and the emitter wiring 9.

The lead-out portion 8a of the base wire 8 is formed at the other end on the same side as the lead-out portion of the emitter wire 9.

The power transistor IO having this unique configuration is the second
A p+ isolation region 11. I
IK is separated from adjacent transistors 10. And on this isolation region 11 there is an Al wiring J.
The wiring layer 12 is connected to the ground potential together with the grounding pad 13. Wiring layer 12
Although it is desirable to provide the wiring layer 12 so as to surround the area of one transistor, the wiring layer 12 itself or the wiring for guiding the wiring layer 12 to the pad 13 should be formed in a pattern so that it does not interfere with other wiring. It is necessary to establish In areas where this is not possible, as shown in FIG. 1 or FIG. 2, the buried layer 14 (indicated by a broken line in FIG. 1) is entirely formed on the substrate 4, and a portion is covered with AI! This fL may be used instead of the wiring layer 12.

When the collector potential becomes lower than the base potential, the p+ isolation region connected to the p+ base region 2, the n- epitaxial layer 5, and the substrate 4, as shown surrounded by circles in FIG. Parasitic PNP between 11
) a transistor is formed. Previously, it was sub-stray) 4
A current flows through the substrate resistor 4a [
However, in the case of the present invention, the presence of the wiring layer 12 connected to the ground potential causes the substrate resistance AaK style n to increase. As a result, the t-potential of the substrate 4 and the isolation region 11 can be prevented from becoming higher than the ground potential, and floating oscillation can be prevented.

As mentioned above, the integrated circuit according to the present invention is characterized in that a wiring layer to be connected to the ground potential is formed on the upper layer of the isolation region that completely isolates a plurality of transistors, so that the wiring layer that is connected to the ground potential flows to the substrate. It becomes possible to effectively absorb parasitic current and prevent floating oscillation.

Note that the present invention can also be applied to PNP type transistors.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention, in which FIG. 1 is a plan pattern diagram of a main part of an integrated circuit according to the invention, and FIG. 2 is a schematic cross-sectional structural diagram thereof. l...Collector area 2...Base area 3...Emitter area 4...Substrate 7...Collector wiring 8...Base wiring 9...Emitter wiring
10...Power transistor 11...Isolation region 12...Wiring layer 13.1.Grounding pad Patent applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Noboru Kono

Claims (1)

[Claims] 1. An integrated circuit characterized in that a wiring layer to be connected to a ground potential is formed above an isolation region separating a plurality of transistors.